sound/soc/codecs/tlv320aic3x.c

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This source file includes following definitions.
aic3x_volatile_reg
snd_soc_dapm_put_volsw_aic3x
mic_bias_event
aic3x_add_widgets
aic3x_hw_params
aic3x_prepare
aic3x_mute
aic3x_set_dai_sysclk
aic3x_set_dai_fmt
aic3x_set_dai_tdm_slot
aic3x_regulator_event
aic3x_set_power
aic3x_set_bias_level
aic3x_mono_init
aic3x_init
aic3x_is_shared_reset
aic3x_probe
aic3x_configure_ocmv
aic3x_i2c_probe
aic3x_i2c_remove
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * ALSA SoC TLV320AIC3X codec driver
   4  *
   5  * Author:      Vladimir Barinov, <vbarinov@embeddedalley.com>
   6  * Copyright:   (C) 2007 MontaVista Software, Inc., <source@mvista.com>
   7  *
   8  * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
   9  *
  10  * Notes:
  11  *  The AIC3X is a driver for a low power stereo audio
  12  *  codecs aic31, aic32, aic33, aic3007.
  13  *
  14  *  It supports full aic33 codec functionality.
  15  *  The compatibility with aic32, aic31 and aic3007 is as follows:
  16  *    aic32/aic3007    |        aic31
  17  *  ---------------------------------------
  18  *   MONO_LOUT -> N/A  |  MONO_LOUT -> N/A
  19  *                     |  IN1L -> LINE1L
  20  *                     |  IN1R -> LINE1R
  21  *                     |  IN2L -> LINE2L
  22  *                     |  IN2R -> LINE2R
  23  *                     |  MIC3L/R -> N/A
  24  *   truncated internal functionality in
  25  *   accordance with documentation
  26  *  ---------------------------------------
  27  *
  28  *  Hence the machine layer should disable unsupported inputs/outputs by
  29  *  snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
  30  */
  31 
  32 #include <linux/module.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/init.h>
  35 #include <linux/delay.h>
  36 #include <linux/pm.h>
  37 #include <linux/i2c.h>
  38 #include <linux/gpio.h>
  39 #include <linux/regulator/consumer.h>
  40 #include <linux/of.h>
  41 #include <linux/of_gpio.h>
  42 #include <linux/slab.h>
  43 #include <sound/core.h>
  44 #include <sound/pcm.h>
  45 #include <sound/pcm_params.h>
  46 #include <sound/soc.h>
  47 #include <sound/initval.h>
  48 #include <sound/tlv.h>
  49 #include <sound/tlv320aic3x.h>
  50 
  51 #include "tlv320aic3x.h"
  52 
  53 #define AIC3X_NUM_SUPPLIES      4
  54 static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
  55         "IOVDD",        /* I/O Voltage */
  56         "DVDD",         /* Digital Core Voltage */
  57         "AVDD",         /* Analog DAC Voltage */
  58         "DRVDD",        /* ADC Analog and Output Driver Voltage */
  59 };
  60 
  61 static LIST_HEAD(reset_list);
  62 
  63 struct aic3x_priv;
  64 
  65 struct aic3x_disable_nb {
  66         struct notifier_block nb;
  67         struct aic3x_priv *aic3x;
  68 };
  69 
  70 /* codec private data */
  71 struct aic3x_priv {
  72         struct snd_soc_component *component;
  73         struct regmap *regmap;
  74         struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
  75         struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
  76         struct aic3x_setup_data *setup;
  77         unsigned int sysclk;
  78         unsigned int dai_fmt;
  79         unsigned int tdm_delay;
  80         unsigned int slot_width;
  81         struct list_head list;
  82         int master;
  83         int gpio_reset;
  84         int power;
  85 #define AIC3X_MODEL_3X 0
  86 #define AIC3X_MODEL_33 1
  87 #define AIC3X_MODEL_3007 2
  88 #define AIC3X_MODEL_3104 3
  89         u16 model;
  90 
  91         /* Selects the micbias voltage */
  92         enum aic3x_micbias_voltage micbias_vg;
  93         /* Output Common-Mode Voltage */
  94         u8 ocmv;
  95 };
  96 
  97 static const struct reg_default aic3x_reg[] = {
  98         {   0, 0x00 }, {   1, 0x00 }, {   2, 0x00 }, {   3, 0x10 },
  99         {   4, 0x04 }, {   5, 0x00 }, {   6, 0x00 }, {   7, 0x00 },
 100         {   8, 0x00 }, {   9, 0x00 }, {  10, 0x00 }, {  11, 0x01 },
 101         {  12, 0x00 }, {  13, 0x00 }, {  14, 0x00 }, {  15, 0x80 },
 102         {  16, 0x80 }, {  17, 0xff }, {  18, 0xff }, {  19, 0x78 },
 103         {  20, 0x78 }, {  21, 0x78 }, {  22, 0x78 }, {  23, 0x78 },
 104         {  24, 0x78 }, {  25, 0x00 }, {  26, 0x00 }, {  27, 0xfe },
 105         {  28, 0x00 }, {  29, 0x00 }, {  30, 0xfe }, {  31, 0x00 },
 106         {  32, 0x18 }, {  33, 0x18 }, {  34, 0x00 }, {  35, 0x00 },
 107         {  36, 0x00 }, {  37, 0x00 }, {  38, 0x00 }, {  39, 0x00 },
 108         {  40, 0x00 }, {  41, 0x00 }, {  42, 0x00 }, {  43, 0x80 },
 109         {  44, 0x80 }, {  45, 0x00 }, {  46, 0x00 }, {  47, 0x00 },
 110         {  48, 0x00 }, {  49, 0x00 }, {  50, 0x00 }, {  51, 0x04 },
 111         {  52, 0x00 }, {  53, 0x00 }, {  54, 0x00 }, {  55, 0x00 },
 112         {  56, 0x00 }, {  57, 0x00 }, {  58, 0x04 }, {  59, 0x00 },
 113         {  60, 0x00 }, {  61, 0x00 }, {  62, 0x00 }, {  63, 0x00 },
 114         {  64, 0x00 }, {  65, 0x04 }, {  66, 0x00 }, {  67, 0x00 },
 115         {  68, 0x00 }, {  69, 0x00 }, {  70, 0x00 }, {  71, 0x00 },
 116         {  72, 0x04 }, {  73, 0x00 }, {  74, 0x00 }, {  75, 0x00 },
 117         {  76, 0x00 }, {  77, 0x00 }, {  78, 0x00 }, {  79, 0x00 },
 118         {  80, 0x00 }, {  81, 0x00 }, {  82, 0x00 }, {  83, 0x00 },
 119         {  84, 0x00 }, {  85, 0x00 }, {  86, 0x00 }, {  87, 0x00 },
 120         {  88, 0x00 }, {  89, 0x00 }, {  90, 0x00 }, {  91, 0x00 },
 121         {  92, 0x00 }, {  93, 0x00 }, {  94, 0x00 }, {  95, 0x00 },
 122         {  96, 0x00 }, {  97, 0x00 }, {  98, 0x00 }, {  99, 0x00 },
 123         { 100, 0x00 }, { 101, 0x00 }, { 102, 0x02 }, { 103, 0x00 },
 124         { 104, 0x00 }, { 105, 0x00 }, { 106, 0x00 }, { 107, 0x00 },
 125         { 108, 0x00 }, { 109, 0x00 },
 126 };
 127 
 128 static bool aic3x_volatile_reg(struct device *dev, unsigned int reg)
 129 {
 130         switch (reg) {
 131         case AIC3X_RESET:
 132                 return true;
 133         default:
 134                 return false;
 135         }
 136 }
 137 
 138 static const struct regmap_config aic3x_regmap = {
 139         .reg_bits = 8,
 140         .val_bits = 8,
 141 
 142         .max_register = DAC_ICC_ADJ,
 143         .reg_defaults = aic3x_reg,
 144         .num_reg_defaults = ARRAY_SIZE(aic3x_reg),
 145 
 146         .volatile_reg = aic3x_volatile_reg,
 147 
 148         .cache_type = REGCACHE_RBTREE,
 149 };
 150 
 151 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
 152         SOC_SINGLE_EXT(xname, reg, shift, mask, invert, \
 153                 snd_soc_dapm_get_volsw, snd_soc_dapm_put_volsw_aic3x)
 154 
 155 /*
 156  * All input lines are connected when !0xf and disconnected with 0xf bit field,
 157  * so we have to use specific dapm_put call for input mixer
 158  */
 159 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
 160                                         struct snd_ctl_elem_value *ucontrol)
 161 {
 162         struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
 163         struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
 164         struct soc_mixer_control *mc =
 165                 (struct soc_mixer_control *)kcontrol->private_value;
 166         unsigned int reg = mc->reg;
 167         unsigned int shift = mc->shift;
 168         int max = mc->max;
 169         unsigned int mask = (1 << fls(max)) - 1;
 170         unsigned int invert = mc->invert;
 171         unsigned short val;
 172         struct snd_soc_dapm_update update = {};
 173         int connect, change;
 174 
 175         val = (ucontrol->value.integer.value[0] & mask);
 176 
 177         mask = 0xf;
 178         if (val)
 179                 val = mask;
 180 
 181         connect = !!val;
 182 
 183         if (invert)
 184                 val = mask - val;
 185 
 186         mask <<= shift;
 187         val <<= shift;
 188 
 189         change = snd_soc_component_test_bits(component, reg, mask, val);
 190         if (change) {
 191                 update.kcontrol = kcontrol;
 192                 update.reg = reg;
 193                 update.mask = mask;
 194                 update.val = val;
 195 
 196                 snd_soc_dapm_mixer_update_power(dapm, kcontrol, connect,
 197                         &update);
 198         }
 199 
 200         return change;
 201 }
 202 
 203 /*
 204  * mic bias power on/off share the same register bits with
 205  * output voltage of mic bias. when power on mic bias, we
 206  * need reclaim it to voltage value.
 207  * 0x0 = Powered off
 208  * 0x1 = MICBIAS output is powered to 2.0V,
 209  * 0x2 = MICBIAS output is powered to 2.5V
 210  * 0x3 = MICBIAS output is connected to AVDD
 211  */
 212 static int mic_bias_event(struct snd_soc_dapm_widget *w,
 213         struct snd_kcontrol *kcontrol, int event)
 214 {
 215         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 216         struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
 217 
 218         switch (event) {
 219         case SND_SOC_DAPM_POST_PMU:
 220                 /* change mic bias voltage to user defined */
 221                 snd_soc_component_update_bits(component, MICBIAS_CTRL,
 222                                 MICBIAS_LEVEL_MASK,
 223                                 aic3x->micbias_vg << MICBIAS_LEVEL_SHIFT);
 224                 break;
 225 
 226         case SND_SOC_DAPM_PRE_PMD:
 227                 snd_soc_component_update_bits(component, MICBIAS_CTRL,
 228                                 MICBIAS_LEVEL_MASK, 0);
 229                 break;
 230         }
 231         return 0;
 232 }
 233 
 234 static const char * const aic3x_left_dac_mux[] = {
 235         "DAC_L1", "DAC_L3", "DAC_L2" };
 236 static SOC_ENUM_SINGLE_DECL(aic3x_left_dac_enum, DAC_LINE_MUX, 6,
 237                             aic3x_left_dac_mux);
 238 
 239 static const char * const aic3x_right_dac_mux[] = {
 240         "DAC_R1", "DAC_R3", "DAC_R2" };
 241 static SOC_ENUM_SINGLE_DECL(aic3x_right_dac_enum, DAC_LINE_MUX, 4,
 242                             aic3x_right_dac_mux);
 243 
 244 static const char * const aic3x_left_hpcom_mux[] = {
 245         "differential of HPLOUT", "constant VCM", "single-ended" };
 246 static SOC_ENUM_SINGLE_DECL(aic3x_left_hpcom_enum, HPLCOM_CFG, 4,
 247                             aic3x_left_hpcom_mux);
 248 
 249 static const char * const aic3x_right_hpcom_mux[] = {
 250         "differential of HPROUT", "constant VCM", "single-ended",
 251         "differential of HPLCOM", "external feedback" };
 252 static SOC_ENUM_SINGLE_DECL(aic3x_right_hpcom_enum, HPRCOM_CFG, 3,
 253                             aic3x_right_hpcom_mux);
 254 
 255 static const char * const aic3x_linein_mode_mux[] = {
 256         "single-ended", "differential" };
 257 static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_l_enum, LINE1L_2_LADC_CTRL, 7,
 258                             aic3x_linein_mode_mux);
 259 static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_r_enum, LINE1L_2_RADC_CTRL, 7,
 260                             aic3x_linein_mode_mux);
 261 static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_l_enum, LINE1R_2_LADC_CTRL, 7,
 262                             aic3x_linein_mode_mux);
 263 static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_r_enum, LINE1R_2_RADC_CTRL, 7,
 264                             aic3x_linein_mode_mux);
 265 static SOC_ENUM_SINGLE_DECL(aic3x_line2l_2_ldac_enum, LINE2L_2_LADC_CTRL, 7,
 266                             aic3x_linein_mode_mux);
 267 static SOC_ENUM_SINGLE_DECL(aic3x_line2r_2_rdac_enum, LINE2R_2_RADC_CTRL, 7,
 268                             aic3x_linein_mode_mux);
 269 
 270 static const char * const aic3x_adc_hpf[] = {
 271         "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
 272 static SOC_ENUM_DOUBLE_DECL(aic3x_adc_hpf_enum, AIC3X_CODEC_DFILT_CTRL, 6, 4,
 273                             aic3x_adc_hpf);
 274 
 275 static const char * const aic3x_agc_level[] = {
 276         "-5.5dB", "-8dB", "-10dB", "-12dB",
 277         "-14dB", "-17dB", "-20dB", "-24dB" };
 278 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_level_enum, LAGC_CTRL_A, 4,
 279                             aic3x_agc_level);
 280 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_level_enum, RAGC_CTRL_A, 4,
 281                             aic3x_agc_level);
 282 
 283 static const char * const aic3x_agc_attack[] = {
 284         "8ms", "11ms", "16ms", "20ms" };
 285 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_attack_enum, LAGC_CTRL_A, 2,
 286                             aic3x_agc_attack);
 287 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_attack_enum, RAGC_CTRL_A, 2,
 288                             aic3x_agc_attack);
 289 
 290 static const char * const aic3x_agc_decay[] = {
 291         "100ms", "200ms", "400ms", "500ms" };
 292 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_decay_enum, LAGC_CTRL_A, 0,
 293                             aic3x_agc_decay);
 294 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_decay_enum, RAGC_CTRL_A, 0,
 295                             aic3x_agc_decay);
 296 
 297 static const char * const aic3x_poweron_time[] = {
 298         "0us", "10us", "100us", "1ms", "10ms", "50ms",
 299         "100ms", "200ms", "400ms", "800ms", "2s", "4s" };
 300 static SOC_ENUM_SINGLE_DECL(aic3x_poweron_time_enum, HPOUT_POP_REDUCTION, 4,
 301                             aic3x_poweron_time);
 302 
 303 static const char * const aic3x_rampup_step[] = { "0ms", "1ms", "2ms", "4ms" };
 304 static SOC_ENUM_SINGLE_DECL(aic3x_rampup_step_enum, HPOUT_POP_REDUCTION, 2,
 305                             aic3x_rampup_step);
 306 
 307 /*
 308  * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
 309  */
 310 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
 311 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
 312 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
 313 /*
 314  * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
 315  * Step size is approximately 0.5 dB over most of the scale but increasing
 316  * near the very low levels.
 317  * Define dB scale so that it is mostly correct for range about -55 to 0 dB
 318  * but having increasing dB difference below that (and where it doesn't count
 319  * so much). This setting shows -50 dB (actual is -50.3 dB) for register
 320  * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
 321  */
 322 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
 323 
 324 /* Output volumes. From 0 to 9 dB in 1 dB steps */
 325 static const DECLARE_TLV_DB_SCALE(out_tlv, 0, 100, 0);
 326 
 327 static const struct snd_kcontrol_new aic3x_snd_controls[] = {
 328         /* Output */
 329         SOC_DOUBLE_R_TLV("PCM Playback Volume",
 330                          LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
 331 
 332         /*
 333          * Output controls that map to output mixer switches. Note these are
 334          * only for swapped L-to-R and R-to-L routes. See below stereo controls
 335          * for direct L-to-L and R-to-R routes.
 336          */
 337         SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
 338                        PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
 339         SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
 340                        DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
 341 
 342         SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
 343                        PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
 344         SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
 345                        DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
 346 
 347         SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
 348                        PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
 349         SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
 350                        DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
 351 
 352         SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
 353                        PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
 354         SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
 355                        DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
 356 
 357         SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
 358                        PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
 359         SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
 360                        DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
 361 
 362         SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
 363                        PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
 364         SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
 365                        DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
 366 
 367         /* Stereo output controls for direct L-to-L and R-to-R routes */
 368         SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
 369                          PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
 370                          0, 118, 1, output_stage_tlv),
 371         SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
 372                          DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
 373                          0, 118, 1, output_stage_tlv),
 374 
 375         SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
 376                          PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
 377                          0, 118, 1, output_stage_tlv),
 378         SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
 379                          DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
 380                          0, 118, 1, output_stage_tlv),
 381 
 382         SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
 383                          PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
 384                          0, 118, 1, output_stage_tlv),
 385         SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
 386                          DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
 387                          0, 118, 1, output_stage_tlv),
 388 
 389         /* Output pin controls */
 390         SOC_DOUBLE_R_TLV("Line Playback Volume", LLOPM_CTRL, RLOPM_CTRL, 4,
 391                          9, 0, out_tlv),
 392         SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
 393                      0x01, 0),
 394         SOC_DOUBLE_R_TLV("HP Playback Volume", HPLOUT_CTRL, HPROUT_CTRL, 4,
 395                          9, 0, out_tlv),
 396         SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
 397                      0x01, 0),
 398         SOC_DOUBLE_R_TLV("HPCOM Playback Volume", HPLCOM_CTRL, HPRCOM_CTRL,
 399                          4, 9, 0, out_tlv),
 400         SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
 401                      0x01, 0),
 402 
 403         /*
 404          * Note: enable Automatic input Gain Controller with care. It can
 405          * adjust PGA to max value when ADC is on and will never go back.
 406         */
 407         SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
 408         SOC_ENUM("Left AGC Target level", aic3x_lagc_level_enum),
 409         SOC_ENUM("Right AGC Target level", aic3x_ragc_level_enum),
 410         SOC_ENUM("Left AGC Attack time", aic3x_lagc_attack_enum),
 411         SOC_ENUM("Right AGC Attack time", aic3x_ragc_attack_enum),
 412         SOC_ENUM("Left AGC Decay time", aic3x_lagc_decay_enum),
 413         SOC_ENUM("Right AGC Decay time", aic3x_ragc_decay_enum),
 414 
 415         /* De-emphasis */
 416         SOC_DOUBLE("De-emphasis Switch", AIC3X_CODEC_DFILT_CTRL, 2, 0, 0x01, 0),
 417 
 418         /* Input */
 419         SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
 420                          0, 119, 0, adc_tlv),
 421         SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
 422 
 423         SOC_ENUM("ADC HPF Cut-off", aic3x_adc_hpf_enum),
 424 
 425         /* Pop reduction */
 426         SOC_ENUM("Output Driver Power-On time", aic3x_poweron_time_enum),
 427         SOC_ENUM("Output Driver Ramp-up step", aic3x_rampup_step_enum),
 428 };
 429 
 430 /* For other than tlv320aic3104 */
 431 static const struct snd_kcontrol_new aic3x_extra_snd_controls[] = {
 432         /*
 433          * Output controls that map to output mixer switches. Note these are
 434          * only for swapped L-to-R and R-to-L routes. See below stereo controls
 435          * for direct L-to-L and R-to-R routes.
 436          */
 437         SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
 438                        LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
 439 
 440         SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
 441                        LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
 442 
 443         SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
 444                        LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
 445 
 446         SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
 447                        LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
 448 
 449         SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
 450                        LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
 451 
 452         SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
 453                        LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
 454 
 455         /* Stereo output controls for direct L-to-L and R-to-R routes */
 456         SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
 457                          LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
 458                          0, 118, 1, output_stage_tlv),
 459 
 460         SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
 461                          LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
 462                          0, 118, 1, output_stage_tlv),
 463 
 464         SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
 465                          LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
 466                          0, 118, 1, output_stage_tlv),
 467 };
 468 
 469 static const struct snd_kcontrol_new aic3x_mono_controls[] = {
 470         SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
 471                          LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
 472                          0, 118, 1, output_stage_tlv),
 473         SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
 474                          PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
 475                          0, 118, 1, output_stage_tlv),
 476         SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
 477                          DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
 478                          0, 118, 1, output_stage_tlv),
 479 
 480         SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
 481         SOC_SINGLE_TLV("Mono Playback Volume", MONOLOPM_CTRL, 4, 9, 0,
 482                         out_tlv),
 483 
 484 };
 485 
 486 /*
 487  * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
 488  */
 489 static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
 490 
 491 static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
 492         SOC_DOUBLE_TLV("Class-D Playback Volume", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
 493 
 494 /* Left DAC Mux */
 495 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
 496 SOC_DAPM_ENUM("Route", aic3x_left_dac_enum);
 497 
 498 /* Right DAC Mux */
 499 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
 500 SOC_DAPM_ENUM("Route", aic3x_right_dac_enum);
 501 
 502 /* Left HPCOM Mux */
 503 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
 504 SOC_DAPM_ENUM("Route", aic3x_left_hpcom_enum);
 505 
 506 /* Right HPCOM Mux */
 507 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
 508 SOC_DAPM_ENUM("Route", aic3x_right_hpcom_enum);
 509 
 510 /* Left Line Mixer */
 511 static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
 512         SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
 513         SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
 514         SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
 515         SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
 516         /* Not on tlv320aic3104 */
 517         SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
 518         SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
 519 };
 520 
 521 /* Right Line Mixer */
 522 static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
 523         SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
 524         SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
 525         SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
 526         SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
 527         /* Not on tlv320aic3104 */
 528         SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
 529         SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
 530 };
 531 
 532 /* Mono Mixer */
 533 static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
 534         SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
 535         SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
 536         SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
 537         SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
 538         SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
 539         SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
 540 };
 541 
 542 /* Left HP Mixer */
 543 static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
 544         SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
 545         SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
 546         SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
 547         SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
 548         /* Not on tlv320aic3104 */
 549         SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
 550         SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
 551 };
 552 
 553 /* Right HP Mixer */
 554 static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
 555         SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
 556         SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
 557         SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
 558         SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
 559         /* Not on tlv320aic3104 */
 560         SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
 561         SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
 562 };
 563 
 564 /* Left HPCOM Mixer */
 565 static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
 566         SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
 567         SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
 568         SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
 569         SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
 570         /* Not on tlv320aic3104 */
 571         SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
 572         SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
 573 };
 574 
 575 /* Right HPCOM Mixer */
 576 static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
 577         SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
 578         SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
 579         SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
 580         SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
 581         /* Not on tlv320aic3104 */
 582         SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
 583         SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
 584 };
 585 
 586 /* Left PGA Mixer */
 587 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
 588         SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
 589         SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
 590         SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
 591         SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
 592         SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
 593 };
 594 
 595 /* Right PGA Mixer */
 596 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
 597         SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
 598         SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
 599         SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
 600         SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
 601         SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
 602 };
 603 
 604 /* Left PGA Mixer for tlv320aic3104 */
 605 static const struct snd_kcontrol_new aic3104_left_pga_mixer_controls[] = {
 606         SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
 607         SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
 608         SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
 609         SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
 610 };
 611 
 612 /* Right PGA Mixer for tlv320aic3104 */
 613 static const struct snd_kcontrol_new aic3104_right_pga_mixer_controls[] = {
 614         SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
 615         SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
 616         SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
 617         SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
 618 };
 619 
 620 /* Left Line1 Mux */
 621 static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls =
 622 SOC_DAPM_ENUM("Route", aic3x_line1l_2_l_enum);
 623 static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls =
 624 SOC_DAPM_ENUM("Route", aic3x_line1l_2_r_enum);
 625 
 626 /* Right Line1 Mux */
 627 static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls =
 628 SOC_DAPM_ENUM("Route", aic3x_line1r_2_r_enum);
 629 static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls =
 630 SOC_DAPM_ENUM("Route", aic3x_line1r_2_l_enum);
 631 
 632 /* Left Line2 Mux */
 633 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
 634 SOC_DAPM_ENUM("Route", aic3x_line2l_2_ldac_enum);
 635 
 636 /* Right Line2 Mux */
 637 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
 638 SOC_DAPM_ENUM("Route", aic3x_line2r_2_rdac_enum);
 639 
 640 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
 641         /* Left DAC to Left Outputs */
 642         SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
 643         SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
 644                          &aic3x_left_dac_mux_controls),
 645         SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
 646                          &aic3x_left_hpcom_mux_controls),
 647         SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
 648         SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
 649         SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
 650 
 651         /* Right DAC to Right Outputs */
 652         SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
 653         SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
 654                          &aic3x_right_dac_mux_controls),
 655         SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
 656                          &aic3x_right_hpcom_mux_controls),
 657         SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
 658         SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
 659         SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
 660 
 661         /* Inputs to Left ADC */
 662         SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
 663         SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
 664                          &aic3x_left_line1l_mux_controls),
 665         SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
 666                          &aic3x_left_line1r_mux_controls),
 667 
 668         /* Inputs to Right ADC */
 669         SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
 670                          LINE1R_2_RADC_CTRL, 2, 0),
 671         SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
 672                          &aic3x_right_line1l_mux_controls),
 673         SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
 674                          &aic3x_right_line1r_mux_controls),
 675 
 676         /* Mic Bias */
 677         SND_SOC_DAPM_SUPPLY("Mic Bias", MICBIAS_CTRL, 6, 0,
 678                          mic_bias_event,
 679                          SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 680 
 681         SND_SOC_DAPM_OUTPUT("LLOUT"),
 682         SND_SOC_DAPM_OUTPUT("RLOUT"),
 683         SND_SOC_DAPM_OUTPUT("HPLOUT"),
 684         SND_SOC_DAPM_OUTPUT("HPROUT"),
 685         SND_SOC_DAPM_OUTPUT("HPLCOM"),
 686         SND_SOC_DAPM_OUTPUT("HPRCOM"),
 687 
 688         SND_SOC_DAPM_INPUT("LINE1L"),
 689         SND_SOC_DAPM_INPUT("LINE1R"),
 690 
 691         /*
 692          * Virtual output pin to detection block inside codec. This can be
 693          * used to keep codec bias on if gpio or detection features are needed.
 694          * Force pin on or construct a path with an input jack and mic bias
 695          * widgets.
 696          */
 697         SND_SOC_DAPM_OUTPUT("Detection"),
 698 };
 699 
 700 /* For other than tlv320aic3104 */
 701 static const struct snd_soc_dapm_widget aic3x_extra_dapm_widgets[] = {
 702         /* Inputs to Left ADC */
 703         SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
 704                            &aic3x_left_pga_mixer_controls[0],
 705                            ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
 706         SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
 707                          &aic3x_left_line2_mux_controls),
 708 
 709         /* Inputs to Right ADC */
 710         SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
 711                            &aic3x_right_pga_mixer_controls[0],
 712                            ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
 713         SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
 714                          &aic3x_right_line2_mux_controls),
 715 
 716         /*
 717          * Not a real mic bias widget but similar function. This is for dynamic
 718          * control of GPIO1 digital mic modulator clock output function when
 719          * using digital mic.
 720          */
 721         SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
 722                          AIC3X_GPIO1_REG, 4, 0xf,
 723                          AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
 724                          AIC3X_GPIO1_FUNC_DISABLED),
 725 
 726         /*
 727          * Also similar function like mic bias. Selects digital mic with
 728          * configurable oversampling rate instead of ADC converter.
 729          */
 730         SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
 731                          AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
 732         SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
 733                          AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
 734         SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
 735                          AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
 736 
 737         /* Output mixers */
 738         SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
 739                            &aic3x_left_line_mixer_controls[0],
 740                            ARRAY_SIZE(aic3x_left_line_mixer_controls)),
 741         SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
 742                            &aic3x_right_line_mixer_controls[0],
 743                            ARRAY_SIZE(aic3x_right_line_mixer_controls)),
 744         SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
 745                            &aic3x_left_hp_mixer_controls[0],
 746                            ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
 747         SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
 748                            &aic3x_right_hp_mixer_controls[0],
 749                            ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
 750         SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
 751                            &aic3x_left_hpcom_mixer_controls[0],
 752                            ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
 753         SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
 754                            &aic3x_right_hpcom_mixer_controls[0],
 755                            ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
 756 
 757         SND_SOC_DAPM_INPUT("MIC3L"),
 758         SND_SOC_DAPM_INPUT("MIC3R"),
 759         SND_SOC_DAPM_INPUT("LINE2L"),
 760         SND_SOC_DAPM_INPUT("LINE2R"),
 761 };
 762 
 763 /* For tlv320aic3104 */
 764 static const struct snd_soc_dapm_widget aic3104_extra_dapm_widgets[] = {
 765         /* Inputs to Left ADC */
 766         SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
 767                            &aic3104_left_pga_mixer_controls[0],
 768                            ARRAY_SIZE(aic3104_left_pga_mixer_controls)),
 769 
 770         /* Inputs to Right ADC */
 771         SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
 772                            &aic3104_right_pga_mixer_controls[0],
 773                            ARRAY_SIZE(aic3104_right_pga_mixer_controls)),
 774 
 775         /* Output mixers */
 776         SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
 777                            &aic3x_left_line_mixer_controls[0],
 778                            ARRAY_SIZE(aic3x_left_line_mixer_controls) - 2),
 779         SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
 780                            &aic3x_right_line_mixer_controls[0],
 781                            ARRAY_SIZE(aic3x_right_line_mixer_controls) - 2),
 782         SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
 783                            &aic3x_left_hp_mixer_controls[0],
 784                            ARRAY_SIZE(aic3x_left_hp_mixer_controls) - 2),
 785         SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
 786                            &aic3x_right_hp_mixer_controls[0],
 787                            ARRAY_SIZE(aic3x_right_hp_mixer_controls) - 2),
 788         SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
 789                            &aic3x_left_hpcom_mixer_controls[0],
 790                            ARRAY_SIZE(aic3x_left_hpcom_mixer_controls) - 2),
 791         SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
 792                            &aic3x_right_hpcom_mixer_controls[0],
 793                            ARRAY_SIZE(aic3x_right_hpcom_mixer_controls) - 2),
 794 
 795         SND_SOC_DAPM_INPUT("MIC2L"),
 796         SND_SOC_DAPM_INPUT("MIC2R"),
 797 };
 798 
 799 static const struct snd_soc_dapm_widget aic3x_dapm_mono_widgets[] = {
 800         /* Mono Output */
 801         SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
 802 
 803         SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
 804                            &aic3x_mono_mixer_controls[0],
 805                            ARRAY_SIZE(aic3x_mono_mixer_controls)),
 806 
 807         SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
 808 };
 809 
 810 static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
 811         /* Class-D outputs */
 812         SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
 813         SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
 814 
 815         SND_SOC_DAPM_OUTPUT("SPOP"),
 816         SND_SOC_DAPM_OUTPUT("SPOM"),
 817 };
 818 
 819 static const struct snd_soc_dapm_route intercon[] = {
 820         /* Left Input */
 821         {"Left Line1L Mux", "single-ended", "LINE1L"},
 822         {"Left Line1L Mux", "differential", "LINE1L"},
 823         {"Left Line1R Mux", "single-ended", "LINE1R"},
 824         {"Left Line1R Mux", "differential", "LINE1R"},
 825 
 826         {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
 827         {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
 828 
 829         {"Left ADC", NULL, "Left PGA Mixer"},
 830 
 831         /* Right Input */
 832         {"Right Line1R Mux", "single-ended", "LINE1R"},
 833         {"Right Line1R Mux", "differential", "LINE1R"},
 834         {"Right Line1L Mux", "single-ended", "LINE1L"},
 835         {"Right Line1L Mux", "differential", "LINE1L"},
 836 
 837         {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
 838         {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
 839 
 840         {"Right ADC", NULL, "Right PGA Mixer"},
 841 
 842         /* Left DAC Output */
 843         {"Left DAC Mux", "DAC_L1", "Left DAC"},
 844         {"Left DAC Mux", "DAC_L2", "Left DAC"},
 845         {"Left DAC Mux", "DAC_L3", "Left DAC"},
 846 
 847         /* Right DAC Output */
 848         {"Right DAC Mux", "DAC_R1", "Right DAC"},
 849         {"Right DAC Mux", "DAC_R2", "Right DAC"},
 850         {"Right DAC Mux", "DAC_R3", "Right DAC"},
 851 
 852         /* Left Line Output */
 853         {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
 854         {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
 855         {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
 856         {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
 857 
 858         {"Left Line Out", NULL, "Left Line Mixer"},
 859         {"Left Line Out", NULL, "Left DAC Mux"},
 860         {"LLOUT", NULL, "Left Line Out"},
 861 
 862         /* Right Line Output */
 863         {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
 864         {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
 865         {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
 866         {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
 867 
 868         {"Right Line Out", NULL, "Right Line Mixer"},
 869         {"Right Line Out", NULL, "Right DAC Mux"},
 870         {"RLOUT", NULL, "Right Line Out"},
 871 
 872         /* Left HP Output */
 873         {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
 874         {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
 875         {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
 876         {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
 877 
 878         {"Left HP Out", NULL, "Left HP Mixer"},
 879         {"Left HP Out", NULL, "Left DAC Mux"},
 880         {"HPLOUT", NULL, "Left HP Out"},
 881 
 882         /* Right HP Output */
 883         {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
 884         {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
 885         {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
 886         {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
 887 
 888         {"Right HP Out", NULL, "Right HP Mixer"},
 889         {"Right HP Out", NULL, "Right DAC Mux"},
 890         {"HPROUT", NULL, "Right HP Out"},
 891 
 892         /* Left HPCOM Output */
 893         {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
 894         {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
 895         {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
 896         {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
 897 
 898         {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
 899         {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
 900         {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
 901         {"Left HP Com", NULL, "Left HPCOM Mux"},
 902         {"HPLCOM", NULL, "Left HP Com"},
 903 
 904         /* Right HPCOM Output */
 905         {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
 906         {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
 907         {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
 908         {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
 909 
 910         {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
 911         {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
 912         {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
 913         {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
 914         {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
 915         {"Right HP Com", NULL, "Right HPCOM Mux"},
 916         {"HPRCOM", NULL, "Right HP Com"},
 917 };
 918 
 919 /* For other than tlv320aic3104 */
 920 static const struct snd_soc_dapm_route intercon_extra[] = {
 921         /* Left Input */
 922         {"Left Line2L Mux", "single-ended", "LINE2L"},
 923         {"Left Line2L Mux", "differential", "LINE2L"},
 924 
 925         {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
 926         {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
 927         {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
 928 
 929         {"Left ADC", NULL, "GPIO1 dmic modclk"},
 930 
 931         /* Right Input */
 932         {"Right Line2R Mux", "single-ended", "LINE2R"},
 933         {"Right Line2R Mux", "differential", "LINE2R"},
 934 
 935         {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
 936         {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
 937         {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
 938 
 939         {"Right ADC", NULL, "GPIO1 dmic modclk"},
 940 
 941         /*
 942          * Logical path between digital mic enable and GPIO1 modulator clock
 943          * output function
 944          */
 945         {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
 946         {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
 947         {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
 948 
 949         /* Left Line Output */
 950         {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
 951         {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
 952 
 953         /* Right Line Output */
 954         {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
 955         {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
 956 
 957         /* Left HP Output */
 958         {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
 959         {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
 960 
 961         /* Right HP Output */
 962         {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
 963         {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
 964 
 965         /* Left HPCOM Output */
 966         {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
 967         {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
 968 
 969         /* Right HPCOM Output */
 970         {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
 971         {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
 972 };
 973 
 974 /* For tlv320aic3104 */
 975 static const struct snd_soc_dapm_route intercon_extra_3104[] = {
 976         /* Left Input */
 977         {"Left PGA Mixer", "Mic2L Switch", "MIC2L"},
 978         {"Left PGA Mixer", "Mic2R Switch", "MIC2R"},
 979 
 980         /* Right Input */
 981         {"Right PGA Mixer", "Mic2L Switch", "MIC2L"},
 982         {"Right PGA Mixer", "Mic2R Switch", "MIC2R"},
 983 };
 984 
 985 static const struct snd_soc_dapm_route intercon_mono[] = {
 986         /* Mono Output */
 987         {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
 988         {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
 989         {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
 990         {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
 991         {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
 992         {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
 993         {"Mono Out", NULL, "Mono Mixer"},
 994         {"MONO_LOUT", NULL, "Mono Out"},
 995 };
 996 
 997 static const struct snd_soc_dapm_route intercon_3007[] = {
 998         /* Class-D outputs */
 999         {"Left Class-D Out", NULL, "Left Line Out"},
1000         {"Right Class-D Out", NULL, "Left Line Out"},
1001         {"SPOP", NULL, "Left Class-D Out"},
1002         {"SPOM", NULL, "Right Class-D Out"},
1003 };
1004 
1005 static int aic3x_add_widgets(struct snd_soc_component *component)
1006 {
1007         struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1008         struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1009 
1010         switch (aic3x->model) {
1011         case AIC3X_MODEL_3X:
1012         case AIC3X_MODEL_33:
1013                 snd_soc_dapm_new_controls(dapm, aic3x_extra_dapm_widgets,
1014                                           ARRAY_SIZE(aic3x_extra_dapm_widgets));
1015                 snd_soc_dapm_add_routes(dapm, intercon_extra,
1016                                         ARRAY_SIZE(intercon_extra));
1017                 snd_soc_dapm_new_controls(dapm, aic3x_dapm_mono_widgets,
1018                         ARRAY_SIZE(aic3x_dapm_mono_widgets));
1019                 snd_soc_dapm_add_routes(dapm, intercon_mono,
1020                                         ARRAY_SIZE(intercon_mono));
1021                 break;
1022         case AIC3X_MODEL_3007:
1023                 snd_soc_dapm_new_controls(dapm, aic3x_extra_dapm_widgets,
1024                                           ARRAY_SIZE(aic3x_extra_dapm_widgets));
1025                 snd_soc_dapm_add_routes(dapm, intercon_extra,
1026                                         ARRAY_SIZE(intercon_extra));
1027                 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
1028                         ARRAY_SIZE(aic3007_dapm_widgets));
1029                 snd_soc_dapm_add_routes(dapm, intercon_3007,
1030                                         ARRAY_SIZE(intercon_3007));
1031                 break;
1032         case AIC3X_MODEL_3104:
1033                 snd_soc_dapm_new_controls(dapm, aic3104_extra_dapm_widgets,
1034                                 ARRAY_SIZE(aic3104_extra_dapm_widgets));
1035                 snd_soc_dapm_add_routes(dapm, intercon_extra_3104,
1036                                 ARRAY_SIZE(intercon_extra_3104));
1037                 break;
1038         }
1039 
1040         return 0;
1041 }
1042 
1043 static int aic3x_hw_params(struct snd_pcm_substream *substream,
1044                            struct snd_pcm_hw_params *params,
1045                            struct snd_soc_dai *dai)
1046 {
1047         struct snd_soc_component *component = dai->component;
1048         struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1049         int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
1050         u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
1051         u16 d, pll_d = 1;
1052         int clk;
1053         int width = aic3x->slot_width;
1054 
1055         if (!width)
1056                 width = params_width(params);
1057 
1058         /* select data word length */
1059         data = snd_soc_component_read32(component, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
1060         switch (width) {
1061         case 16:
1062                 break;
1063         case 20:
1064                 data |= (0x01 << 4);
1065                 break;
1066         case 24:
1067                 data |= (0x02 << 4);
1068                 break;
1069         case 32:
1070                 data |= (0x03 << 4);
1071                 break;
1072         }
1073         snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLB, data);
1074 
1075         /* Fsref can be 44100 or 48000 */
1076         fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
1077 
1078         /* Try to find a value for Q which allows us to bypass the PLL and
1079          * generate CODEC_CLK directly. */
1080         for (pll_q = 2; pll_q < 18; pll_q++)
1081                 if (aic3x->sysclk / (128 * pll_q) == fsref) {
1082                         bypass_pll = 1;
1083                         break;
1084                 }
1085 
1086         if (bypass_pll) {
1087                 pll_q &= 0xf;
1088                 snd_soc_component_write(component, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
1089                 snd_soc_component_write(component, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
1090                 /* disable PLL if it is bypassed */
1091                 snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0);
1092 
1093         } else {
1094                 snd_soc_component_write(component, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
1095                 /* enable PLL when it is used */
1096                 snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG,
1097                                     PLL_ENABLE, PLL_ENABLE);
1098         }
1099 
1100         /* Route Left DAC to left channel input and
1101          * right DAC to right channel input */
1102         data = (LDAC2LCH | RDAC2RCH);
1103         data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
1104         if (params_rate(params) >= 64000)
1105                 data |= DUAL_RATE_MODE;
1106         snd_soc_component_write(component, AIC3X_CODEC_DATAPATH_REG, data);
1107 
1108         /* codec sample rate select */
1109         data = (fsref * 20) / params_rate(params);
1110         if (params_rate(params) < 64000)
1111                 data /= 2;
1112         data /= 5;
1113         data -= 2;
1114         data |= (data << 4);
1115         snd_soc_component_write(component, AIC3X_SAMPLE_RATE_SEL_REG, data);
1116 
1117         if (bypass_pll)
1118                 return 0;
1119 
1120         /* Use PLL, compute appropriate setup for j, d, r and p, the closest
1121          * one wins the game. Try with d==0 first, next with d!=0.
1122          * Constraints for j are according to the datasheet.
1123          * The sysclk is divided by 1000 to prevent integer overflows.
1124          */
1125 
1126         codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
1127 
1128         for (r = 1; r <= 16; r++)
1129                 for (p = 1; p <= 8; p++) {
1130                         for (j = 4; j <= 55; j++) {
1131                                 /* This is actually 1000*((j+(d/10000))*r)/p
1132                                  * The term had to be converted to get
1133                                  * rid of the division by 10000; d = 0 here
1134                                  */
1135                                 int tmp_clk = (1000 * j * r) / p;
1136 
1137                                 /* Check whether this values get closer than
1138                                  * the best ones we had before
1139                                  */
1140                                 if (abs(codec_clk - tmp_clk) <
1141                                         abs(codec_clk - last_clk)) {
1142                                         pll_j = j; pll_d = 0;
1143                                         pll_r = r; pll_p = p;
1144                                         last_clk = tmp_clk;
1145                                 }
1146 
1147                                 /* Early exit for exact matches */
1148                                 if (tmp_clk == codec_clk)
1149                                         goto found;
1150                         }
1151                 }
1152 
1153         /* try with d != 0 */
1154         for (p = 1; p <= 8; p++) {
1155                 j = codec_clk * p / 1000;
1156 
1157                 if (j < 4 || j > 11)
1158                         continue;
1159 
1160                 /* do not use codec_clk here since we'd loose precision */
1161                 d = ((2048 * p * fsref) - j * aic3x->sysclk)
1162                         * 100 / (aic3x->sysclk/100);
1163 
1164                 clk = (10000 * j + d) / (10 * p);
1165 
1166                 /* check whether this values get closer than the best
1167                  * ones we had before */
1168                 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
1169                         pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
1170                         last_clk = clk;
1171                 }
1172 
1173                 /* Early exit for exact matches */
1174                 if (clk == codec_clk)
1175                         goto found;
1176         }
1177 
1178         if (last_clk == 0) {
1179                 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
1180                 return -EINVAL;
1181         }
1182 
1183 found:
1184         snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG, PLLP_MASK, pll_p);
1185         snd_soc_component_write(component, AIC3X_OVRF_STATUS_AND_PLLR_REG,
1186                       pll_r << PLLR_SHIFT);
1187         snd_soc_component_write(component, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
1188         snd_soc_component_write(component, AIC3X_PLL_PROGC_REG,
1189                       (pll_d >> 6) << PLLD_MSB_SHIFT);
1190         snd_soc_component_write(component, AIC3X_PLL_PROGD_REG,
1191                       (pll_d & 0x3F) << PLLD_LSB_SHIFT);
1192 
1193         return 0;
1194 }
1195 
1196 static int aic3x_prepare(struct snd_pcm_substream *substream,
1197                          struct snd_soc_dai *dai)
1198 {
1199         struct snd_soc_component *component = dai->component;
1200         struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1201         int delay = 0;
1202         int width = aic3x->slot_width;
1203 
1204         if (!width)
1205                 width = substream->runtime->sample_bits;
1206 
1207         /* TDM slot selection only valid in DSP_A/_B mode */
1208         if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_A)
1209                 delay += (aic3x->tdm_delay*width + 1);
1210         else if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_B)
1211                 delay += aic3x->tdm_delay*width;
1212 
1213         /* Configure data delay */
1214         snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLC, delay);
1215 
1216         return 0;
1217 }
1218 
1219 static int aic3x_mute(struct snd_soc_dai *dai, int mute)
1220 {
1221         struct snd_soc_component *component = dai->component;
1222         u8 ldac_reg = snd_soc_component_read32(component, LDAC_VOL) & ~MUTE_ON;
1223         u8 rdac_reg = snd_soc_component_read32(component, RDAC_VOL) & ~MUTE_ON;
1224 
1225         if (mute) {
1226                 snd_soc_component_write(component, LDAC_VOL, ldac_reg | MUTE_ON);
1227                 snd_soc_component_write(component, RDAC_VOL, rdac_reg | MUTE_ON);
1228         } else {
1229                 snd_soc_component_write(component, LDAC_VOL, ldac_reg);
1230                 snd_soc_component_write(component, RDAC_VOL, rdac_reg);
1231         }
1232 
1233         return 0;
1234 }
1235 
1236 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1237                                 int clk_id, unsigned int freq, int dir)
1238 {
1239         struct snd_soc_component *component = codec_dai->component;
1240         struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1241 
1242         /* set clock on MCLK or GPIO2 or BCLK */
1243         snd_soc_component_update_bits(component, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK,
1244                                 clk_id << PLLCLK_IN_SHIFT);
1245         snd_soc_component_update_bits(component, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK,
1246                                 clk_id << CLKDIV_IN_SHIFT);
1247 
1248         aic3x->sysclk = freq;
1249         return 0;
1250 }
1251 
1252 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
1253                              unsigned int fmt)
1254 {
1255         struct snd_soc_component *component = codec_dai->component;
1256         struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1257         u8 iface_areg, iface_breg;
1258 
1259         iface_areg = snd_soc_component_read32(component, AIC3X_ASD_INTF_CTRLA) & 0x3f;
1260         iface_breg = snd_soc_component_read32(component, AIC3X_ASD_INTF_CTRLB) & 0x3f;
1261 
1262         /* set master/slave audio interface */
1263         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1264         case SND_SOC_DAIFMT_CBM_CFM:
1265                 aic3x->master = 1;
1266                 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1267                 break;
1268         case SND_SOC_DAIFMT_CBS_CFS:
1269                 aic3x->master = 0;
1270                 iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER);
1271                 break;
1272         case SND_SOC_DAIFMT_CBM_CFS:
1273                 aic3x->master = 1;
1274                 iface_areg |= BIT_CLK_MASTER;
1275                 iface_areg &= ~WORD_CLK_MASTER;
1276                 break;
1277         case SND_SOC_DAIFMT_CBS_CFM:
1278                 aic3x->master = 1;
1279                 iface_areg |= WORD_CLK_MASTER;
1280                 iface_areg &= ~BIT_CLK_MASTER;
1281                 break;
1282         default:
1283                 return -EINVAL;
1284         }
1285 
1286         /*
1287          * match both interface format and signal polarities since they
1288          * are fixed
1289          */
1290         switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1291                        SND_SOC_DAIFMT_INV_MASK)) {
1292         case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
1293                 break;
1294         case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1295         case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
1296                 iface_breg |= (0x01 << 6);
1297                 break;
1298         case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
1299                 iface_breg |= (0x02 << 6);
1300                 break;
1301         case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
1302                 iface_breg |= (0x03 << 6);
1303                 break;
1304         default:
1305                 return -EINVAL;
1306         }
1307 
1308         aic3x->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
1309 
1310         /* set iface */
1311         snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLA, iface_areg);
1312         snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLB, iface_breg);
1313 
1314         return 0;
1315 }
1316 
1317 static int aic3x_set_dai_tdm_slot(struct snd_soc_dai *codec_dai,
1318                                   unsigned int tx_mask, unsigned int rx_mask,
1319                                   int slots, int slot_width)
1320 {
1321         struct snd_soc_component *component = codec_dai->component;
1322         struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1323         unsigned int lsb;
1324 
1325         if (tx_mask != rx_mask) {
1326                 dev_err(component->dev, "tx and rx masks must be symmetric\n");
1327                 return -EINVAL;
1328         }
1329 
1330         if (unlikely(!tx_mask)) {
1331                 dev_err(component->dev, "tx and rx masks need to be non 0\n");
1332                 return -EINVAL;
1333         }
1334 
1335         /* TDM based on DSP mode requires slots to be adjacent */
1336         lsb = __ffs(tx_mask);
1337         if ((lsb + 1) != __fls(tx_mask)) {
1338                 dev_err(component->dev, "Invalid mask, slots must be adjacent\n");
1339                 return -EINVAL;
1340         }
1341 
1342         switch (slot_width) {
1343         case 16:
1344         case 20:
1345         case 24:
1346         case 32:
1347                 break;
1348         default:
1349                 dev_err(component->dev, "Unsupported slot width %d\n", slot_width);
1350                 return -EINVAL;
1351         }
1352 
1353 
1354         aic3x->tdm_delay = lsb;
1355         aic3x->slot_width = slot_width;
1356 
1357         /* DOUT in high-impedance on inactive bit clocks */
1358         snd_soc_component_update_bits(component, AIC3X_ASD_INTF_CTRLA,
1359                             DOUT_TRISTATE, DOUT_TRISTATE);
1360 
1361         return 0;
1362 }
1363 
1364 static int aic3x_regulator_event(struct notifier_block *nb,
1365                                  unsigned long event, void *data)
1366 {
1367         struct aic3x_disable_nb *disable_nb =
1368                 container_of(nb, struct aic3x_disable_nb, nb);
1369         struct aic3x_priv *aic3x = disable_nb->aic3x;
1370 
1371         if (event & REGULATOR_EVENT_DISABLE) {
1372                 /*
1373                  * Put codec to reset and require cache sync as at least one
1374                  * of the supplies was disabled
1375                  */
1376                 if (gpio_is_valid(aic3x->gpio_reset))
1377                         gpio_set_value(aic3x->gpio_reset, 0);
1378                 regcache_mark_dirty(aic3x->regmap);
1379         }
1380 
1381         return 0;
1382 }
1383 
1384 static int aic3x_set_power(struct snd_soc_component *component, int power)
1385 {
1386         struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1387         unsigned int pll_c, pll_d;
1388         int ret;
1389 
1390         if (power) {
1391                 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1392                                             aic3x->supplies);
1393                 if (ret)
1394                         goto out;
1395                 aic3x->power = 1;
1396 
1397                 if (gpio_is_valid(aic3x->gpio_reset)) {
1398                         udelay(1);
1399                         gpio_set_value(aic3x->gpio_reset, 1);
1400                 }
1401 
1402                 /* Sync reg_cache with the hardware */
1403                 regcache_cache_only(aic3x->regmap, false);
1404                 regcache_sync(aic3x->regmap);
1405 
1406                 /* Rewrite paired PLL D registers in case cached sync skipped
1407                  * writing one of them and thus caused other one also not
1408                  * being written
1409                  */
1410                 pll_c = snd_soc_component_read32(component, AIC3X_PLL_PROGC_REG);
1411                 pll_d = snd_soc_component_read32(component, AIC3X_PLL_PROGD_REG);
1412                 if (pll_c == aic3x_reg[AIC3X_PLL_PROGC_REG].def ||
1413                         pll_d == aic3x_reg[AIC3X_PLL_PROGD_REG].def) {
1414                         snd_soc_component_write(component, AIC3X_PLL_PROGC_REG, pll_c);
1415                         snd_soc_component_write(component, AIC3X_PLL_PROGD_REG, pll_d);
1416                 }
1417 
1418                 /*
1419                  * Delay is needed to reduce pop-noise after syncing back the
1420                  * registers
1421                  */
1422                 mdelay(50);
1423         } else {
1424                 /*
1425                  * Do soft reset to this codec instance in order to clear
1426                  * possible VDD leakage currents in case the supply regulators
1427                  * remain on
1428                  */
1429                 snd_soc_component_write(component, AIC3X_RESET, SOFT_RESET);
1430                 regcache_mark_dirty(aic3x->regmap);
1431                 aic3x->power = 0;
1432                 /* HW writes are needless when bias is off */
1433                 regcache_cache_only(aic3x->regmap, true);
1434                 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
1435                                              aic3x->supplies);
1436         }
1437 out:
1438         return ret;
1439 }
1440 
1441 static int aic3x_set_bias_level(struct snd_soc_component *component,
1442                                 enum snd_soc_bias_level level)
1443 {
1444         struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1445 
1446         switch (level) {
1447         case SND_SOC_BIAS_ON:
1448                 break;
1449         case SND_SOC_BIAS_PREPARE:
1450                 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY &&
1451                     aic3x->master) {
1452                         /* enable pll */
1453                         snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG,
1454                                             PLL_ENABLE, PLL_ENABLE);
1455                 }
1456                 break;
1457         case SND_SOC_BIAS_STANDBY:
1458                 if (!aic3x->power)
1459                         aic3x_set_power(component, 1);
1460                 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE &&
1461                     aic3x->master) {
1462                         /* disable pll */
1463                         snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG,
1464                                             PLL_ENABLE, 0);
1465                 }
1466                 break;
1467         case SND_SOC_BIAS_OFF:
1468                 if (aic3x->power)
1469                         aic3x_set_power(component, 0);
1470                 break;
1471         }
1472 
1473         return 0;
1474 }
1475 
1476 #define AIC3X_RATES     SNDRV_PCM_RATE_8000_96000
1477 #define AIC3X_FORMATS   (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1478                          SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE | \
1479                          SNDRV_PCM_FMTBIT_S32_LE)
1480 
1481 static const struct snd_soc_dai_ops aic3x_dai_ops = {
1482         .hw_params      = aic3x_hw_params,
1483         .prepare        = aic3x_prepare,
1484         .digital_mute   = aic3x_mute,
1485         .set_sysclk     = aic3x_set_dai_sysclk,
1486         .set_fmt        = aic3x_set_dai_fmt,
1487         .set_tdm_slot   = aic3x_set_dai_tdm_slot,
1488 };
1489 
1490 static struct snd_soc_dai_driver aic3x_dai = {
1491         .name = "tlv320aic3x-hifi",
1492         .playback = {
1493                 .stream_name = "Playback",
1494                 .channels_min = 2,
1495                 .channels_max = 2,
1496                 .rates = AIC3X_RATES,
1497                 .formats = AIC3X_FORMATS,},
1498         .capture = {
1499                 .stream_name = "Capture",
1500                 .channels_min = 2,
1501                 .channels_max = 2,
1502                 .rates = AIC3X_RATES,
1503                 .formats = AIC3X_FORMATS,},
1504         .ops = &aic3x_dai_ops,
1505         .symmetric_rates = 1,
1506 };
1507 
1508 static void aic3x_mono_init(struct snd_soc_component *component)
1509 {
1510         /* DAC to Mono Line Out default volume and route to Output mixer */
1511         snd_soc_component_write(component, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1512         snd_soc_component_write(component, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1513 
1514         /* unmute all outputs */
1515         snd_soc_component_update_bits(component, MONOLOPM_CTRL, UNMUTE, UNMUTE);
1516 
1517         /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1518         snd_soc_component_write(component, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1519         snd_soc_component_write(component, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1520 
1521         /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1522         snd_soc_component_write(component, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1523         snd_soc_component_write(component, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1524 }
1525 
1526 /*
1527  * initialise the AIC3X driver
1528  * register the mixer and dsp interfaces with the kernel
1529  */
1530 static int aic3x_init(struct snd_soc_component *component)
1531 {
1532         struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1533 
1534         snd_soc_component_write(component, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1535         snd_soc_component_write(component, AIC3X_RESET, SOFT_RESET);
1536 
1537         /* DAC default volume and mute */
1538         snd_soc_component_write(component, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1539         snd_soc_component_write(component, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1540 
1541         /* DAC to HP default volume and route to Output mixer */
1542         snd_soc_component_write(component, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1543         snd_soc_component_write(component, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1544         snd_soc_component_write(component, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1545         snd_soc_component_write(component, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1546         /* DAC to Line Out default volume and route to Output mixer */
1547         snd_soc_component_write(component, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1548         snd_soc_component_write(component, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1549 
1550         /* unmute all outputs */
1551         snd_soc_component_update_bits(component, LLOPM_CTRL, UNMUTE, UNMUTE);
1552         snd_soc_component_update_bits(component, RLOPM_CTRL, UNMUTE, UNMUTE);
1553         snd_soc_component_update_bits(component, HPLOUT_CTRL, UNMUTE, UNMUTE);
1554         snd_soc_component_update_bits(component, HPROUT_CTRL, UNMUTE, UNMUTE);
1555         snd_soc_component_update_bits(component, HPLCOM_CTRL, UNMUTE, UNMUTE);
1556         snd_soc_component_update_bits(component, HPRCOM_CTRL, UNMUTE, UNMUTE);
1557 
1558         /* ADC default volume and unmute */
1559         snd_soc_component_write(component, LADC_VOL, DEFAULT_GAIN);
1560         snd_soc_component_write(component, RADC_VOL, DEFAULT_GAIN);
1561         /* By default route Line1 to ADC PGA mixer */
1562         snd_soc_component_write(component, LINE1L_2_LADC_CTRL, 0x0);
1563         snd_soc_component_write(component, LINE1R_2_RADC_CTRL, 0x0);
1564 
1565         /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1566         snd_soc_component_write(component, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1567         snd_soc_component_write(component, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1568         snd_soc_component_write(component, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1569         snd_soc_component_write(component, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1570         /* PGA to Line Out default volume, disconnect from Output Mixer */
1571         snd_soc_component_write(component, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1572         snd_soc_component_write(component, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1573 
1574         /* On tlv320aic3104, these registers are reserved and must not be written */
1575         if (aic3x->model != AIC3X_MODEL_3104) {
1576                 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1577                 snd_soc_component_write(component, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1578                 snd_soc_component_write(component, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1579                 snd_soc_component_write(component, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1580                 snd_soc_component_write(component, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1581                 /* Line2 Line Out default volume, disconnect from Output Mixer */
1582                 snd_soc_component_write(component, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1583                 snd_soc_component_write(component, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1584         }
1585 
1586         switch (aic3x->model) {
1587         case AIC3X_MODEL_3X:
1588         case AIC3X_MODEL_33:
1589                 aic3x_mono_init(component);
1590                 break;
1591         case AIC3X_MODEL_3007:
1592                 snd_soc_component_write(component, CLASSD_CTRL, 0);
1593                 break;
1594         }
1595 
1596         /*  Output common-mode voltage = 1.5 V */
1597         snd_soc_component_update_bits(component, HPOUT_SC, HPOUT_SC_OCMV_MASK,
1598                             aic3x->ocmv << HPOUT_SC_OCMV_SHIFT);
1599 
1600         return 0;
1601 }
1602 
1603 static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x)
1604 {
1605         struct aic3x_priv *a;
1606 
1607         list_for_each_entry(a, &reset_list, list) {
1608                 if (gpio_is_valid(aic3x->gpio_reset) &&
1609                     aic3x->gpio_reset == a->gpio_reset)
1610                         return true;
1611         }
1612 
1613         return false;
1614 }
1615 
1616 static int aic3x_probe(struct snd_soc_component *component)
1617 {
1618         struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1619         int ret, i;
1620 
1621         aic3x->component = component;
1622 
1623         for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
1624                 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
1625                 aic3x->disable_nb[i].aic3x = aic3x;
1626                 ret = devm_regulator_register_notifier(
1627                                                 aic3x->supplies[i].consumer,
1628                                                 &aic3x->disable_nb[i].nb);
1629                 if (ret) {
1630                         dev_err(component->dev,
1631                                 "Failed to request regulator notifier: %d\n",
1632                                  ret);
1633                         return ret;
1634                 }
1635         }
1636 
1637         regcache_mark_dirty(aic3x->regmap);
1638         aic3x_init(component);
1639 
1640         if (aic3x->setup) {
1641                 if (aic3x->model != AIC3X_MODEL_3104) {
1642                         /* setup GPIO functions */
1643                         snd_soc_component_write(component, AIC3X_GPIO1_REG,
1644                                       (aic3x->setup->gpio_func[0] & 0xf) << 4);
1645                         snd_soc_component_write(component, AIC3X_GPIO2_REG,
1646                                       (aic3x->setup->gpio_func[1] & 0xf) << 4);
1647                 } else {
1648                         dev_warn(component->dev, "GPIO functionality is not supported on tlv320aic3104\n");
1649                 }
1650         }
1651 
1652         switch (aic3x->model) {
1653         case AIC3X_MODEL_3X:
1654         case AIC3X_MODEL_33:
1655                 snd_soc_add_component_controls(component, aic3x_extra_snd_controls,
1656                                 ARRAY_SIZE(aic3x_extra_snd_controls));
1657                 snd_soc_add_component_controls(component, aic3x_mono_controls,
1658                                 ARRAY_SIZE(aic3x_mono_controls));
1659                 break;
1660         case AIC3X_MODEL_3007:
1661                 snd_soc_add_component_controls(component, aic3x_extra_snd_controls,
1662                                 ARRAY_SIZE(aic3x_extra_snd_controls));
1663                 snd_soc_add_component_controls(component,
1664                                 &aic3x_classd_amp_gain_ctrl, 1);
1665                 break;
1666         case AIC3X_MODEL_3104:
1667                 break;
1668         }
1669 
1670         /* set mic bias voltage */
1671         switch (aic3x->micbias_vg) {
1672         case AIC3X_MICBIAS_2_0V:
1673         case AIC3X_MICBIAS_2_5V:
1674         case AIC3X_MICBIAS_AVDDV:
1675                 snd_soc_component_update_bits(component, MICBIAS_CTRL,
1676                                     MICBIAS_LEVEL_MASK,
1677                                     (aic3x->micbias_vg) << MICBIAS_LEVEL_SHIFT);
1678                 break;
1679         case AIC3X_MICBIAS_OFF:
1680                 /*
1681                  * noting to do. target won't enter here. This is just to avoid
1682                  * compile time warning "warning: enumeration value
1683                  * 'AIC3X_MICBIAS_OFF' not handled in switch"
1684                  */
1685                 break;
1686         }
1687 
1688         aic3x_add_widgets(component);
1689 
1690         return 0;
1691 }
1692 
1693 static const struct snd_soc_component_driver soc_component_dev_aic3x = {
1694         .set_bias_level         = aic3x_set_bias_level,
1695         .probe                  = aic3x_probe,
1696         .controls               = aic3x_snd_controls,
1697         .num_controls           = ARRAY_SIZE(aic3x_snd_controls),
1698         .dapm_widgets           = aic3x_dapm_widgets,
1699         .num_dapm_widgets       = ARRAY_SIZE(aic3x_dapm_widgets),
1700         .dapm_routes            = intercon,
1701         .num_dapm_routes        = ARRAY_SIZE(intercon),
1702         .use_pmdown_time        = 1,
1703         .endianness             = 1,
1704         .non_legacy_dai_naming  = 1,
1705 };
1706 
1707 static void aic3x_configure_ocmv(struct i2c_client *client)
1708 {
1709         struct device_node *np = client->dev.of_node;
1710         struct aic3x_priv *aic3x = i2c_get_clientdata(client);
1711         u32 value;
1712         int dvdd, avdd;
1713 
1714         if (np && !of_property_read_u32(np, "ai3x-ocmv", &value)) {
1715                 /* OCMV setting is forced by DT */
1716                 if (value <= 3) {
1717                         aic3x->ocmv = value;
1718                         return;
1719                 }
1720         }
1721 
1722         dvdd = regulator_get_voltage(aic3x->supplies[1].consumer);
1723         avdd = regulator_get_voltage(aic3x->supplies[2].consumer);
1724 
1725         if (avdd > 3600000 || dvdd > 1950000) {
1726                 dev_warn(&client->dev,
1727                          "Too high supply voltage(s) AVDD: %d, DVDD: %d\n",
1728                          avdd, dvdd);
1729         } else if (avdd == 3600000 && dvdd == 1950000) {
1730                 aic3x->ocmv = HPOUT_SC_OCMV_1_8V;
1731         } else if (avdd > 3300000 && dvdd > 1800000) {
1732                 aic3x->ocmv = HPOUT_SC_OCMV_1_65V;
1733         } else if (avdd > 3000000 && dvdd > 1650000) {
1734                 aic3x->ocmv = HPOUT_SC_OCMV_1_5V;
1735         } else if (avdd >= 2700000 && dvdd >= 1525000) {
1736                 aic3x->ocmv = HPOUT_SC_OCMV_1_35V;
1737         } else {
1738                 dev_warn(&client->dev,
1739                          "Invalid supply voltage(s) AVDD: %d, DVDD: %d\n",
1740                          avdd, dvdd);
1741         }
1742 }
1743 
1744 /*
1745  * AIC3X 2 wire address can be up to 4 devices with device addresses
1746  * 0x18, 0x19, 0x1A, 0x1B
1747  */
1748 
1749 static const struct i2c_device_id aic3x_i2c_id[] = {
1750         { "tlv320aic3x", AIC3X_MODEL_3X },
1751         { "tlv320aic33", AIC3X_MODEL_33 },
1752         { "tlv320aic3007", AIC3X_MODEL_3007 },
1753         { "tlv320aic3106", AIC3X_MODEL_3X },
1754         { "tlv320aic3104", AIC3X_MODEL_3104 },
1755         { }
1756 };
1757 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1758 
1759 static const struct reg_sequence aic3007_class_d[] = {
1760         /* Class-D speaker driver init; datasheet p. 46 */
1761         { AIC3X_PAGE_SELECT, 0x0D },
1762         { 0xD, 0x0D },
1763         { 0x8, 0x5C },
1764         { 0x8, 0x5D },
1765         { 0x8, 0x5C },
1766         { AIC3X_PAGE_SELECT, 0x00 },
1767 };
1768 
1769 /*
1770  * If the i2c layer weren't so broken, we could pass this kind of data
1771  * around
1772  */
1773 static int aic3x_i2c_probe(struct i2c_client *i2c,
1774                            const struct i2c_device_id *id)
1775 {
1776         struct aic3x_pdata *pdata = i2c->dev.platform_data;
1777         struct aic3x_priv *aic3x;
1778         struct aic3x_setup_data *ai3x_setup;
1779         struct device_node *np = i2c->dev.of_node;
1780         int ret, i;
1781         u32 value;
1782 
1783         aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL);
1784         if (!aic3x)
1785                 return -ENOMEM;
1786 
1787         aic3x->regmap = devm_regmap_init_i2c(i2c, &aic3x_regmap);
1788         if (IS_ERR(aic3x->regmap)) {
1789                 ret = PTR_ERR(aic3x->regmap);
1790                 return ret;
1791         }
1792 
1793         regcache_cache_only(aic3x->regmap, true);
1794 
1795         i2c_set_clientdata(i2c, aic3x);
1796         if (pdata) {
1797                 aic3x->gpio_reset = pdata->gpio_reset;
1798                 aic3x->setup = pdata->setup;
1799                 aic3x->micbias_vg = pdata->micbias_vg;
1800         } else if (np) {
1801                 ai3x_setup = devm_kzalloc(&i2c->dev, sizeof(*ai3x_setup),
1802                                                                 GFP_KERNEL);
1803                 if (!ai3x_setup)
1804                         return -ENOMEM;
1805 
1806                 ret = of_get_named_gpio(np, "reset-gpios", 0);
1807                 if (ret >= 0) {
1808                         aic3x->gpio_reset = ret;
1809                 } else {
1810                         ret = of_get_named_gpio(np, "gpio-reset", 0);
1811                         if (ret > 0) {
1812                                 dev_warn(&i2c->dev, "Using deprecated property \"gpio-reset\", please update your DT");
1813                                 aic3x->gpio_reset = ret;
1814                         } else {
1815                                 aic3x->gpio_reset = -1;
1816                         }
1817                 }
1818 
1819                 if (of_property_read_u32_array(np, "ai3x-gpio-func",
1820                                         ai3x_setup->gpio_func, 2) >= 0) {
1821                         aic3x->setup = ai3x_setup;
1822                 }
1823 
1824                 if (!of_property_read_u32(np, "ai3x-micbias-vg", &value)) {
1825                         switch (value) {
1826                         case 1 :
1827                                 aic3x->micbias_vg = AIC3X_MICBIAS_2_0V;
1828                                 break;
1829                         case 2 :
1830                                 aic3x->micbias_vg = AIC3X_MICBIAS_2_5V;
1831                                 break;
1832                         case 3 :
1833                                 aic3x->micbias_vg = AIC3X_MICBIAS_AVDDV;
1834                                 break;
1835                         default :
1836                                 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1837                                 dev_err(&i2c->dev, "Unsuitable MicBias voltage "
1838                                                         "found in DT\n");
1839                         }
1840                 } else {
1841                         aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1842                 }
1843 
1844         } else {
1845                 aic3x->gpio_reset = -1;
1846         }
1847 
1848         aic3x->model = id->driver_data;
1849 
1850         if (gpio_is_valid(aic3x->gpio_reset) &&
1851             !aic3x_is_shared_reset(aic3x)) {
1852                 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
1853                 if (ret != 0)
1854                         goto err;
1855                 gpio_direction_output(aic3x->gpio_reset, 0);
1856         }
1857 
1858         for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1859                 aic3x->supplies[i].supply = aic3x_supply_names[i];
1860 
1861         ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(aic3x->supplies),
1862                                       aic3x->supplies);
1863         if (ret != 0) {
1864                 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
1865                 goto err_gpio;
1866         }
1867 
1868         aic3x_configure_ocmv(i2c);
1869 
1870         if (aic3x->model == AIC3X_MODEL_3007) {
1871                 ret = regmap_register_patch(aic3x->regmap, aic3007_class_d,
1872                                             ARRAY_SIZE(aic3007_class_d));
1873                 if (ret != 0)
1874                         dev_err(&i2c->dev, "Failed to init class D: %d\n",
1875                                 ret);
1876         }
1877 
1878         ret = devm_snd_soc_register_component(&i2c->dev,
1879                         &soc_component_dev_aic3x, &aic3x_dai, 1);
1880 
1881         if (ret != 0)
1882                 goto err_gpio;
1883 
1884         INIT_LIST_HEAD(&aic3x->list);
1885         list_add(&aic3x->list, &reset_list);
1886 
1887         return 0;
1888 
1889 err_gpio:
1890         if (gpio_is_valid(aic3x->gpio_reset) &&
1891             !aic3x_is_shared_reset(aic3x))
1892                 gpio_free(aic3x->gpio_reset);
1893 err:
1894         return ret;
1895 }
1896 
1897 static int aic3x_i2c_remove(struct i2c_client *client)
1898 {
1899         struct aic3x_priv *aic3x = i2c_get_clientdata(client);
1900 
1901         list_del(&aic3x->list);
1902 
1903         if (gpio_is_valid(aic3x->gpio_reset) &&
1904             !aic3x_is_shared_reset(aic3x)) {
1905                 gpio_set_value(aic3x->gpio_reset, 0);
1906                 gpio_free(aic3x->gpio_reset);
1907         }
1908         return 0;
1909 }
1910 
1911 #if defined(CONFIG_OF)
1912 static const struct of_device_id tlv320aic3x_of_match[] = {
1913         { .compatible = "ti,tlv320aic3x", },
1914         { .compatible = "ti,tlv320aic33" },
1915         { .compatible = "ti,tlv320aic3007" },
1916         { .compatible = "ti,tlv320aic3106" },
1917         { .compatible = "ti,tlv320aic3104" },
1918         {},
1919 };
1920 MODULE_DEVICE_TABLE(of, tlv320aic3x_of_match);
1921 #endif
1922 
1923 /* machine i2c codec control layer */
1924 static struct i2c_driver aic3x_i2c_driver = {
1925         .driver = {
1926                 .name = "tlv320aic3x-codec",
1927                 .of_match_table = of_match_ptr(tlv320aic3x_of_match),
1928         },
1929         .probe  = aic3x_i2c_probe,
1930         .remove = aic3x_i2c_remove,
1931         .id_table = aic3x_i2c_id,
1932 };
1933 
1934 module_i2c_driver(aic3x_i2c_driver);
1935 
1936 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1937 MODULE_AUTHOR("Vladimir Barinov");
1938 MODULE_LICENSE("GPL");
/* [<][>][^][v][top][bottom][index][help] */
root/sound/soc/codecs/tlv320aic3x.c

DEFINITIONS
