1
2
3
4
5
6
7
8 #ifndef _TLV320AIC31XX_H
9 #define _TLV320AIC31XX_H
10
11 #define AIC31XX_RATES SNDRV_PCM_RATE_8000_192000
12
13 #define AIC31XX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
14 SNDRV_PCM_FMTBIT_S20_3LE | \
15 SNDRV_PCM_FMTBIT_S24_3LE | \
16 SNDRV_PCM_FMTBIT_S24_LE | \
17 SNDRV_PCM_FMTBIT_S32_LE)
18
19 #define AIC31XX_STEREO_CLASS_D_BIT BIT(1)
20 #define AIC31XX_MINIDSP_BIT BIT(2)
21 #define DAC31XX_BIT BIT(3)
22
23 #define AIC31XX_JACK_MASK (SND_JACK_HEADPHONE | \
24 SND_JACK_HEADSET | \
25 SND_JACK_BTN_0)
26
27 enum aic31xx_type {
28 AIC3100 = 0,
29 AIC3110 = AIC31XX_STEREO_CLASS_D_BIT,
30 AIC3120 = AIC31XX_MINIDSP_BIT,
31 AIC3111 = AIC31XX_STEREO_CLASS_D_BIT | AIC31XX_MINIDSP_BIT,
32 DAC3100 = DAC31XX_BIT,
33 DAC3101 = DAC31XX_BIT | AIC31XX_STEREO_CLASS_D_BIT,
34 };
35
36 struct aic31xx_pdata {
37 enum aic31xx_type codec_type;
38 unsigned int gpio_reset;
39 int micbias_vg;
40 };
41
42 #define AIC31XX_REG(page, reg) ((page * 128) + reg)
43
44 #define AIC31XX_PAGECTL AIC31XX_REG(0, 0)
45
46
47 #define AIC31XX_RESET AIC31XX_REG(0, 1)
48 #define AIC31XX_OT_FLAG AIC31XX_REG(0, 3)
49 #define AIC31XX_CLKMUX AIC31XX_REG(0, 4)
50 #define AIC31XX_PLLPR AIC31XX_REG(0, 5)
51 #define AIC31XX_PLLJ AIC31XX_REG(0, 6)
52 #define AIC31XX_PLLDMSB AIC31XX_REG(0, 7)
53 #define AIC31XX_PLLDLSB AIC31XX_REG(0, 8)
54 #define AIC31XX_NDAC AIC31XX_REG(0, 11)
55 #define AIC31XX_MDAC AIC31XX_REG(0, 12)
56 #define AIC31XX_DOSRMSB AIC31XX_REG(0, 13)
57 #define AIC31XX_DOSRLSB AIC31XX_REG(0, 14)
58 #define AIC31XX_MINI_DSP_INPOL AIC31XX_REG(0, 16)
59 #define AIC31XX_NADC AIC31XX_REG(0, 18)
60 #define AIC31XX_MADC AIC31XX_REG(0, 19)
61 #define AIC31XX_AOSR AIC31XX_REG(0, 20)
62 #define AIC31XX_CLKOUTMUX AIC31XX_REG(0, 25)
63 #define AIC31XX_CLKOUTMVAL AIC31XX_REG(0, 26)
64 #define AIC31XX_IFACE1 AIC31XX_REG(0, 27)
65 #define AIC31XX_DATA_OFFSET AIC31XX_REG(0, 28)
66 #define AIC31XX_IFACE2 AIC31XX_REG(0, 29)
67 #define AIC31XX_BCLKN AIC31XX_REG(0, 30)
68 #define AIC31XX_IFACESEC1 AIC31XX_REG(0, 31)
69 #define AIC31XX_IFACESEC2 AIC31XX_REG(0, 32)
70 #define AIC31XX_IFACESEC3 AIC31XX_REG(0, 33)
71 #define AIC31XX_I2C AIC31XX_REG(0, 34)
72 #define AIC31XX_ADCFLAG AIC31XX_REG(0, 36)
73 #define AIC31XX_DACFLAG1 AIC31XX_REG(0, 37)
74 #define AIC31XX_DACFLAG2 AIC31XX_REG(0, 38)
75 #define AIC31XX_OFFLAG AIC31XX_REG(0, 39)
76 #define AIC31XX_INTRDACFLAG AIC31XX_REG(0, 44)
77 #define AIC31XX_INTRADCFLAG AIC31XX_REG(0, 45)
78 #define AIC31XX_INTRDACFLAG2 AIC31XX_REG(0, 46)
79 #define AIC31XX_INTRADCFLAG2 AIC31XX_REG(0, 47)
80 #define AIC31XX_INT1CTRL AIC31XX_REG(0, 48)
81 #define AIC31XX_INT2CTRL AIC31XX_REG(0, 49)
82 #define AIC31XX_GPIO1 AIC31XX_REG(0, 51)
83 #define AIC31XX_DACPRB AIC31XX_REG(0, 60)
84 #define AIC31XX_ADCPRB AIC31XX_REG(0, 61)
85 #define AIC31XX_DACSETUP AIC31XX_REG(0, 63)
86 #define AIC31XX_DACMUTE AIC31XX_REG(0, 64)
87 #define AIC31XX_LDACVOL AIC31XX_REG(0, 65)
88 #define AIC31XX_RDACVOL AIC31XX_REG(0, 66)
89 #define AIC31XX_HSDETECT AIC31XX_REG(0, 67)
90 #define AIC31XX_ADCSETUP AIC31XX_REG(0, 81)
91 #define AIC31XX_ADCFGA AIC31XX_REG(0, 82)
92 #define AIC31XX_ADCVOL AIC31XX_REG(0, 83)
93
94
95 #define AIC31XX_HPDRIVER AIC31XX_REG(1, 31)
96 #define AIC31XX_SPKAMP AIC31XX_REG(1, 32)
97 #define AIC31XX_HPPOP AIC31XX_REG(1, 33)
98 #define AIC31XX_SPPGARAMP AIC31XX_REG(1, 34)
99 #define AIC31XX_DACMIXERROUTE AIC31XX_REG(1, 35)
100 #define AIC31XX_LANALOGHPL AIC31XX_REG(1, 36)
101 #define AIC31XX_RANALOGHPR AIC31XX_REG(1, 37)
102 #define AIC31XX_LANALOGSPL AIC31XX_REG(1, 38)
103 #define AIC31XX_RANALOGSPR AIC31XX_REG(1, 39)
104 #define AIC31XX_HPLGAIN AIC31XX_REG(1, 40)
105 #define AIC31XX_HPRGAIN AIC31XX_REG(1, 41)
106 #define AIC31XX_SPLGAIN AIC31XX_REG(1, 42)
107 #define AIC31XX_SPRGAIN AIC31XX_REG(1, 43)
108 #define AIC31XX_HPCONTROL AIC31XX_REG(1, 44)
109 #define AIC31XX_MICBIAS AIC31XX_REG(1, 46)
110 #define AIC31XX_MICPGA AIC31XX_REG(1, 47)
111 #define AIC31XX_MICPGAPI AIC31XX_REG(1, 48)
112 #define AIC31XX_MICPGAMI AIC31XX_REG(1, 49)
113 #define AIC31XX_MICPGACM AIC31XX_REG(1, 50)
114
115
116
117
118 #define AIC31XX_PLL_CLKIN_MASK GENMASK(3, 2)
119 #define AIC31XX_PLL_CLKIN_SHIFT (2)
120 #define AIC31XX_PLL_CLKIN_MCLK 0x00
121 #define AIC31XX_PLL_CLKIN_BCKL 0x01
122 #define AIC31XX_PLL_CLKIN_GPIO1 0x02
123 #define AIC31XX_PLL_CLKIN_DIN 0x03
124 #define AIC31XX_CODEC_CLKIN_MASK GENMASK(1, 0)
125 #define AIC31XX_CODEC_CLKIN_SHIFT (0)
126 #define AIC31XX_CODEC_CLKIN_MCLK 0x00
127 #define AIC31XX_CODEC_CLKIN_BCLK 0x01
128 #define AIC31XX_CODEC_CLKIN_GPIO1 0x02
129 #define AIC31XX_CODEC_CLKIN_PLL 0x03
130
131
132
133
134
135
136
137 #define AIC31XX_PLL_MASK GENMASK(6, 0)
138 #define AIC31XX_PM_MASK BIT(7)
139
140
141 #define AIC31XX_IFACE1_DATATYPE_MASK GENMASK(7, 6)
142 #define AIC31XX_IFACE1_DATATYPE_SHIFT (6)
143 #define AIC31XX_I2S_MODE 0x00
144 #define AIC31XX_DSP_MODE 0x01
145 #define AIC31XX_RIGHT_JUSTIFIED_MODE 0x02
146 #define AIC31XX_LEFT_JUSTIFIED_MODE 0x03
147 #define AIC31XX_IFACE1_DATALEN_MASK GENMASK(5, 4)
148 #define AIC31XX_IFACE1_DATALEN_SHIFT (4)
149 #define AIC31XX_WORD_LEN_16BITS 0x00
150 #define AIC31XX_WORD_LEN_20BITS 0x01
151 #define AIC31XX_WORD_LEN_24BITS 0x02
152 #define AIC31XX_WORD_LEN_32BITS 0x03
153 #define AIC31XX_IFACE1_MASTER_MASK GENMASK(3, 2)
154 #define AIC31XX_BCLK_MASTER BIT(2)
155 #define AIC31XX_WCLK_MASTER BIT(3)
156
157
158 #define AIC31XX_DATA_OFFSET_MASK GENMASK(7, 0)
159
160
161 #define AIC31XX_BCLKINV_MASK BIT(3)
162 #define AIC31XX_BDIVCLK_MASK GENMASK(1, 0)
163 #define AIC31XX_DAC2BCLK 0x00
164 #define AIC31XX_DACMOD2BCLK 0x01
165 #define AIC31XX_ADC2BCLK 0x02
166 #define AIC31XX_ADCMOD2BCLK 0x03
167 #define AIC31XX_KEEP_I2SCLK BIT(2)
168
169
170 #define AIC31XX_ADCPWRSTATUS_MASK BIT(6)
171
172
173 #define AIC31XX_LDACPWRSTATUS_MASK BIT(7)
174 #define AIC31XX_HPLDRVPWRSTATUS_MASK BIT(5)
175 #define AIC31XX_SPLDRVPWRSTATUS_MASK BIT(4)
176 #define AIC31XX_RDACPWRSTATUS_MASK BIT(3)
177 #define AIC31XX_HPRDRVPWRSTATUS_MASK BIT(1)
178 #define AIC31XX_SPRDRVPWRSTATUS_MASK BIT(0)
179
180
181 #define AIC31XX_DAC_OF_LEFT BIT(7)
182 #define AIC31XX_DAC_OF_RIGHT BIT(6)
183 #define AIC31XX_DAC_OF_SHIFTER BIT(5)
184 #define AIC31XX_ADC_OF BIT(3)
185 #define AIC31XX_ADC_OF_SHIFTER BIT(1)
186
187
188 #define AIC31XX_HPLSCDETECT BIT(7)
189 #define AIC31XX_HPRSCDETECT BIT(6)
190 #define AIC31XX_BUTTONPRESS BIT(5)
191 #define AIC31XX_HSPLUG BIT(4)
192 #define AIC31XX_LDRCTHRES BIT(3)
193 #define AIC31XX_RDRCTHRES BIT(2)
194 #define AIC31XX_DACSINT BIT(1)
195 #define AIC31XX_DACAINT BIT(0)
196
197
198 #define AIC31XX_HSPLUGDET BIT(7)
199 #define AIC31XX_BUTTONPRESSDET BIT(6)
200 #define AIC31XX_DRCTHRES BIT(5)
201 #define AIC31XX_AGCNOISE BIT(4)
202 #define AIC31XX_SC BIT(3)
203 #define AIC31XX_ENGINE BIT(2)
204
205
206 #define AIC31XX_GPIO1_FUNC_MASK GENMASK(5, 2)
207 #define AIC31XX_GPIO1_FUNC_SHIFT 2
208 #define AIC31XX_GPIO1_DISABLED 0x00
209 #define AIC31XX_GPIO1_INPUT 0x01
210 #define AIC31XX_GPIO1_GPI 0x02
211 #define AIC31XX_GPIO1_GPO 0x03
212 #define AIC31XX_GPIO1_CLKOUT 0x04
213 #define AIC31XX_GPIO1_INT1 0x05
214 #define AIC31XX_GPIO1_INT2 0x06
215 #define AIC31XX_GPIO1_ADC_WCLK 0x07
216 #define AIC31XX_GPIO1_SBCLK 0x08
217 #define AIC31XX_GPIO1_SWCLK 0x09
218 #define AIC31XX_GPIO1_ADC_MOD_CLK 0x10
219 #define AIC31XX_GPIO1_SDOUT 0x11
220
221
222 #define AIC31XX_SOFTSTEP_MASK GENMASK(1, 0)
223
224
225 #define AIC31XX_DACMUTE_MASK GENMASK(3, 2)
226
227
228 #define AIC31XX_HSD_ENABLE BIT(7)
229 #define AIC31XX_HSD_TYPE_MASK GENMASK(6, 5)
230 #define AIC31XX_HSD_TYPE_SHIFT 5
231 #define AIC31XX_HSD_NONE 0x00
232 #define AIC31XX_HSD_HP 0x01
233 #define AIC31XX_HSD_HS 0x03
234
235
236 #define AIC31XX_MICBIAS_MASK GENMASK(1, 0)
237 #define AIC31XX_MICBIAS_SHIFT 0
238
239 #endif