This source file includes following definitions.
- rt5677_volatile_register
- rt5677_readable_register
- rt5677_dsp_mode_i2c_write_addr
- rt5677_dsp_mode_i2c_read_addr
- rt5677_dsp_mode_i2c_write
- rt5677_dsp_mode_i2c_read
- rt5677_set_dsp_mode
- rt5677_set_dsp_vad
- rt5677_dsp_vad_get
- rt5677_dsp_vad_put
- set_dmic_clk
- is_sys_clk_from_pll
- is_using_asrc
- can_use_asrc
- rt5677_sel_asrc_clk_src
- rt5677_dmic_use_asrc
- rt5677_bst1_event
- rt5677_bst2_event
- rt5677_set_pll1_event
- rt5677_set_pll2_event
- rt5677_set_micbias1_event
- rt5677_if1_adc_tdm_event
- rt5677_if2_adc_tdm_event
- rt5677_vref_event
- rt5677_filter_power_event
- rt5677_hw_params
- rt5677_set_dai_fmt
- rt5677_set_dai_sysclk
- rt5677_pll_calc
- rt5677_set_dai_pll
- rt5677_set_tdm_slot
- rt5677_set_bias_level
- rt5677_gpio_set
- rt5677_gpio_direction_out
- rt5677_gpio_get
- rt5677_gpio_direction_in
- rt5677_gpio_config
- rt5677_to_irq
- rt5677_init_gpio
- rt5677_free_gpio
- rt5677_gpio_config
- rt5677_init_gpio
- rt5677_free_gpio
- rt5677_probe
- rt5677_remove
- rt5677_suspend
- rt5677_resume
- rt5677_read
- rt5677_write
- rt5677_read_device_properties
- rt5677_irq
- rt5677_irq_bus_lock
- rt5677_irq_bus_sync_unlock
- rt5677_irq_enable
- rt5677_irq_disable
- rt5677_irq_map
- rt5677_init_irq
- rt5677_i2c_probe
- rt5677_i2c_remove
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9 #include <linux/acpi.h>
10 #include <linux/fs.h>
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
15 #include <linux/pm.h>
16 #include <linux/regmap.h>
17 #include <linux/i2c.h>
18 #include <linux/platform_device.h>
19 #include <linux/spi/spi.h>
20 #include <linux/firmware.h>
21 #include <linux/of_device.h>
22 #include <linux/property.h>
23 #include <linux/irq.h>
24 #include <linux/interrupt.h>
25 #include <linux/irqdomain.h>
26 #include <linux/workqueue.h>
27 #include <sound/core.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/soc.h>
31 #include <sound/soc-dapm.h>
32 #include <sound/initval.h>
33 #include <sound/tlv.h>
34
35 #include "rl6231.h"
36 #include "rt5677.h"
37 #include "rt5677-spi.h"
38
39 #define RT5677_DEVICE_ID 0x6327
40
41 #define RT5677_PR_RANGE_BASE (0xff + 1)
42 #define RT5677_PR_SPACING 0x100
43
44 #define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
45
46 static const struct regmap_range_cfg rt5677_ranges[] = {
47 {
48 .name = "PR",
49 .range_min = RT5677_PR_BASE,
50 .range_max = RT5677_PR_BASE + 0xfd,
51 .selector_reg = RT5677_PRIV_INDEX,
52 .selector_mask = 0xff,
53 .selector_shift = 0x0,
54 .window_start = RT5677_PRIV_DATA,
55 .window_len = 0x1,
56 },
57 };
58
59 static const struct reg_sequence init_list[] = {
60 {RT5677_ASRC_12, 0x0018},
61 {RT5677_PR_BASE + 0x3d, 0x364d},
62 {RT5677_PR_BASE + 0x17, 0x4fc0},
63 {RT5677_PR_BASE + 0x13, 0x0312},
64 {RT5677_PR_BASE + 0x1e, 0x0000},
65 {RT5677_PR_BASE + 0x12, 0x0eaa},
66 {RT5677_PR_BASE + 0x14, 0x018a},
67 {RT5677_PR_BASE + 0x15, 0x0490},
68 {RT5677_PR_BASE + 0x38, 0x0f71},
69 {RT5677_PR_BASE + 0x39, 0x0f71},
70 };
71 #define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
72
73 static const struct reg_default rt5677_reg[] = {
74 {RT5677_RESET , 0x0000},
75 {RT5677_LOUT1 , 0xa800},
76 {RT5677_IN1 , 0x0000},
77 {RT5677_MICBIAS , 0x0000},
78 {RT5677_SLIMBUS_PARAM , 0x0000},
79 {RT5677_SLIMBUS_RX , 0x0000},
80 {RT5677_SLIMBUS_CTRL , 0x0000},
81 {RT5677_SIDETONE_CTRL , 0x000b},
82 {RT5677_ANA_DAC1_2_3_SRC , 0x0000},
83 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
84 {RT5677_DAC4_DIG_VOL , 0xafaf},
85 {RT5677_DAC3_DIG_VOL , 0xafaf},
86 {RT5677_DAC1_DIG_VOL , 0xafaf},
87 {RT5677_DAC2_DIG_VOL , 0xafaf},
88 {RT5677_IF_DSP_DAC2_MIXER , 0x0011},
89 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
90 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
91 {RT5677_STO1_2_ADC_BST , 0x0000},
92 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
93 {RT5677_ADC_BST_CTRL2 , 0x0000},
94 {RT5677_STO3_4_ADC_BST , 0x0000},
95 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
96 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
97 {RT5677_STO4_ADC_MIXER , 0xd4c0},
98 {RT5677_STO3_ADC_MIXER , 0xd4c0},
99 {RT5677_STO2_ADC_MIXER , 0xd4c0},
100 {RT5677_STO1_ADC_MIXER , 0xd4c0},
101 {RT5677_MONO_ADC_MIXER , 0xd4d1},
102 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
103 {RT5677_STO1_DAC_MIXER , 0xaaaa},
104 {RT5677_MONO_DAC_MIXER , 0xaaaa},
105 {RT5677_DD1_MIXER , 0xaaaa},
106 {RT5677_DD2_MIXER , 0xaaaa},
107 {RT5677_IF3_DATA , 0x0000},
108 {RT5677_IF4_DATA , 0x0000},
109 {RT5677_PDM_OUT_CTRL , 0x8888},
110 {RT5677_PDM_DATA_CTRL1 , 0x0000},
111 {RT5677_PDM_DATA_CTRL2 , 0x0000},
112 {RT5677_PDM1_DATA_CTRL2 , 0x0000},
113 {RT5677_PDM1_DATA_CTRL3 , 0x0000},
114 {RT5677_PDM1_DATA_CTRL4 , 0x0000},
115 {RT5677_PDM2_DATA_CTRL2 , 0x0000},
116 {RT5677_PDM2_DATA_CTRL3 , 0x0000},
117 {RT5677_PDM2_DATA_CTRL4 , 0x0000},
118 {RT5677_TDM1_CTRL1 , 0x0300},
119 {RT5677_TDM1_CTRL2 , 0x0000},
120 {RT5677_TDM1_CTRL3 , 0x4000},
121 {RT5677_TDM1_CTRL4 , 0x0123},
122 {RT5677_TDM1_CTRL5 , 0x4567},
123 {RT5677_TDM2_CTRL1 , 0x0300},
124 {RT5677_TDM2_CTRL2 , 0x0000},
125 {RT5677_TDM2_CTRL3 , 0x4000},
126 {RT5677_TDM2_CTRL4 , 0x0123},
127 {RT5677_TDM2_CTRL5 , 0x4567},
128 {RT5677_I2C_MASTER_CTRL1 , 0x0001},
129 {RT5677_I2C_MASTER_CTRL2 , 0x0000},
130 {RT5677_I2C_MASTER_CTRL3 , 0x0000},
131 {RT5677_I2C_MASTER_CTRL4 , 0x0000},
132 {RT5677_I2C_MASTER_CTRL5 , 0x0000},
133 {RT5677_I2C_MASTER_CTRL6 , 0x0000},
134 {RT5677_I2C_MASTER_CTRL7 , 0x0000},
135 {RT5677_I2C_MASTER_CTRL8 , 0x0000},
136 {RT5677_DMIC_CTRL1 , 0x1505},
137 {RT5677_DMIC_CTRL2 , 0x0055},
138 {RT5677_HAP_GENE_CTRL1 , 0x0111},
139 {RT5677_HAP_GENE_CTRL2 , 0x0064},
140 {RT5677_HAP_GENE_CTRL3 , 0xef0e},
141 {RT5677_HAP_GENE_CTRL4 , 0xf0f0},
142 {RT5677_HAP_GENE_CTRL5 , 0xef0e},
143 {RT5677_HAP_GENE_CTRL6 , 0xf0f0},
144 {RT5677_HAP_GENE_CTRL7 , 0xef0e},
145 {RT5677_HAP_GENE_CTRL8 , 0xf0f0},
146 {RT5677_HAP_GENE_CTRL9 , 0xf000},
147 {RT5677_HAP_GENE_CTRL10 , 0x0000},
148 {RT5677_PWR_DIG1 , 0x0000},
149 {RT5677_PWR_DIG2 , 0x0000},
150 {RT5677_PWR_ANLG1 , 0x0055},
151 {RT5677_PWR_ANLG2 , 0x0000},
152 {RT5677_PWR_DSP1 , 0x0001},
153 {RT5677_PWR_DSP_ST , 0x0000},
154 {RT5677_PWR_DSP2 , 0x0000},
155 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
156 {RT5677_PRIV_INDEX , 0x0000},
157 {RT5677_PRIV_DATA , 0x0000},
158 {RT5677_I2S4_SDP , 0x8000},
159 {RT5677_I2S1_SDP , 0x8000},
160 {RT5677_I2S2_SDP , 0x8000},
161 {RT5677_I2S3_SDP , 0x8000},
162 {RT5677_CLK_TREE_CTRL1 , 0x1111},
163 {RT5677_CLK_TREE_CTRL2 , 0x1111},
164 {RT5677_CLK_TREE_CTRL3 , 0x0000},
165 {RT5677_PLL1_CTRL1 , 0x0000},
166 {RT5677_PLL1_CTRL2 , 0x0000},
167 {RT5677_PLL2_CTRL1 , 0x0c60},
168 {RT5677_PLL2_CTRL2 , 0x2000},
169 {RT5677_GLB_CLK1 , 0x0000},
170 {RT5677_GLB_CLK2 , 0x0000},
171 {RT5677_ASRC_1 , 0x0000},
172 {RT5677_ASRC_2 , 0x0000},
173 {RT5677_ASRC_3 , 0x0000},
174 {RT5677_ASRC_4 , 0x0000},
175 {RT5677_ASRC_5 , 0x0000},
176 {RT5677_ASRC_6 , 0x0000},
177 {RT5677_ASRC_7 , 0x0000},
178 {RT5677_ASRC_8 , 0x0000},
179 {RT5677_ASRC_9 , 0x0000},
180 {RT5677_ASRC_10 , 0x0000},
181 {RT5677_ASRC_11 , 0x0000},
182 {RT5677_ASRC_12 , 0x0018},
183 {RT5677_ASRC_13 , 0x0000},
184 {RT5677_ASRC_14 , 0x0000},
185 {RT5677_ASRC_15 , 0x0000},
186 {RT5677_ASRC_16 , 0x0000},
187 {RT5677_ASRC_17 , 0x0000},
188 {RT5677_ASRC_18 , 0x0000},
189 {RT5677_ASRC_19 , 0x0000},
190 {RT5677_ASRC_20 , 0x0000},
191 {RT5677_ASRC_21 , 0x000c},
192 {RT5677_ASRC_22 , 0x0000},
193 {RT5677_ASRC_23 , 0x0000},
194 {RT5677_VAD_CTRL1 , 0x2184},
195 {RT5677_VAD_CTRL2 , 0x010a},
196 {RT5677_VAD_CTRL3 , 0x0aea},
197 {RT5677_VAD_CTRL4 , 0x000c},
198 {RT5677_VAD_CTRL5 , 0x0000},
199 {RT5677_DSP_INB_CTRL1 , 0x0000},
200 {RT5677_DSP_INB_CTRL2 , 0x0000},
201 {RT5677_DSP_IN_OUTB_CTRL , 0x0000},
202 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
203 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
204 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
205 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
206 {RT5677_ADC_EQ_CTRL1 , 0x6000},
207 {RT5677_ADC_EQ_CTRL2 , 0x0000},
208 {RT5677_EQ_CTRL1 , 0xc000},
209 {RT5677_EQ_CTRL2 , 0x0000},
210 {RT5677_EQ_CTRL3 , 0x0000},
211 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
212 {RT5677_JD_CTRL1 , 0x0000},
213 {RT5677_JD_CTRL2 , 0x0000},
214 {RT5677_JD_CTRL3 , 0x0000},
215 {RT5677_IRQ_CTRL1 , 0x0000},
216 {RT5677_IRQ_CTRL2 , 0x0000},
217 {RT5677_GPIO_ST , 0x0000},
218 {RT5677_GPIO_CTRL1 , 0x0000},
219 {RT5677_GPIO_CTRL2 , 0x0000},
220 {RT5677_GPIO_CTRL3 , 0x0000},
221 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
222 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
223 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
224 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
225 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
226 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
227 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
228 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
229 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
230 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
231 {RT5677_MB_DRC_CTRL1 , 0x0f20},
232 {RT5677_DRC1_CTRL1 , 0x001f},
233 {RT5677_DRC1_CTRL2 , 0x020c},
234 {RT5677_DRC1_CTRL3 , 0x1f00},
235 {RT5677_DRC1_CTRL4 , 0x0000},
236 {RT5677_DRC1_CTRL5 , 0x0000},
237 {RT5677_DRC1_CTRL6 , 0x0029},
238 {RT5677_DRC2_CTRL1 , 0x001f},
239 {RT5677_DRC2_CTRL2 , 0x020c},
240 {RT5677_DRC2_CTRL3 , 0x1f00},
241 {RT5677_DRC2_CTRL4 , 0x0000},
242 {RT5677_DRC2_CTRL5 , 0x0000},
243 {RT5677_DRC2_CTRL6 , 0x0029},
244 {RT5677_DRC1_HL_CTRL1 , 0x8000},
245 {RT5677_DRC1_HL_CTRL2 , 0x0200},
246 {RT5677_DRC2_HL_CTRL1 , 0x8000},
247 {RT5677_DRC2_HL_CTRL2 , 0x0200},
248 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
249 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
250 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
251 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
252 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
253 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
254 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
255 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
256 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
257 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
258 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
259 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
260 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
261 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
262 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
263 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
264 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
265 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
266 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
267 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
268 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
269 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
270 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
271 {RT5677_DIG_MISC , 0x0000},
272 {RT5677_GEN_CTRL1 , 0x0000},
273 {RT5677_GEN_CTRL2 , 0x0000},
274 {RT5677_VENDOR_ID , 0x0000},
275 {RT5677_VENDOR_ID1 , 0x10ec},
276 {RT5677_VENDOR_ID2 , 0x6327},
277 };
278
279 static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
280 {
281 int i;
282
283 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
284 if (reg >= rt5677_ranges[i].range_min &&
285 reg <= rt5677_ranges[i].range_max) {
286 return true;
287 }
288 }
289
290 switch (reg) {
291 case RT5677_RESET:
292 case RT5677_SLIMBUS_PARAM:
293 case RT5677_PDM_DATA_CTRL1:
294 case RT5677_PDM_DATA_CTRL2:
295 case RT5677_PDM1_DATA_CTRL4:
296 case RT5677_PDM2_DATA_CTRL4:
297 case RT5677_I2C_MASTER_CTRL1:
298 case RT5677_I2C_MASTER_CTRL7:
299 case RT5677_I2C_MASTER_CTRL8:
300 case RT5677_HAP_GENE_CTRL2:
301 case RT5677_PWR_ANLG2:
302 case RT5677_PWR_DSP_ST:
303 case RT5677_PRIV_DATA:
304 case RT5677_ASRC_22:
305 case RT5677_ASRC_23:
306 case RT5677_VAD_CTRL5:
307 case RT5677_ADC_EQ_CTRL1:
308 case RT5677_EQ_CTRL1:
309 case RT5677_IRQ_CTRL1:
310 case RT5677_IRQ_CTRL2:
311 case RT5677_GPIO_ST:
312 case RT5677_DSP_INB1_SRC_CTRL4:
313 case RT5677_DSP_INB2_SRC_CTRL4:
314 case RT5677_DSP_INB3_SRC_CTRL4:
315 case RT5677_DSP_OUTB1_SRC_CTRL4:
316 case RT5677_DSP_OUTB2_SRC_CTRL4:
317 case RT5677_VENDOR_ID:
318 case RT5677_VENDOR_ID1:
319 case RT5677_VENDOR_ID2:
320 return true;
321 default:
322 return false;
323 }
324 }
325
326 static bool rt5677_readable_register(struct device *dev, unsigned int reg)
327 {
328 int i;
329
330 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
331 if (reg >= rt5677_ranges[i].range_min &&
332 reg <= rt5677_ranges[i].range_max) {
333 return true;
334 }
335 }
336
337 switch (reg) {
338 case RT5677_RESET:
339 case RT5677_LOUT1:
340 case RT5677_IN1:
341 case RT5677_MICBIAS:
342 case RT5677_SLIMBUS_PARAM:
343 case RT5677_SLIMBUS_RX:
344 case RT5677_SLIMBUS_CTRL:
345 case RT5677_SIDETONE_CTRL:
346 case RT5677_ANA_DAC1_2_3_SRC:
347 case RT5677_IF_DSP_DAC3_4_MIXER:
348 case RT5677_DAC4_DIG_VOL:
349 case RT5677_DAC3_DIG_VOL:
350 case RT5677_DAC1_DIG_VOL:
351 case RT5677_DAC2_DIG_VOL:
352 case RT5677_IF_DSP_DAC2_MIXER:
353 case RT5677_STO1_ADC_DIG_VOL:
354 case RT5677_MONO_ADC_DIG_VOL:
355 case RT5677_STO1_2_ADC_BST:
356 case RT5677_STO2_ADC_DIG_VOL:
357 case RT5677_ADC_BST_CTRL2:
358 case RT5677_STO3_4_ADC_BST:
359 case RT5677_STO3_ADC_DIG_VOL:
360 case RT5677_STO4_ADC_DIG_VOL:
361 case RT5677_STO4_ADC_MIXER:
362 case RT5677_STO3_ADC_MIXER:
363 case RT5677_STO2_ADC_MIXER:
364 case RT5677_STO1_ADC_MIXER:
365 case RT5677_MONO_ADC_MIXER:
366 case RT5677_ADC_IF_DSP_DAC1_MIXER:
367 case RT5677_STO1_DAC_MIXER:
368 case RT5677_MONO_DAC_MIXER:
369 case RT5677_DD1_MIXER:
370 case RT5677_DD2_MIXER:
371 case RT5677_IF3_DATA:
372 case RT5677_IF4_DATA:
373 case RT5677_PDM_OUT_CTRL:
374 case RT5677_PDM_DATA_CTRL1:
375 case RT5677_PDM_DATA_CTRL2:
376 case RT5677_PDM1_DATA_CTRL2:
377 case RT5677_PDM1_DATA_CTRL3:
378 case RT5677_PDM1_DATA_CTRL4:
379 case RT5677_PDM2_DATA_CTRL2:
380 case RT5677_PDM2_DATA_CTRL3:
381 case RT5677_PDM2_DATA_CTRL4:
382 case RT5677_TDM1_CTRL1:
383 case RT5677_TDM1_CTRL2:
384 case RT5677_TDM1_CTRL3:
385 case RT5677_TDM1_CTRL4:
386 case RT5677_TDM1_CTRL5:
387 case RT5677_TDM2_CTRL1:
388 case RT5677_TDM2_CTRL2:
389 case RT5677_TDM2_CTRL3:
390 case RT5677_TDM2_CTRL4:
391 case RT5677_TDM2_CTRL5:
392 case RT5677_I2C_MASTER_CTRL1:
393 case RT5677_I2C_MASTER_CTRL2:
394 case RT5677_I2C_MASTER_CTRL3:
395 case RT5677_I2C_MASTER_CTRL4:
396 case RT5677_I2C_MASTER_CTRL5:
397 case RT5677_I2C_MASTER_CTRL6:
398 case RT5677_I2C_MASTER_CTRL7:
399 case RT5677_I2C_MASTER_CTRL8:
400 case RT5677_DMIC_CTRL1:
401 case RT5677_DMIC_CTRL2:
402 case RT5677_HAP_GENE_CTRL1:
403 case RT5677_HAP_GENE_CTRL2:
404 case RT5677_HAP_GENE_CTRL3:
405 case RT5677_HAP_GENE_CTRL4:
406 case RT5677_HAP_GENE_CTRL5:
407 case RT5677_HAP_GENE_CTRL6:
408 case RT5677_HAP_GENE_CTRL7:
409 case RT5677_HAP_GENE_CTRL8:
410 case RT5677_HAP_GENE_CTRL9:
411 case RT5677_HAP_GENE_CTRL10:
412 case RT5677_PWR_DIG1:
413 case RT5677_PWR_DIG2:
414 case RT5677_PWR_ANLG1:
415 case RT5677_PWR_ANLG2:
416 case RT5677_PWR_DSP1:
417 case RT5677_PWR_DSP_ST:
418 case RT5677_PWR_DSP2:
419 case RT5677_ADC_DAC_HPF_CTRL1:
420 case RT5677_PRIV_INDEX:
421 case RT5677_PRIV_DATA:
422 case RT5677_I2S4_SDP:
423 case RT5677_I2S1_SDP:
424 case RT5677_I2S2_SDP:
425 case RT5677_I2S3_SDP:
426 case RT5677_CLK_TREE_CTRL1:
427 case RT5677_CLK_TREE_CTRL2:
428 case RT5677_CLK_TREE_CTRL3:
429 case RT5677_PLL1_CTRL1:
430 case RT5677_PLL1_CTRL2:
431 case RT5677_PLL2_CTRL1:
432 case RT5677_PLL2_CTRL2:
433 case RT5677_GLB_CLK1:
434 case RT5677_GLB_CLK2:
435 case RT5677_ASRC_1:
436 case RT5677_ASRC_2:
437 case RT5677_ASRC_3:
438 case RT5677_ASRC_4:
439 case RT5677_ASRC_5:
440 case RT5677_ASRC_6:
441 case RT5677_ASRC_7:
442 case RT5677_ASRC_8:
443 case RT5677_ASRC_9:
444 case RT5677_ASRC_10:
445 case RT5677_ASRC_11:
446 case RT5677_ASRC_12:
447 case RT5677_ASRC_13:
448 case RT5677_ASRC_14:
449 case RT5677_ASRC_15:
450 case RT5677_ASRC_16:
451 case RT5677_ASRC_17:
452 case RT5677_ASRC_18:
453 case RT5677_ASRC_19:
454 case RT5677_ASRC_20:
455 case RT5677_ASRC_21:
456 case RT5677_ASRC_22:
457 case RT5677_ASRC_23:
458 case RT5677_VAD_CTRL1:
459 case RT5677_VAD_CTRL2:
460 case RT5677_VAD_CTRL3:
461 case RT5677_VAD_CTRL4:
462 case RT5677_VAD_CTRL5:
463 case RT5677_DSP_INB_CTRL1:
464 case RT5677_DSP_INB_CTRL2:
465 case RT5677_DSP_IN_OUTB_CTRL:
466 case RT5677_DSP_OUTB0_1_DIG_VOL:
467 case RT5677_DSP_OUTB2_3_DIG_VOL:
468 case RT5677_DSP_OUTB4_5_DIG_VOL:
469 case RT5677_DSP_OUTB6_7_DIG_VOL:
470 case RT5677_ADC_EQ_CTRL1:
471 case RT5677_ADC_EQ_CTRL2:
472 case RT5677_EQ_CTRL1:
473 case RT5677_EQ_CTRL2:
474 case RT5677_EQ_CTRL3:
475 case RT5677_SOFT_VOL_ZERO_CROSS1:
476 case RT5677_JD_CTRL1:
477 case RT5677_JD_CTRL2:
478 case RT5677_JD_CTRL3:
479 case RT5677_IRQ_CTRL1:
480 case RT5677_IRQ_CTRL2:
481 case RT5677_GPIO_ST:
482 case RT5677_GPIO_CTRL1:
483 case RT5677_GPIO_CTRL2:
484 case RT5677_GPIO_CTRL3:
485 case RT5677_STO1_ADC_HI_FILTER1:
486 case RT5677_STO1_ADC_HI_FILTER2:
487 case RT5677_MONO_ADC_HI_FILTER1:
488 case RT5677_MONO_ADC_HI_FILTER2:
489 case RT5677_STO2_ADC_HI_FILTER1:
490 case RT5677_STO2_ADC_HI_FILTER2:
491 case RT5677_STO3_ADC_HI_FILTER1:
492 case RT5677_STO3_ADC_HI_FILTER2:
493 case RT5677_STO4_ADC_HI_FILTER1:
494 case RT5677_STO4_ADC_HI_FILTER2:
495 case RT5677_MB_DRC_CTRL1:
496 case RT5677_DRC1_CTRL1:
497 case RT5677_DRC1_CTRL2:
498 case RT5677_DRC1_CTRL3:
499 case RT5677_DRC1_CTRL4:
500 case RT5677_DRC1_CTRL5:
501 case RT5677_DRC1_CTRL6:
502 case RT5677_DRC2_CTRL1:
503 case RT5677_DRC2_CTRL2:
504 case RT5677_DRC2_CTRL3:
505 case RT5677_DRC2_CTRL4:
506 case RT5677_DRC2_CTRL5:
507 case RT5677_DRC2_CTRL6:
508 case RT5677_DRC1_HL_CTRL1:
509 case RT5677_DRC1_HL_CTRL2:
510 case RT5677_DRC2_HL_CTRL1:
511 case RT5677_DRC2_HL_CTRL2:
512 case RT5677_DSP_INB1_SRC_CTRL1:
513 case RT5677_DSP_INB1_SRC_CTRL2:
514 case RT5677_DSP_INB1_SRC_CTRL3:
515 case RT5677_DSP_INB1_SRC_CTRL4:
516 case RT5677_DSP_INB2_SRC_CTRL1:
517 case RT5677_DSP_INB2_SRC_CTRL2:
518 case RT5677_DSP_INB2_SRC_CTRL3:
519 case RT5677_DSP_INB2_SRC_CTRL4:
520 case RT5677_DSP_INB3_SRC_CTRL1:
521 case RT5677_DSP_INB3_SRC_CTRL2:
522 case RT5677_DSP_INB3_SRC_CTRL3:
523 case RT5677_DSP_INB3_SRC_CTRL4:
524 case RT5677_DSP_OUTB1_SRC_CTRL1:
525 case RT5677_DSP_OUTB1_SRC_CTRL2:
526 case RT5677_DSP_OUTB1_SRC_CTRL3:
527 case RT5677_DSP_OUTB1_SRC_CTRL4:
528 case RT5677_DSP_OUTB2_SRC_CTRL1:
529 case RT5677_DSP_OUTB2_SRC_CTRL2:
530 case RT5677_DSP_OUTB2_SRC_CTRL3:
531 case RT5677_DSP_OUTB2_SRC_CTRL4:
532 case RT5677_DSP_OUTB_0123_MIXER_CTRL:
533 case RT5677_DSP_OUTB_45_MIXER_CTRL:
534 case RT5677_DSP_OUTB_67_MIXER_CTRL:
535 case RT5677_DIG_MISC:
536 case RT5677_GEN_CTRL1:
537 case RT5677_GEN_CTRL2:
538 case RT5677_VENDOR_ID:
539 case RT5677_VENDOR_ID1:
540 case RT5677_VENDOR_ID2:
541 return true;
542 default:
543 return false;
544 }
545 }
546
547
548
549
550
551
552
553
554
555
556 static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
557 unsigned int addr, unsigned int value, unsigned int opcode)
558 {
559 struct snd_soc_component *component = rt5677->component;
560 int ret;
561
562 mutex_lock(&rt5677->dsp_cmd_lock);
563
564 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
565 addr >> 16);
566 if (ret < 0) {
567 dev_err(component->dev, "Failed to set addr msb value: %d\n", ret);
568 goto err;
569 }
570
571 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
572 addr & 0xffff);
573 if (ret < 0) {
574 dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret);
575 goto err;
576 }
577
578 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
579 value >> 16);
580 if (ret < 0) {
581 dev_err(component->dev, "Failed to set data msb value: %d\n", ret);
582 goto err;
583 }
584
585 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
586 value & 0xffff);
587 if (ret < 0) {
588 dev_err(component->dev, "Failed to set data lsb value: %d\n", ret);
589 goto err;
590 }
591
592 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
593 opcode);
594 if (ret < 0) {
595 dev_err(component->dev, "Failed to set op code value: %d\n", ret);
596 goto err;
597 }
598
599 err:
600 mutex_unlock(&rt5677->dsp_cmd_lock);
601
602 return ret;
603 }
604
605
606
607
608
609
610
611
612
613
614 static int rt5677_dsp_mode_i2c_read_addr(
615 struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
616 {
617 struct snd_soc_component *component = rt5677->component;
618 int ret;
619 unsigned int msb, lsb;
620
621 mutex_lock(&rt5677->dsp_cmd_lock);
622
623 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
624 addr >> 16);
625 if (ret < 0) {
626 dev_err(component->dev, "Failed to set addr msb value: %d\n", ret);
627 goto err;
628 }
629
630 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
631 addr & 0xffff);
632 if (ret < 0) {
633 dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret);
634 goto err;
635 }
636
637 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
638 0x0002);
639 if (ret < 0) {
640 dev_err(component->dev, "Failed to set op code value: %d\n", ret);
641 goto err;
642 }
643
644 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
645 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
646 *value = (msb << 16) | lsb;
647
648 err:
649 mutex_unlock(&rt5677->dsp_cmd_lock);
650
651 return ret;
652 }
653
654
655
656
657
658
659
660
661
662
663 static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
664 unsigned int reg, unsigned int value)
665 {
666 return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
667 value, 0x0001);
668 }
669
670
671
672
673
674
675
676
677
678
679 static int rt5677_dsp_mode_i2c_read(
680 struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
681 {
682 int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
683 value);
684
685 *value &= 0xffff;
686
687 return ret;
688 }
689
690 static void rt5677_set_dsp_mode(struct snd_soc_component *component, bool on)
691 {
692 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
693
694 if (on) {
695 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
696 RT5677_PWR_DSP, RT5677_PWR_DSP);
697 rt5677->is_dsp_mode = true;
698 } else {
699 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
700 RT5677_PWR_DSP, 0x0);
701 rt5677->is_dsp_mode = false;
702 }
703 }
704
705 static int rt5677_set_dsp_vad(struct snd_soc_component *component, bool on)
706 {
707 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
708 static bool activity;
709 int ret;
710
711 if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI))
712 return -ENXIO;
713
714 if (on && !activity) {
715 activity = true;
716
717 regcache_cache_only(rt5677->regmap, false);
718 regcache_cache_bypass(rt5677->regmap, true);
719
720 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1);
721 regmap_update_bits(rt5677->regmap,
722 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00);
723 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
724 RT5677_LDO1_SEL_MASK, 0x0);
725 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
726 RT5677_PWR_LDO1, RT5677_PWR_LDO1);
727 switch (rt5677->type) {
728 case RT5677:
729 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
730 RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC);
731 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
732 RT5677_PLL2_PR_SRC_MASK |
733 RT5677_DSP_CLK_SRC_MASK,
734 RT5677_PLL2_PR_SRC_MCLK2 |
735 RT5677_DSP_CLK_SRC_BYPASS);
736 break;
737 case RT5676:
738 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
739 RT5677_DSP_CLK_SRC_MASK,
740 RT5677_DSP_CLK_SRC_BYPASS);
741 break;
742 default:
743 break;
744 }
745 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff);
746 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd);
747 rt5677_set_dsp_mode(component, true);
748
749 ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1,
750 component->dev);
751 if (ret == 0) {
752 rt5677_spi_write_firmware(0x50000000, rt5677->fw1);
753 release_firmware(rt5677->fw1);
754 }
755
756 ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2,
757 component->dev);
758 if (ret == 0) {
759 rt5677_spi_write_firmware(0x60000000, rt5677->fw2);
760 release_firmware(rt5677->fw2);
761 }
762
763 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0);
764
765 regcache_cache_bypass(rt5677->regmap, false);
766 regcache_cache_only(rt5677->regmap, true);
767 } else if (!on && activity) {
768 activity = false;
769
770 regcache_cache_only(rt5677->regmap, false);
771 regcache_cache_bypass(rt5677->regmap, true);
772
773 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1);
774 rt5677_set_dsp_mode(component, false);
775 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001);
776
777 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
778
779 regcache_cache_bypass(rt5677->regmap, false);
780 regcache_mark_dirty(rt5677->regmap);
781 regcache_sync(rt5677->regmap);
782 }
783
784 return 0;
785 }
786
787 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
788 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
789 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
790 static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
791
792
793 static const DECLARE_TLV_DB_RANGE(bst_tlv,
794 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
795 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
796 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
797 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
798 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
799 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
800 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
801 );
802
803 static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
804 struct snd_ctl_elem_value *ucontrol)
805 {
806 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
807 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
808
809 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en;
810
811 return 0;
812 }
813
814 static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
815 struct snd_ctl_elem_value *ucontrol)
816 {
817 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
818 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
819
820 rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
821
822 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
823 rt5677_set_dsp_vad(component, rt5677->dsp_vad_en);
824
825 return 0;
826 }
827
828 static const struct snd_kcontrol_new rt5677_snd_controls[] = {
829
830 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
831 RT5677_LOUT1_L_MUTE_SFT, 1, 1),
832 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
833 RT5677_LOUT2_L_MUTE_SFT, 1, 1),
834 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
835 RT5677_LOUT3_L_MUTE_SFT, 1, 1),
836
837
838 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
839 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv),
840 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
841 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv),
842 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
843 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv),
844 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
845 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv),
846
847
848 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
849 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
850
851
852 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
853 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
854 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
855 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
856 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
857 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
858 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
859 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
860 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
861 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
862
863 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
864 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
865 adc_vol_tlv),
866 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
867 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
868 adc_vol_tlv),
869 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
870 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
871 adc_vol_tlv),
872 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
873 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
874 adc_vol_tlv),
875 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
876 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0,
877 adc_vol_tlv),
878
879
880 SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
881 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),
882
883
884 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
885 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
886 adc_bst_tlv),
887 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
888 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
889 adc_bst_tlv),
890 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
891 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
892 adc_bst_tlv),
893 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
894 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
895 adc_bst_tlv),
896 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
897 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
898 adc_bst_tlv),
899
900 SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0,
901 rt5677_dsp_vad_get, rt5677_dsp_vad_put),
902 };
903
904
905
906
907
908
909
910
911
912
913
914 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
915 struct snd_kcontrol *kcontrol, int event)
916 {
917 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
918 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
919 int idx, rate;
920
921 rate = rt5677->sysclk / rl6231_get_pre_div(rt5677->regmap,
922 RT5677_CLK_TREE_CTRL1, RT5677_I2S_PD1_SFT);
923 idx = rl6231_calc_dmic_clk(rate);
924 if (idx < 0)
925 dev_err(component->dev, "Failed to set DMIC clock\n");
926 else
927 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
928 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
929 return idx;
930 }
931
932 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
933 struct snd_soc_dapm_widget *sink)
934 {
935 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
936 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
937 unsigned int val;
938
939 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
940 val &= RT5677_SCLK_SRC_MASK;
941 if (val == RT5677_SCLK_SRC_PLL1)
942 return 1;
943 else
944 return 0;
945 }
946
947 static int is_using_asrc(struct snd_soc_dapm_widget *source,
948 struct snd_soc_dapm_widget *sink)
949 {
950 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
951 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
952 unsigned int reg, shift, val;
953
954 if (source->reg == RT5677_ASRC_1) {
955 switch (source->shift) {
956 case 12:
957 reg = RT5677_ASRC_4;
958 shift = 0;
959 break;
960 case 13:
961 reg = RT5677_ASRC_4;
962 shift = 4;
963 break;
964 case 14:
965 reg = RT5677_ASRC_4;
966 shift = 8;
967 break;
968 case 15:
969 reg = RT5677_ASRC_4;
970 shift = 12;
971 break;
972 default:
973 return 0;
974 }
975 } else {
976 switch (source->shift) {
977 case 0:
978 reg = RT5677_ASRC_6;
979 shift = 8;
980 break;
981 case 1:
982 reg = RT5677_ASRC_6;
983 shift = 12;
984 break;
985 case 2:
986 reg = RT5677_ASRC_5;
987 shift = 0;
988 break;
989 case 3:
990 reg = RT5677_ASRC_5;
991 shift = 4;
992 break;
993 case 4:
994 reg = RT5677_ASRC_5;
995 shift = 8;
996 break;
997 case 5:
998 reg = RT5677_ASRC_5;
999 shift = 12;
1000 break;
1001 case 12:
1002 reg = RT5677_ASRC_3;
1003 shift = 0;
1004 break;
1005 case 13:
1006 reg = RT5677_ASRC_3;
1007 shift = 4;
1008 break;
1009 case 14:
1010 reg = RT5677_ASRC_3;
1011 shift = 12;
1012 break;
1013 default:
1014 return 0;
1015 }
1016 }
1017
1018 regmap_read(rt5677->regmap, reg, &val);
1019 val = (val >> shift) & 0xf;
1020
1021 switch (val) {
1022 case 1 ... 6:
1023 return 1;
1024 default:
1025 return 0;
1026 }
1027
1028 }
1029
1030 static int can_use_asrc(struct snd_soc_dapm_widget *source,
1031 struct snd_soc_dapm_widget *sink)
1032 {
1033 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
1034 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
1035
1036 if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384)
1037 return 1;
1038
1039 return 0;
1040 }
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056 int rt5677_sel_asrc_clk_src(struct snd_soc_component *component,
1057 unsigned int filter_mask, unsigned int clk_src)
1058 {
1059 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
1060 unsigned int asrc3_mask = 0, asrc3_value = 0;
1061 unsigned int asrc4_mask = 0, asrc4_value = 0;
1062 unsigned int asrc5_mask = 0, asrc5_value = 0;
1063 unsigned int asrc6_mask = 0, asrc6_value = 0;
1064 unsigned int asrc7_mask = 0, asrc7_value = 0;
1065 unsigned int asrc8_mask = 0, asrc8_value = 0;
1066
1067 switch (clk_src) {
1068 case RT5677_CLK_SEL_SYS:
1069 case RT5677_CLK_SEL_I2S1_ASRC:
1070 case RT5677_CLK_SEL_I2S2_ASRC:
1071 case RT5677_CLK_SEL_I2S3_ASRC:
1072 case RT5677_CLK_SEL_I2S4_ASRC:
1073 case RT5677_CLK_SEL_I2S5_ASRC:
1074 case RT5677_CLK_SEL_I2S6_ASRC:
1075 case RT5677_CLK_SEL_SYS2:
1076 case RT5677_CLK_SEL_SYS3:
1077 case RT5677_CLK_SEL_SYS4:
1078 case RT5677_CLK_SEL_SYS5:
1079 case RT5677_CLK_SEL_SYS6:
1080 case RT5677_CLK_SEL_SYS7:
1081 break;
1082
1083 default:
1084 return -EINVAL;
1085 }
1086
1087
1088 if (filter_mask & RT5677_DA_STEREO_FILTER) {
1089 asrc3_mask |= RT5677_DA_STO_CLK_SEL_MASK;
1090 asrc3_value = (asrc3_value & ~RT5677_DA_STO_CLK_SEL_MASK)
1091 | (clk_src << RT5677_DA_STO_CLK_SEL_SFT);
1092 }
1093
1094 if (filter_mask & RT5677_DA_MONO2_L_FILTER) {
1095 asrc3_mask |= RT5677_DA_MONO2L_CLK_SEL_MASK;
1096 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2L_CLK_SEL_MASK)
1097 | (clk_src << RT5677_DA_MONO2L_CLK_SEL_SFT);
1098 }
1099
1100 if (filter_mask & RT5677_DA_MONO2_R_FILTER) {
1101 asrc3_mask |= RT5677_DA_MONO2R_CLK_SEL_MASK;
1102 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2R_CLK_SEL_MASK)
1103 | (clk_src << RT5677_DA_MONO2R_CLK_SEL_SFT);
1104 }
1105
1106 if (asrc3_mask)
1107 regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask,
1108 asrc3_value);
1109
1110
1111 if (filter_mask & RT5677_DA_MONO3_L_FILTER) {
1112 asrc4_mask |= RT5677_DA_MONO3L_CLK_SEL_MASK;
1113 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3L_CLK_SEL_MASK)
1114 | (clk_src << RT5677_DA_MONO3L_CLK_SEL_SFT);
1115 }
1116
1117 if (filter_mask & RT5677_DA_MONO3_R_FILTER) {
1118 asrc4_mask |= RT5677_DA_MONO3R_CLK_SEL_MASK;
1119 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3R_CLK_SEL_MASK)
1120 | (clk_src << RT5677_DA_MONO3R_CLK_SEL_SFT);
1121 }
1122
1123 if (filter_mask & RT5677_DA_MONO4_L_FILTER) {
1124 asrc4_mask |= RT5677_DA_MONO4L_CLK_SEL_MASK;
1125 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4L_CLK_SEL_MASK)
1126 | (clk_src << RT5677_DA_MONO4L_CLK_SEL_SFT);
1127 }
1128
1129 if (filter_mask & RT5677_DA_MONO4_R_FILTER) {
1130 asrc4_mask |= RT5677_DA_MONO4R_CLK_SEL_MASK;
1131 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4R_CLK_SEL_MASK)
1132 | (clk_src << RT5677_DA_MONO4R_CLK_SEL_SFT);
1133 }
1134
1135 if (asrc4_mask)
1136 regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask,
1137 asrc4_value);
1138
1139
1140 if (filter_mask & RT5677_AD_STEREO1_FILTER) {
1141 asrc5_mask |= RT5677_AD_STO1_CLK_SEL_MASK;
1142 asrc5_value = (asrc5_value & ~RT5677_AD_STO1_CLK_SEL_MASK)
1143 | (clk_src << RT5677_AD_STO1_CLK_SEL_SFT);
1144 }
1145
1146 if (filter_mask & RT5677_AD_STEREO2_FILTER) {
1147 asrc5_mask |= RT5677_AD_STO2_CLK_SEL_MASK;
1148 asrc5_value = (asrc5_value & ~RT5677_AD_STO2_CLK_SEL_MASK)
1149 | (clk_src << RT5677_AD_STO2_CLK_SEL_SFT);
1150 }
1151
1152 if (filter_mask & RT5677_AD_STEREO3_FILTER) {
1153 asrc5_mask |= RT5677_AD_STO3_CLK_SEL_MASK;
1154 asrc5_value = (asrc5_value & ~RT5677_AD_STO3_CLK_SEL_MASK)
1155 | (clk_src << RT5677_AD_STO3_CLK_SEL_SFT);
1156 }
1157
1158 if (filter_mask & RT5677_AD_STEREO4_FILTER) {
1159 asrc5_mask |= RT5677_AD_STO4_CLK_SEL_MASK;
1160 asrc5_value = (asrc5_value & ~RT5677_AD_STO4_CLK_SEL_MASK)
1161 | (clk_src << RT5677_AD_STO4_CLK_SEL_SFT);
1162 }
1163
1164 if (asrc5_mask)
1165 regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask,
1166 asrc5_value);
1167
1168
1169 if (filter_mask & RT5677_AD_MONO_L_FILTER) {
1170 asrc6_mask |= RT5677_AD_MONOL_CLK_SEL_MASK;
1171 asrc6_value = (asrc6_value & ~RT5677_AD_MONOL_CLK_SEL_MASK)
1172 | (clk_src << RT5677_AD_MONOL_CLK_SEL_SFT);
1173 }
1174
1175 if (filter_mask & RT5677_AD_MONO_R_FILTER) {
1176 asrc6_mask |= RT5677_AD_MONOR_CLK_SEL_MASK;
1177 asrc6_value = (asrc6_value & ~RT5677_AD_MONOR_CLK_SEL_MASK)
1178 | (clk_src << RT5677_AD_MONOR_CLK_SEL_SFT);
1179 }
1180
1181 if (asrc6_mask)
1182 regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask,
1183 asrc6_value);
1184
1185
1186 if (filter_mask & RT5677_DSP_OB_0_3_FILTER) {
1187 asrc7_mask |= RT5677_DSP_OB_0_3_CLK_SEL_MASK;
1188 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_0_3_CLK_SEL_MASK)
1189 | (clk_src << RT5677_DSP_OB_0_3_CLK_SEL_SFT);
1190 }
1191
1192 if (filter_mask & RT5677_DSP_OB_4_7_FILTER) {
1193 asrc7_mask |= RT5677_DSP_OB_4_7_CLK_SEL_MASK;
1194 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_4_7_CLK_SEL_MASK)
1195 | (clk_src << RT5677_DSP_OB_4_7_CLK_SEL_SFT);
1196 }
1197
1198 if (asrc7_mask)
1199 regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask,
1200 asrc7_value);
1201
1202
1203 if (filter_mask & RT5677_I2S1_SOURCE) {
1204 asrc8_mask |= RT5677_I2S1_CLK_SEL_MASK;
1205 asrc8_value = (asrc8_value & ~RT5677_I2S1_CLK_SEL_MASK)
1206 | ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT);
1207 }
1208
1209 if (filter_mask & RT5677_I2S2_SOURCE) {
1210 asrc8_mask |= RT5677_I2S2_CLK_SEL_MASK;
1211 asrc8_value = (asrc8_value & ~RT5677_I2S2_CLK_SEL_MASK)
1212 | ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT);
1213 }
1214
1215 if (filter_mask & RT5677_I2S3_SOURCE) {
1216 asrc8_mask |= RT5677_I2S3_CLK_SEL_MASK;
1217 asrc8_value = (asrc8_value & ~RT5677_I2S3_CLK_SEL_MASK)
1218 | ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT);
1219 }
1220
1221 if (filter_mask & RT5677_I2S4_SOURCE) {
1222 asrc8_mask |= RT5677_I2S4_CLK_SEL_MASK;
1223 asrc8_value = (asrc8_value & ~RT5677_I2S4_CLK_SEL_MASK)
1224 | ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT);
1225 }
1226
1227 if (asrc8_mask)
1228 regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask,
1229 asrc8_value);
1230
1231 return 0;
1232 }
1233 EXPORT_SYMBOL_GPL(rt5677_sel_asrc_clk_src);
1234
1235 static int rt5677_dmic_use_asrc(struct snd_soc_dapm_widget *source,
1236 struct snd_soc_dapm_widget *sink)
1237 {
1238 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
1239 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
1240 unsigned int asrc_setting;
1241
1242 switch (source->shift) {
1243 case 11:
1244 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1245 asrc_setting = (asrc_setting & RT5677_AD_STO1_CLK_SEL_MASK) >>
1246 RT5677_AD_STO1_CLK_SEL_SFT;
1247 break;
1248
1249 case 10:
1250 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1251 asrc_setting = (asrc_setting & RT5677_AD_STO2_CLK_SEL_MASK) >>
1252 RT5677_AD_STO2_CLK_SEL_SFT;
1253 break;
1254
1255 case 9:
1256 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1257 asrc_setting = (asrc_setting & RT5677_AD_STO3_CLK_SEL_MASK) >>
1258 RT5677_AD_STO3_CLK_SEL_SFT;
1259 break;
1260
1261 case 8:
1262 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1263 asrc_setting = (asrc_setting & RT5677_AD_STO4_CLK_SEL_MASK) >>
1264 RT5677_AD_STO4_CLK_SEL_SFT;
1265 break;
1266
1267 case 7:
1268 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1269 asrc_setting = (asrc_setting & RT5677_AD_MONOL_CLK_SEL_MASK) >>
1270 RT5677_AD_MONOL_CLK_SEL_SFT;
1271 break;
1272
1273 case 6:
1274 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1275 asrc_setting = (asrc_setting & RT5677_AD_MONOR_CLK_SEL_MASK) >>
1276 RT5677_AD_MONOR_CLK_SEL_SFT;
1277 break;
1278
1279 default:
1280 return 0;
1281 }
1282
1283 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1284 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1285 return 1;
1286
1287 return 0;
1288 }
1289
1290
1291 static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
1292 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1293 RT5677_M_STO1_ADC_L1_SFT, 1, 1),
1294 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1295 RT5677_M_STO1_ADC_L2_SFT, 1, 1),
1296 };
1297
1298 static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
1299 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1300 RT5677_M_STO1_ADC_R1_SFT, 1, 1),
1301 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1302 RT5677_M_STO1_ADC_R2_SFT, 1, 1),
1303 };
1304
1305 static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
1306 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1307 RT5677_M_STO2_ADC_L1_SFT, 1, 1),
1308 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1309 RT5677_M_STO2_ADC_L2_SFT, 1, 1),
1310 };
1311
1312 static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
1313 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1314 RT5677_M_STO2_ADC_R1_SFT, 1, 1),
1315 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1316 RT5677_M_STO2_ADC_R2_SFT, 1, 1),
1317 };
1318
1319 static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
1320 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1321 RT5677_M_STO3_ADC_L1_SFT, 1, 1),
1322 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1323 RT5677_M_STO3_ADC_L2_SFT, 1, 1),
1324 };
1325
1326 static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
1327 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1328 RT5677_M_STO3_ADC_R1_SFT, 1, 1),
1329 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1330 RT5677_M_STO3_ADC_R2_SFT, 1, 1),
1331 };
1332
1333 static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
1334 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1335 RT5677_M_STO4_ADC_L1_SFT, 1, 1),
1336 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1337 RT5677_M_STO4_ADC_L2_SFT, 1, 1),
1338 };
1339
1340 static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
1341 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1342 RT5677_M_STO4_ADC_R1_SFT, 1, 1),
1343 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1344 RT5677_M_STO4_ADC_R2_SFT, 1, 1),
1345 };
1346
1347 static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
1348 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1349 RT5677_M_MONO_ADC_L1_SFT, 1, 1),
1350 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1351 RT5677_M_MONO_ADC_L2_SFT, 1, 1),
1352 };
1353
1354 static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
1355 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1356 RT5677_M_MONO_ADC_R1_SFT, 1, 1),
1357 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1358 RT5677_M_MONO_ADC_R2_SFT, 1, 1),
1359 };
1360
1361 static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
1362 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1363 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
1364 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1365 RT5677_M_DAC1_L_SFT, 1, 1),
1366 };
1367
1368 static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
1369 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1370 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
1371 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1372 RT5677_M_DAC1_R_SFT, 1, 1),
1373 };
1374
1375 static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
1376 SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_STO1_DAC_MIXER,
1377 RT5677_M_ST_DAC1_L_SFT, 1, 1),
1378 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1379 RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
1380 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
1381 RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
1382 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1383 RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
1384 };
1385
1386 static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
1387 SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_STO1_DAC_MIXER,
1388 RT5677_M_ST_DAC1_R_SFT, 1, 1),
1389 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1390 RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
1391 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
1392 RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
1393 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1394 RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
1395 };
1396
1397 static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
1398 SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_MONO_DAC_MIXER,
1399 RT5677_M_ST_DAC2_L_SFT, 1, 1),
1400 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
1401 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
1402 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1403 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
1404 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1405 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
1406 };
1407
1408 static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
1409 SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_MONO_DAC_MIXER,
1410 RT5677_M_ST_DAC2_R_SFT, 1, 1),
1411 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
1412 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
1413 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1414 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
1415 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1416 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
1417 };
1418
1419 static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
1420 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
1421 RT5677_M_STO_L_DD1_L_SFT, 1, 1),
1422 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
1423 RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
1424 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER,
1425 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
1426 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER,
1427 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
1428 };
1429
1430 static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
1431 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
1432 RT5677_M_STO_R_DD1_R_SFT, 1, 1),
1433 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
1434 RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
1435 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER,
1436 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
1437 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER,
1438 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
1439 };
1440
1441 static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
1442 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
1443 RT5677_M_STO_L_DD2_L_SFT, 1, 1),
1444 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
1445 RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
1446 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER,
1447 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
1448 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER,
1449 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
1450 };
1451
1452 static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
1453 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
1454 RT5677_M_STO_R_DD2_R_SFT, 1, 1),
1455 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
1456 RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
1457 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER,
1458 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
1459 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER,
1460 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
1461 };
1462
1463 static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
1464 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1465 RT5677_DSP_IB_01_H_SFT, 1, 1),
1466 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1467 RT5677_DSP_IB_23_H_SFT, 1, 1),
1468 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1469 RT5677_DSP_IB_45_H_SFT, 1, 1),
1470 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1471 RT5677_DSP_IB_6_H_SFT, 1, 1),
1472 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1473 RT5677_DSP_IB_7_H_SFT, 1, 1),
1474 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1475 RT5677_DSP_IB_8_H_SFT, 1, 1),
1476 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1477 RT5677_DSP_IB_9_H_SFT, 1, 1),
1478 };
1479
1480 static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
1481 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1482 RT5677_DSP_IB_01_L_SFT, 1, 1),
1483 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1484 RT5677_DSP_IB_23_L_SFT, 1, 1),
1485 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1486 RT5677_DSP_IB_45_L_SFT, 1, 1),
1487 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1488 RT5677_DSP_IB_6_L_SFT, 1, 1),
1489 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1490 RT5677_DSP_IB_7_L_SFT, 1, 1),
1491 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1492 RT5677_DSP_IB_8_L_SFT, 1, 1),
1493 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1494 RT5677_DSP_IB_9_L_SFT, 1, 1),
1495 };
1496
1497 static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
1498 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1499 RT5677_DSP_IB_01_H_SFT, 1, 1),
1500 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1501 RT5677_DSP_IB_23_H_SFT, 1, 1),
1502 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1503 RT5677_DSP_IB_45_H_SFT, 1, 1),
1504 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1505 RT5677_DSP_IB_6_H_SFT, 1, 1),
1506 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1507 RT5677_DSP_IB_7_H_SFT, 1, 1),
1508 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1509 RT5677_DSP_IB_8_H_SFT, 1, 1),
1510 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1511 RT5677_DSP_IB_9_H_SFT, 1, 1),
1512 };
1513
1514 static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
1515 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1516 RT5677_DSP_IB_01_L_SFT, 1, 1),
1517 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1518 RT5677_DSP_IB_23_L_SFT, 1, 1),
1519 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1520 RT5677_DSP_IB_45_L_SFT, 1, 1),
1521 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1522 RT5677_DSP_IB_6_L_SFT, 1, 1),
1523 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1524 RT5677_DSP_IB_7_L_SFT, 1, 1),
1525 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1526 RT5677_DSP_IB_8_L_SFT, 1, 1),
1527 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1528 RT5677_DSP_IB_9_L_SFT, 1, 1),
1529 };
1530
1531 static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
1532 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1533 RT5677_DSP_IB_01_H_SFT, 1, 1),
1534 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1535 RT5677_DSP_IB_23_H_SFT, 1, 1),
1536 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1537 RT5677_DSP_IB_45_H_SFT, 1, 1),
1538 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1539 RT5677_DSP_IB_6_H_SFT, 1, 1),
1540 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1541 RT5677_DSP_IB_7_H_SFT, 1, 1),
1542 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1543 RT5677_DSP_IB_8_H_SFT, 1, 1),
1544 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1545 RT5677_DSP_IB_9_H_SFT, 1, 1),
1546 };
1547
1548 static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
1549 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1550 RT5677_DSP_IB_01_L_SFT, 1, 1),
1551 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1552 RT5677_DSP_IB_23_L_SFT, 1, 1),
1553 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1554 RT5677_DSP_IB_45_L_SFT, 1, 1),
1555 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1556 RT5677_DSP_IB_6_L_SFT, 1, 1),
1557 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1558 RT5677_DSP_IB_7_L_SFT, 1, 1),
1559 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1560 RT5677_DSP_IB_8_L_SFT, 1, 1),
1561 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1562 RT5677_DSP_IB_9_L_SFT, 1, 1),
1563 };
1564
1565
1566
1567
1568 static const char * const rt5677_dac1_src[] = {
1569 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
1570 "OB 01"
1571 };
1572
1573 static SOC_ENUM_SINGLE_DECL(
1574 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1575 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
1576
1577 static const struct snd_kcontrol_new rt5677_dac1_mux =
1578 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
1579
1580
1581 static const char * const rt5677_adda1_src[] = {
1582 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
1583 };
1584
1585 static SOC_ENUM_SINGLE_DECL(
1586 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1587 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
1588
1589 static const struct snd_kcontrol_new rt5677_adda1_mux =
1590 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
1591
1592
1593
1594 static const char * const rt5677_dac2l_src[] = {
1595 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
1596 "OB 2",
1597 };
1598
1599 static SOC_ENUM_SINGLE_DECL(
1600 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
1601 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
1602
1603 static const struct snd_kcontrol_new rt5677_dac2_l_mux =
1604 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
1605
1606 static const char * const rt5677_dac2r_src[] = {
1607 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
1608 "OB 3", "Haptic Generator", "VAD ADC"
1609 };
1610
1611 static SOC_ENUM_SINGLE_DECL(
1612 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
1613 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
1614
1615 static const struct snd_kcontrol_new rt5677_dac2_r_mux =
1616 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
1617
1618
1619 static const char * const rt5677_dac3l_src[] = {
1620 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
1621 "SLB DAC 4", "OB 4"
1622 };
1623
1624 static SOC_ENUM_SINGLE_DECL(
1625 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1626 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1627
1628 static const struct snd_kcontrol_new rt5677_dac3_l_mux =
1629 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
1630
1631 static const char * const rt5677_dac3r_src[] = {
1632 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1633 "SLB DAC 5", "OB 5"
1634 };
1635
1636 static SOC_ENUM_SINGLE_DECL(
1637 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1638 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1639
1640 static const struct snd_kcontrol_new rt5677_dac3_r_mux =
1641 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
1642
1643
1644 static const char * const rt5677_dac4l_src[] = {
1645 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1646 "SLB DAC 6", "OB 6"
1647 };
1648
1649 static SOC_ENUM_SINGLE_DECL(
1650 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1651 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1652
1653 static const struct snd_kcontrol_new rt5677_dac4_l_mux =
1654 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
1655
1656 static const char * const rt5677_dac4r_src[] = {
1657 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1658 "SLB DAC 7", "OB 7"
1659 };
1660
1661 static SOC_ENUM_SINGLE_DECL(
1662 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1663 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1664
1665 static const struct snd_kcontrol_new rt5677_dac4_r_mux =
1666 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
1667
1668
1669 static const char * const rt5677_iob_bypass_src[] = {
1670 "Bypass", "Pass SRC"
1671 };
1672
1673 static SOC_ENUM_SINGLE_DECL(
1674 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1675 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1676
1677 static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
1678 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
1679
1680 static SOC_ENUM_SINGLE_DECL(
1681 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1682 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1683
1684 static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
1685 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
1686
1687 static SOC_ENUM_SINGLE_DECL(
1688 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1689 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1690
1691 static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
1692 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
1693
1694 static SOC_ENUM_SINGLE_DECL(
1695 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1696 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1697
1698 static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
1699 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
1700
1701 static SOC_ENUM_SINGLE_DECL(
1702 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1703 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1704
1705 static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
1706 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
1707
1708
1709 static const char * const rt5677_stereo_adc2_src[] = {
1710 "DD MIX1", "DMIC", "Stereo DAC MIX"
1711 };
1712
1713 static SOC_ENUM_SINGLE_DECL(
1714 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1715 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1716
1717 static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
1718 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
1719
1720 static SOC_ENUM_SINGLE_DECL(
1721 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1722 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1723
1724 static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
1725 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
1726
1727 static SOC_ENUM_SINGLE_DECL(
1728 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1729 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1730
1731 static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
1732 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
1733
1734
1735 static const char * const rt5677_dmic_src[] = {
1736 "DMIC1", "DMIC2", "DMIC3", "DMIC4"
1737 };
1738
1739 static SOC_ENUM_SINGLE_DECL(
1740 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1741 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1742
1743 static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
1744 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
1745
1746 static SOC_ENUM_SINGLE_DECL(
1747 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1748 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1749
1750 static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
1751 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
1752
1753 static SOC_ENUM_SINGLE_DECL(
1754 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1755 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1756
1757 static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
1758 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
1759
1760 static SOC_ENUM_SINGLE_DECL(
1761 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1762 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1763
1764 static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
1765 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
1766
1767 static SOC_ENUM_SINGLE_DECL(
1768 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1769 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1770
1771 static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
1772 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
1773
1774 static SOC_ENUM_SINGLE_DECL(
1775 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1776 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1777
1778 static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
1779 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
1780
1781
1782 static const char * const rt5677_stereo2_adc_lr_src[] = {
1783 "L", "LR"
1784 };
1785
1786 static SOC_ENUM_SINGLE_DECL(
1787 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1788 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1789
1790 static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
1791 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
1792
1793
1794 static const char * const rt5677_stereo_adc1_src[] = {
1795 "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1796 };
1797
1798 static SOC_ENUM_SINGLE_DECL(
1799 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1800 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1801
1802 static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
1803 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
1804
1805 static SOC_ENUM_SINGLE_DECL(
1806 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1807 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1808
1809 static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
1810 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
1811
1812 static SOC_ENUM_SINGLE_DECL(
1813 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1814 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1815
1816 static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
1817 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
1818
1819
1820 static const char * const rt5677_mono_adc2_l_src[] = {
1821 "DD MIX1L", "DMIC", "MONO DAC MIXL"
1822 };
1823
1824 static SOC_ENUM_SINGLE_DECL(
1825 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1826 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1827
1828 static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
1829 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
1830
1831
1832 static const char * const rt5677_mono_adc1_l_src[] = {
1833 "DD MIX1L", "ADC1", "MONO DAC MIXL"
1834 };
1835
1836 static SOC_ENUM_SINGLE_DECL(
1837 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1838 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1839
1840 static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
1841 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
1842
1843
1844 static const char * const rt5677_mono_adc2_r_src[] = {
1845 "DD MIX1R", "DMIC", "MONO DAC MIXR"
1846 };
1847
1848 static SOC_ENUM_SINGLE_DECL(
1849 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1850 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1851
1852 static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
1853 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
1854
1855
1856 static const char * const rt5677_mono_adc1_r_src[] = {
1857 "DD MIX1R", "ADC2", "MONO DAC MIXR"
1858 };
1859
1860 static SOC_ENUM_SINGLE_DECL(
1861 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1862 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1863
1864 static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
1865 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
1866
1867
1868 static const char * const rt5677_stereo4_adc2_src[] = {
1869 "DD MIX1", "DMIC", "DD MIX2"
1870 };
1871
1872 static SOC_ENUM_SINGLE_DECL(
1873 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1874 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1875
1876 static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
1877 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
1878
1879
1880
1881 static const char * const rt5677_stereo4_adc1_src[] = {
1882 "DD MIX1", "ADC1/2", "DD MIX2"
1883 };
1884
1885 static SOC_ENUM_SINGLE_DECL(
1886 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1887 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1888
1889 static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
1890 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
1891
1892
1893 static const char * const rt5677_inbound01_src[] = {
1894 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1895 "VAD ADC/DAC1 FS"
1896 };
1897
1898 static SOC_ENUM_SINGLE_DECL(
1899 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1900 RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1901
1902 static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1903 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1904
1905
1906 static const char * const rt5677_inbound23_src[] = {
1907 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1908 "DAC1 FS", "IF4 DAC"
1909 };
1910
1911 static SOC_ENUM_SINGLE_DECL(
1912 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1913 RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1914
1915 static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1916 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1917
1918
1919 static const char * const rt5677_inbound45_src[] = {
1920 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1921 "IF3 DAC"
1922 };
1923
1924 static SOC_ENUM_SINGLE_DECL(
1925 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1926 RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1927
1928 static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1929 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1930
1931
1932 static const char * const rt5677_inbound6_src[] = {
1933 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1934 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1935 };
1936
1937 static SOC_ENUM_SINGLE_DECL(
1938 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1939 RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1940
1941 static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1942 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1943
1944
1945 static const char * const rt5677_inbound7_src[] = {
1946 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1947 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1948 };
1949
1950 static SOC_ENUM_SINGLE_DECL(
1951 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1952 RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1953
1954 static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1955 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1956
1957
1958 static const char * const rt5677_inbound8_src[] = {
1959 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1960 "MONO ADC MIX L", "DACL1 FS"
1961 };
1962
1963 static SOC_ENUM_SINGLE_DECL(
1964 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1965 RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1966
1967 static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1968 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1969
1970
1971 static const char * const rt5677_inbound9_src[] = {
1972 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1973 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1974 };
1975
1976 static SOC_ENUM_SINGLE_DECL(
1977 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1978 RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1979
1980 static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1981 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1982
1983
1984 static const char * const rt5677_vad_src[] = {
1985 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
1986 "STO3 ADC MIX L"
1987 };
1988
1989 static SOC_ENUM_SINGLE_DECL(
1990 rt5677_vad_enum, RT5677_VAD_CTRL4,
1991 RT5677_VAD_SRC_SFT, rt5677_vad_src);
1992
1993 static const struct snd_kcontrol_new rt5677_vad_src_mux =
1994 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
1995
1996
1997 static const char * const rt5677_sidetone_src[] = {
1998 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
1999 };
2000
2001 static SOC_ENUM_SINGLE_DECL(
2002 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
2003 RT5677_ST_SEL_SFT, rt5677_sidetone_src);
2004
2005 static const struct snd_kcontrol_new rt5677_sidetone_mux =
2006 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
2007
2008
2009 static const char * const rt5677_dac12_src[] = {
2010 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
2011 };
2012
2013 static SOC_ENUM_SINGLE_DECL(
2014 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
2015 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
2016
2017 static const struct snd_kcontrol_new rt5677_dac12_mux =
2018 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
2019
2020
2021 static const char * const rt5677_dac3_src[] = {
2022 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
2023 };
2024
2025 static SOC_ENUM_SINGLE_DECL(
2026 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
2027 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
2028
2029 static const struct snd_kcontrol_new rt5677_dac3_mux =
2030 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
2031
2032
2033 static const char * const rt5677_pdm_src[] = {
2034 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
2035 };
2036
2037 static SOC_ENUM_SINGLE_DECL(
2038 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
2039 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
2040
2041 static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
2042 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
2043
2044 static SOC_ENUM_SINGLE_DECL(
2045 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
2046 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
2047
2048 static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
2049 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
2050
2051 static SOC_ENUM_SINGLE_DECL(
2052 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
2053 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
2054
2055 static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
2056 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
2057
2058 static SOC_ENUM_SINGLE_DECL(
2059 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
2060 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
2061
2062 static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
2063 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
2064
2065
2066 static const char * const rt5677_if12_adc1_src[] = {
2067 "STO1 ADC MIX", "OB01", "VAD ADC"
2068 };
2069
2070 static SOC_ENUM_SINGLE_DECL(
2071 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
2072 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
2073
2074 static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
2075 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
2076
2077 static SOC_ENUM_SINGLE_DECL(
2078 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
2079 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
2080
2081 static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
2082 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
2083
2084 static SOC_ENUM_SINGLE_DECL(
2085 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
2086 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
2087
2088 static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
2089 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
2090
2091
2092 static const char * const rt5677_if12_adc2_src[] = {
2093 "STO2 ADC MIX", "OB23"
2094 };
2095
2096 static SOC_ENUM_SINGLE_DECL(
2097 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
2098 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
2099
2100 static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
2101 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
2102
2103 static SOC_ENUM_SINGLE_DECL(
2104 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
2105 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
2106
2107 static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
2108 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
2109
2110 static SOC_ENUM_SINGLE_DECL(
2111 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
2112 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
2113
2114 static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
2115 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
2116
2117
2118 static const char * const rt5677_if12_adc3_src[] = {
2119 "STO3 ADC MIX", "MONO ADC MIX", "OB45"
2120 };
2121
2122 static SOC_ENUM_SINGLE_DECL(
2123 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
2124 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
2125
2126 static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
2127 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
2128
2129 static SOC_ENUM_SINGLE_DECL(
2130 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
2131 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
2132
2133 static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
2134 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
2135
2136 static SOC_ENUM_SINGLE_DECL(
2137 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
2138 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
2139
2140 static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
2141 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
2142
2143
2144 static const char * const rt5677_if12_adc4_src[] = {
2145 "STO4 ADC MIX", "OB67", "OB01"
2146 };
2147
2148 static SOC_ENUM_SINGLE_DECL(
2149 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
2150 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
2151
2152 static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
2153 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
2154
2155 static SOC_ENUM_SINGLE_DECL(
2156 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
2157 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
2158
2159 static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
2160 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
2161
2162 static SOC_ENUM_SINGLE_DECL(
2163 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
2164 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
2165
2166 static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
2167 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
2168
2169
2170 static const char * const rt5677_if34_adc_src[] = {
2171 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
2172 "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
2173 };
2174
2175 static SOC_ENUM_SINGLE_DECL(
2176 rt5677_if3_adc_enum, RT5677_IF3_DATA,
2177 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
2178
2179 static const struct snd_kcontrol_new rt5677_if3_adc_mux =
2180 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
2181
2182 static SOC_ENUM_SINGLE_DECL(
2183 rt5677_if4_adc_enum, RT5677_IF4_DATA,
2184 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
2185
2186 static const struct snd_kcontrol_new rt5677_if4_adc_mux =
2187 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
2188
2189
2190 static const char * const rt5677_if12_adc_swap_src[] = {
2191 "L/R", "R/L", "L/L", "R/R"
2192 };
2193
2194 static SOC_ENUM_SINGLE_DECL(
2195 rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1,
2196 RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src);
2197
2198 static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux =
2199 SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum);
2200
2201 static SOC_ENUM_SINGLE_DECL(
2202 rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1,
2203 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2204
2205 static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux =
2206 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum);
2207
2208 static SOC_ENUM_SINGLE_DECL(
2209 rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1,
2210 RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2211
2212 static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux =
2213 SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum);
2214
2215 static SOC_ENUM_SINGLE_DECL(
2216 rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1,
2217 RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2218
2219 static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux =
2220 SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum);
2221
2222 static SOC_ENUM_SINGLE_DECL(
2223 rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1,
2224 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2225
2226 static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux =
2227 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum);
2228
2229 static SOC_ENUM_SINGLE_DECL(
2230 rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1,
2231 RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2232
2233 static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux =
2234 SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum);
2235
2236 static SOC_ENUM_SINGLE_DECL(
2237 rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1,
2238 RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2239
2240 static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux =
2241 SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum);
2242
2243 static SOC_ENUM_SINGLE_DECL(
2244 rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1,
2245 RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2246
2247 static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux =
2248 SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum);
2249
2250
2251 static const char * const rt5677_if1_adc_tdm_swap_src[] = {
2252 "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2253 "3/1/2/4", "3/4/1/2"
2254 };
2255
2256 static SOC_ENUM_SINGLE_DECL(
2257 rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2,
2258 RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src);
2259
2260 static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux =
2261 SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum);
2262
2263
2264 static const char * const rt5677_if2_adc_tdm_swap_src[] = {
2265 "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2266 "2/3/1/4", "3/4/1/2"
2267 };
2268
2269 static SOC_ENUM_SINGLE_DECL(
2270 rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2,
2271 RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src);
2272
2273 static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux =
2274 SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum);
2275
2276
2277
2278
2279
2280 static const char * const rt5677_if12_dac_tdm_sel_src[] = {
2281 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
2282 };
2283
2284 static SOC_ENUM_SINGLE_DECL(
2285 rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4,
2286 RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2287
2288 static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux =
2289 SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum);
2290
2291 static SOC_ENUM_SINGLE_DECL(
2292 rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4,
2293 RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2294
2295 static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux =
2296 SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum);
2297
2298 static SOC_ENUM_SINGLE_DECL(
2299 rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4,
2300 RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2301
2302 static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux =
2303 SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum);
2304
2305 static SOC_ENUM_SINGLE_DECL(
2306 rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4,
2307 RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2308
2309 static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux =
2310 SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum);
2311
2312 static SOC_ENUM_SINGLE_DECL(
2313 rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5,
2314 RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2315
2316 static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux =
2317 SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum);
2318
2319 static SOC_ENUM_SINGLE_DECL(
2320 rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5,
2321 RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2322
2323 static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux =
2324 SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum);
2325
2326 static SOC_ENUM_SINGLE_DECL(
2327 rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5,
2328 RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2329
2330 static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux =
2331 SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum);
2332
2333 static SOC_ENUM_SINGLE_DECL(
2334 rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5,
2335 RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2336
2337 static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux =
2338 SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum);
2339
2340 static SOC_ENUM_SINGLE_DECL(
2341 rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4,
2342 RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2343
2344 static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux =
2345 SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum);
2346
2347 static SOC_ENUM_SINGLE_DECL(
2348 rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4,
2349 RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2350
2351 static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux =
2352 SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum);
2353
2354 static SOC_ENUM_SINGLE_DECL(
2355 rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4,
2356 RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2357
2358 static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux =
2359 SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum);
2360
2361 static SOC_ENUM_SINGLE_DECL(
2362 rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4,
2363 RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2364
2365 static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux =
2366 SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum);
2367
2368 static SOC_ENUM_SINGLE_DECL(
2369 rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5,
2370 RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2371
2372 static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux =
2373 SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum);
2374
2375 static SOC_ENUM_SINGLE_DECL(
2376 rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5,
2377 RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2378
2379 static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux =
2380 SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum);
2381
2382 static SOC_ENUM_SINGLE_DECL(
2383 rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5,
2384 RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2385
2386 static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux =
2387 SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum);
2388
2389 static SOC_ENUM_SINGLE_DECL(
2390 rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5,
2391 RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2392
2393 static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux =
2394 SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum);
2395
2396 static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
2397 struct snd_kcontrol *kcontrol, int event)
2398 {
2399 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2400 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2401
2402 switch (event) {
2403 case SND_SOC_DAPM_POST_PMU:
2404 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2405 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
2406 break;
2407
2408 case SND_SOC_DAPM_PRE_PMD:
2409 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2410 RT5677_PWR_BST1_P, 0);
2411 break;
2412
2413 default:
2414 return 0;
2415 }
2416
2417 return 0;
2418 }
2419
2420 static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
2421 struct snd_kcontrol *kcontrol, int event)
2422 {
2423 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2424 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2425
2426 switch (event) {
2427 case SND_SOC_DAPM_POST_PMU:
2428 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2429 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
2430 break;
2431
2432 case SND_SOC_DAPM_PRE_PMD:
2433 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2434 RT5677_PWR_BST2_P, 0);
2435 break;
2436
2437 default:
2438 return 0;
2439 }
2440
2441 return 0;
2442 }
2443
2444 static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
2445 struct snd_kcontrol *kcontrol, int event)
2446 {
2447 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2448 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2449
2450 switch (event) {
2451 case SND_SOC_DAPM_PRE_PMU:
2452 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
2453 break;
2454
2455 case SND_SOC_DAPM_POST_PMU:
2456 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
2457 break;
2458
2459 default:
2460 return 0;
2461 }
2462
2463 return 0;
2464 }
2465
2466 static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
2467 struct snd_kcontrol *kcontrol, int event)
2468 {
2469 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2470 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2471
2472 switch (event) {
2473 case SND_SOC_DAPM_PRE_PMU:
2474 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
2475 break;
2476
2477 case SND_SOC_DAPM_POST_PMU:
2478 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
2479 break;
2480
2481 default:
2482 return 0;
2483 }
2484
2485 return 0;
2486 }
2487
2488 static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
2489 struct snd_kcontrol *kcontrol, int event)
2490 {
2491 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2492 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2493
2494 switch (event) {
2495 case SND_SOC_DAPM_POST_PMU:
2496 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2497 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2498 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
2499 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
2500 break;
2501
2502 case SND_SOC_DAPM_PRE_PMD:
2503 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2504 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2505 RT5677_PWR_CLK_MB, 0);
2506 break;
2507
2508 default:
2509 return 0;
2510 }
2511
2512 return 0;
2513 }
2514
2515 static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w,
2516 struct snd_kcontrol *kcontrol, int event)
2517 {
2518 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2519 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2520 unsigned int value;
2521
2522 switch (event) {
2523 case SND_SOC_DAPM_PRE_PMU:
2524 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
2525 if (value & RT5677_IF1_ADC_CTRL_MASK)
2526 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
2527 RT5677_IF1_ADC_MODE_MASK,
2528 RT5677_IF1_ADC_MODE_TDM);
2529 break;
2530
2531 default:
2532 return 0;
2533 }
2534
2535 return 0;
2536 }
2537
2538 static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w,
2539 struct snd_kcontrol *kcontrol, int event)
2540 {
2541 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2542 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2543 unsigned int value;
2544
2545 switch (event) {
2546 case SND_SOC_DAPM_PRE_PMU:
2547 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
2548 if (value & RT5677_IF2_ADC_CTRL_MASK)
2549 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
2550 RT5677_IF2_ADC_MODE_MASK,
2551 RT5677_IF2_ADC_MODE_TDM);
2552 break;
2553
2554 default:
2555 return 0;
2556 }
2557
2558 return 0;
2559 }
2560
2561 static int rt5677_vref_event(struct snd_soc_dapm_widget *w,
2562 struct snd_kcontrol *kcontrol, int event)
2563 {
2564 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2565 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
2566
2567 switch (event) {
2568 case SND_SOC_DAPM_POST_PMU:
2569 if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_ON &&
2570 !rt5677->is_vref_slow) {
2571 mdelay(20);
2572 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
2573 RT5677_PWR_FV1 | RT5677_PWR_FV2,
2574 RT5677_PWR_FV1 | RT5677_PWR_FV2);
2575 rt5677->is_vref_slow = true;
2576 }
2577 break;
2578
2579 default:
2580 return 0;
2581 }
2582
2583 return 0;
2584 }
2585
2586 static int rt5677_filter_power_event(struct snd_soc_dapm_widget *w,
2587 struct snd_kcontrol *kcontrol, int event)
2588 {
2589 switch (event) {
2590 case SND_SOC_DAPM_POST_PMU:
2591 msleep(50);
2592 break;
2593
2594 default:
2595 return 0;
2596 }
2597
2598 return 0;
2599 }
2600
2601 static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
2602 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
2603 0, rt5677_set_pll1_event, SND_SOC_DAPM_PRE_PMU |
2604 SND_SOC_DAPM_POST_PMU),
2605 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
2606 0, rt5677_set_pll2_event, SND_SOC_DAPM_PRE_PMU |
2607 SND_SOC_DAPM_POST_PMU),
2608
2609
2610 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0),
2611 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0),
2612 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0),
2613 SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0),
2614 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0,
2615 rt5677_filter_power_event, SND_SOC_DAPM_POST_PMU),
2616 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL,
2617 0),
2618 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL,
2619 0),
2620 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL,
2621 0),
2622 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL,
2623 0),
2624 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL,
2625 0),
2626 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL,
2627 0),
2628 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL,
2629 0),
2630 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL,
2631 0),
2632 SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL,
2633 0),
2634 SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL,
2635 0),
2636 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL,
2637 0),
2638 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL,
2639 0),
2640 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0),
2641 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0),
2642 SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0),
2643 SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0),
2644 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL,
2645 0),
2646 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL,
2647 0),
2648
2649
2650
2651 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
2652 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
2653 SND_SOC_DAPM_POST_PMU),
2654
2655
2656 SND_SOC_DAPM_INPUT("DMIC L1"),
2657 SND_SOC_DAPM_INPUT("DMIC R1"),
2658 SND_SOC_DAPM_INPUT("DMIC L2"),
2659 SND_SOC_DAPM_INPUT("DMIC R2"),
2660 SND_SOC_DAPM_INPUT("DMIC L3"),
2661 SND_SOC_DAPM_INPUT("DMIC R3"),
2662 SND_SOC_DAPM_INPUT("DMIC L4"),
2663 SND_SOC_DAPM_INPUT("DMIC R4"),
2664
2665 SND_SOC_DAPM_INPUT("IN1P"),
2666 SND_SOC_DAPM_INPUT("IN1N"),
2667 SND_SOC_DAPM_INPUT("IN2P"),
2668 SND_SOC_DAPM_INPUT("IN2N"),
2669
2670 SND_SOC_DAPM_INPUT("Haptic Generator"),
2671
2672 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2673 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2674 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2675 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2676
2677 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
2678 RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
2679 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
2680 RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
2681 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
2682 RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
2683 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
2684 RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
2685
2686 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2687 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2688
2689
2690 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
2691 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
2692 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2693 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
2694 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
2695 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2696
2697
2698 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
2699 0, 0),
2700 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
2701 0, 0),
2702 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
2703
2704 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
2705 RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
2706 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
2707 RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
2708 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
2709 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
2710 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
2711 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
2712
2713
2714 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2715 &rt5677_sto1_dmic_mux),
2716 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2717 &rt5677_sto1_adc1_mux),
2718 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2719 &rt5677_sto1_adc2_mux),
2720 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
2721 &rt5677_sto2_dmic_mux),
2722 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2723 &rt5677_sto2_adc1_mux),
2724 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2725 &rt5677_sto2_adc2_mux),
2726 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
2727 &rt5677_sto2_adc_lr_mux),
2728 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
2729 &rt5677_sto3_dmic_mux),
2730 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2731 &rt5677_sto3_adc1_mux),
2732 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2733 &rt5677_sto3_adc2_mux),
2734 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
2735 &rt5677_sto4_dmic_mux),
2736 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2737 &rt5677_sto4_adc1_mux),
2738 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2739 &rt5677_sto4_adc2_mux),
2740 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2741 &rt5677_mono_dmic_l_mux),
2742 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2743 &rt5677_mono_dmic_r_mux),
2744 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
2745 &rt5677_mono_adc2_l_mux),
2746 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
2747 &rt5677_mono_adc1_l_mux),
2748 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
2749 &rt5677_mono_adc1_r_mux),
2750 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
2751 &rt5677_mono_adc2_r_mux),
2752
2753
2754 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
2755 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
2756 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
2757 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
2758 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
2759 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
2760 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
2761 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
2762 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2763 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
2764 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2765 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
2766 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
2767 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
2768 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
2769 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
2770 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
2771 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
2772 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
2773 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
2774 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
2775 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
2776 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
2777 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
2778 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
2779 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2780 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2781 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
2782 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
2783 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2784 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2785 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
2786
2787
2788 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2789 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2790 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2791 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2792 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2793 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2794 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2795 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2796 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2797 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2798 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2799 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2800 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2801 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2802 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2803 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2804
2805
2806 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
2807 &rt5677_ib9_src_mux),
2808 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
2809 &rt5677_ib8_src_mux),
2810 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
2811 &rt5677_ib7_src_mux),
2812 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
2813 &rt5677_ib6_src_mux),
2814 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
2815 &rt5677_ib45_src_mux),
2816 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
2817 &rt5677_ib23_src_mux),
2818 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
2819 &rt5677_ib01_src_mux),
2820 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
2821 &rt5677_ib45_bypass_src_mux),
2822 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2823 &rt5677_ib23_bypass_src_mux),
2824 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2825 &rt5677_ib01_bypass_src_mux),
2826 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2827 &rt5677_ob23_bypass_src_mux),
2828 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2829 &rt5677_ob01_bypass_src_mux),
2830
2831 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
2832 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
2833
2834 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
2835 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
2836 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
2837 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
2838 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
2839 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
2840
2841
2842 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
2843 RT5677_PWR_I2S1_BIT, 0, NULL, 0),
2844 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2845 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2846 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2847 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2848 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2849 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2850 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2851 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2852 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2853 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2854 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2855 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2856 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2857 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2858 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2859 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2860
2861 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
2862 RT5677_PWR_I2S2_BIT, 0, NULL, 0),
2863 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2864 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2865 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2866 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2867 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2868 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2869 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2870 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2871 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2872 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2873 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2874 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2875 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2876 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2877 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2878 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2879
2880 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
2881 RT5677_PWR_I2S3_BIT, 0, NULL, 0),
2882 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2883 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2884 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2885 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2886 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2887 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2888
2889 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
2890 RT5677_PWR_I2S4_BIT, 0, NULL, 0),
2891 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2892 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2893 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2894 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2895 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2896 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2897
2898 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
2899 RT5677_PWR_SLB_BIT, 0, NULL, 0),
2900 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2901 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2902 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2903 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2904 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2905 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2906 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2907 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2908 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2909 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2910 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2911 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2912 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2913 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2914 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2915 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2916
2917
2918 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2919 &rt5677_if1_adc1_mux),
2920 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2921 &rt5677_if1_adc2_mux),
2922 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2923 &rt5677_if1_adc3_mux),
2924 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2925 &rt5677_if1_adc4_mux),
2926 SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2927 &rt5677_if1_adc1_swap_mux),
2928 SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2929 &rt5677_if1_adc2_swap_mux),
2930 SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2931 &rt5677_if1_adc3_swap_mux),
2932 SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2933 &rt5677_if1_adc4_swap_mux),
2934 SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2935 &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event,
2936 SND_SOC_DAPM_PRE_PMU),
2937 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2938 &rt5677_if2_adc1_mux),
2939 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2940 &rt5677_if2_adc2_mux),
2941 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2942 &rt5677_if2_adc3_mux),
2943 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2944 &rt5677_if2_adc4_mux),
2945 SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2946 &rt5677_if2_adc1_swap_mux),
2947 SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2948 &rt5677_if2_adc2_swap_mux),
2949 SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2950 &rt5677_if2_adc3_swap_mux),
2951 SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2952 &rt5677_if2_adc4_swap_mux),
2953 SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2954 &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event,
2955 SND_SOC_DAPM_PRE_PMU),
2956 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2957 &rt5677_if3_adc_mux),
2958 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
2959 &rt5677_if4_adc_mux),
2960 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
2961 &rt5677_slb_adc1_mux),
2962 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
2963 &rt5677_slb_adc2_mux),
2964 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
2965 &rt5677_slb_adc3_mux),
2966 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
2967 &rt5677_slb_adc4_mux),
2968
2969 SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2970 &rt5677_if1_dac0_tdm_sel_mux),
2971 SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2972 &rt5677_if1_dac1_tdm_sel_mux),
2973 SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2974 &rt5677_if1_dac2_tdm_sel_mux),
2975 SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2976 &rt5677_if1_dac3_tdm_sel_mux),
2977 SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2978 &rt5677_if1_dac4_tdm_sel_mux),
2979 SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2980 &rt5677_if1_dac5_tdm_sel_mux),
2981 SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2982 &rt5677_if1_dac6_tdm_sel_mux),
2983 SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2984 &rt5677_if1_dac7_tdm_sel_mux),
2985
2986 SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2987 &rt5677_if2_dac0_tdm_sel_mux),
2988 SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2989 &rt5677_if2_dac1_tdm_sel_mux),
2990 SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2991 &rt5677_if2_dac2_tdm_sel_mux),
2992 SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2993 &rt5677_if2_dac3_tdm_sel_mux),
2994 SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2995 &rt5677_if2_dac4_tdm_sel_mux),
2996 SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2997 &rt5677_if2_dac5_tdm_sel_mux),
2998 SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2999 &rt5677_if2_dac6_tdm_sel_mux),
3000 SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0,
3001 &rt5677_if2_dac7_tdm_sel_mux),
3002
3003
3004 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
3005 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
3006 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
3007 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
3008 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
3009 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
3010 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
3011 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
3012 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
3013 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
3014
3015
3016 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
3017 &rt5677_sidetone_mux),
3018 SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL,
3019 RT5677_ST_EN_SFT, 0, NULL, 0),
3020
3021
3022 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
3023 &rt5677_vad_src_mux),
3024
3025
3026 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
3027 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
3028 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
3029 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
3030 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
3031 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
3032 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
3033 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
3034 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
3035 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
3036 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
3037 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
3038 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
3039
3040
3041
3042 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
3043 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
3044 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
3045 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
3046 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
3047
3048
3049 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
3050 &rt5677_dac1_mux),
3051 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
3052 &rt5677_adda1_mux),
3053 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
3054 &rt5677_dac12_mux),
3055 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
3056 &rt5677_dac3_mux),
3057
3058
3059 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
3060 &rt5677_dac2_l_mux),
3061 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
3062 &rt5677_dac2_r_mux),
3063
3064
3065 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
3066 &rt5677_dac3_l_mux),
3067 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
3068 &rt5677_dac3_r_mux),
3069
3070
3071 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
3072 &rt5677_dac4_l_mux),
3073 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
3074 &rt5677_dac4_r_mux),
3075
3076
3077 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
3078 RT5677_PWR_DAC_S1F_BIT, 0, rt5677_filter_power_event,
3079 SND_SOC_DAPM_POST_PMU),
3080 SND_SOC_DAPM_SUPPLY("dac mono2 left filter", RT5677_PWR_DIG2,
3081 RT5677_PWR_DAC_M2F_L_BIT, 0, rt5677_filter_power_event,
3082 SND_SOC_DAPM_POST_PMU),
3083 SND_SOC_DAPM_SUPPLY("dac mono2 right filter", RT5677_PWR_DIG2,
3084 RT5677_PWR_DAC_M2F_R_BIT, 0, rt5677_filter_power_event,
3085 SND_SOC_DAPM_POST_PMU),
3086 SND_SOC_DAPM_SUPPLY("dac mono3 left filter", RT5677_PWR_DIG2,
3087 RT5677_PWR_DAC_M3F_L_BIT, 0, rt5677_filter_power_event,
3088 SND_SOC_DAPM_POST_PMU),
3089 SND_SOC_DAPM_SUPPLY("dac mono3 right filter", RT5677_PWR_DIG2,
3090 RT5677_PWR_DAC_M3F_R_BIT, 0, rt5677_filter_power_event,
3091 SND_SOC_DAPM_POST_PMU),
3092 SND_SOC_DAPM_SUPPLY("dac mono4 left filter", RT5677_PWR_DIG2,
3093 RT5677_PWR_DAC_M4F_L_BIT, 0, rt5677_filter_power_event,
3094 SND_SOC_DAPM_POST_PMU),
3095 SND_SOC_DAPM_SUPPLY("dac mono4 right filter", RT5677_PWR_DIG2,
3096 RT5677_PWR_DAC_M4F_R_BIT, 0, rt5677_filter_power_event,
3097 SND_SOC_DAPM_POST_PMU),
3098
3099 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
3100 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
3101 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
3102 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
3103 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
3104 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
3105 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
3106 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
3107 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
3108 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
3109 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
3110 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
3111 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
3112 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
3113 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
3114 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
3115 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3116 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3117 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3118 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3119
3120
3121 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
3122 RT5677_PWR_DAC1_BIT, 0),
3123 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
3124 RT5677_PWR_DAC2_BIT, 0),
3125 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
3126 RT5677_PWR_DAC3_BIT, 0),
3127
3128
3129 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
3130 RT5677_PWR_PDM1_BIT, 0, NULL, 0),
3131 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
3132 RT5677_PWR_PDM2_BIT, 0, NULL, 0),
3133
3134 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
3135 1, &rt5677_pdm1_l_mux),
3136 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
3137 1, &rt5677_pdm1_r_mux),
3138 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
3139 1, &rt5677_pdm2_l_mux),
3140 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
3141 1, &rt5677_pdm2_r_mux),
3142
3143 SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
3144 0, NULL, 0),
3145 SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
3146 0, NULL, 0),
3147 SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
3148 0, NULL, 0),
3149
3150 SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0,
3151 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3152 SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0,
3153 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3154 SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0,
3155 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3156
3157
3158 SND_SOC_DAPM_OUTPUT("LOUT1"),
3159 SND_SOC_DAPM_OUTPUT("LOUT2"),
3160 SND_SOC_DAPM_OUTPUT("LOUT3"),
3161 SND_SOC_DAPM_OUTPUT("PDM1L"),
3162 SND_SOC_DAPM_OUTPUT("PDM1R"),
3163 SND_SOC_DAPM_OUTPUT("PDM2L"),
3164 SND_SOC_DAPM_OUTPUT("PDM2R"),
3165
3166 SND_SOC_DAPM_POST("vref", rt5677_vref_event),
3167 };
3168
3169 static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
3170 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", rt5677_dmic_use_asrc },
3171 { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", rt5677_dmic_use_asrc },
3172 { "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", rt5677_dmic_use_asrc },
3173 { "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", rt5677_dmic_use_asrc },
3174 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", rt5677_dmic_use_asrc },
3175 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", rt5677_dmic_use_asrc },
3176 { "I2S1", NULL, "I2S1 ASRC", can_use_asrc},
3177 { "I2S2", NULL, "I2S2 ASRC", can_use_asrc},
3178 { "I2S3", NULL, "I2S3 ASRC", can_use_asrc},
3179 { "I2S4", NULL, "I2S4 ASRC", can_use_asrc},
3180
3181 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
3182 { "dac mono2 left filter", NULL, "DAC MONO2 L ASRC", is_using_asrc },
3183 { "dac mono2 right filter", NULL, "DAC MONO2 R ASRC", is_using_asrc },
3184 { "dac mono3 left filter", NULL, "DAC MONO3 L ASRC", is_using_asrc },
3185 { "dac mono3 right filter", NULL, "DAC MONO3 R ASRC", is_using_asrc },
3186 { "dac mono4 left filter", NULL, "DAC MONO4 L ASRC", is_using_asrc },
3187 { "dac mono4 right filter", NULL, "DAC MONO4 R ASRC", is_using_asrc },
3188 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
3189 { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc },
3190 { "adc stereo3 filter", NULL, "ADC STO3 ASRC", is_using_asrc },
3191 { "adc stereo4 filter", NULL, "ADC STO4 ASRC", is_using_asrc },
3192 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
3193 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
3194
3195 { "DMIC1", NULL, "DMIC L1" },
3196 { "DMIC1", NULL, "DMIC R1" },
3197 { "DMIC2", NULL, "DMIC L2" },
3198 { "DMIC2", NULL, "DMIC R2" },
3199 { "DMIC3", NULL, "DMIC L3" },
3200 { "DMIC3", NULL, "DMIC R3" },
3201 { "DMIC4", NULL, "DMIC L4" },
3202 { "DMIC4", NULL, "DMIC R4" },
3203
3204 { "DMIC L1", NULL, "DMIC CLK" },
3205 { "DMIC R1", NULL, "DMIC CLK" },
3206 { "DMIC L2", NULL, "DMIC CLK" },
3207 { "DMIC R2", NULL, "DMIC CLK" },
3208 { "DMIC L3", NULL, "DMIC CLK" },
3209 { "DMIC R3", NULL, "DMIC CLK" },
3210 { "DMIC L4", NULL, "DMIC CLK" },
3211 { "DMIC R4", NULL, "DMIC CLK" },
3212
3213 { "DMIC L1", NULL, "DMIC1 power" },
3214 { "DMIC R1", NULL, "DMIC1 power" },
3215 { "DMIC L3", NULL, "DMIC3 power" },
3216 { "DMIC R3", NULL, "DMIC3 power" },
3217 { "DMIC L4", NULL, "DMIC4 power" },
3218 { "DMIC R4", NULL, "DMIC4 power" },
3219
3220 { "BST1", NULL, "IN1P" },
3221 { "BST1", NULL, "IN1N" },
3222 { "BST2", NULL, "IN2P" },
3223 { "BST2", NULL, "IN2N" },
3224
3225 { "IN1P", NULL, "MICBIAS1" },
3226 { "IN1N", NULL, "MICBIAS1" },
3227 { "IN2P", NULL, "MICBIAS1" },
3228 { "IN2N", NULL, "MICBIAS1" },
3229
3230 { "ADC 1", NULL, "BST1" },
3231 { "ADC 1", NULL, "ADC 1 power" },
3232 { "ADC 1", NULL, "ADC1 clock" },
3233 { "ADC 2", NULL, "BST2" },
3234 { "ADC 2", NULL, "ADC 2 power" },
3235 { "ADC 2", NULL, "ADC2 clock" },
3236
3237 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
3238 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
3239 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
3240 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
3241
3242 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
3243 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
3244 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
3245 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
3246
3247 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
3248 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
3249 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
3250 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
3251
3252 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
3253 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
3254 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
3255 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
3256
3257 { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
3258 { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
3259 { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
3260 { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
3261
3262 { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
3263 { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
3264 { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
3265 { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
3266
3267 { "ADC 1_2", NULL, "ADC 1" },
3268 { "ADC 1_2", NULL, "ADC 2" },
3269
3270 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3271 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3272 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3273
3274 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3275 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
3276 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3277
3278 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3279 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3280 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3281
3282 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3283 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
3284 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3285
3286 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3287 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3288 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3289
3290 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3291 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3292 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3293
3294 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3295 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3296 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
3297
3298 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3299 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3300 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
3301
3302 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
3303 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
3304 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3305
3306 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
3307 { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
3308 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3309
3310 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
3311 { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
3312 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3313
3314 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
3315 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
3316 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3317
3318 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3319 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3320 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3321 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3322
3323 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
3324 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
3325 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
3326 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
3327 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3328
3329 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
3330 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
3331
3332 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3333 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3334 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3335 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3336
3337 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
3338 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
3339
3340 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
3341 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
3342
3343 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
3344 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
3345 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
3346 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
3347 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
3348
3349 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
3350 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
3351
3352 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3353 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3354 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3355 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3356
3357 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
3358 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
3359 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
3360 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
3361 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
3362
3363 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
3364 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
3365
3366 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3367 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3368 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3369 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3370
3371 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
3372 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
3373 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
3374 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
3375 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
3376
3377 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
3378 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
3379
3380 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
3381 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
3382 { "Mono ADC MIXL", NULL, "adc mono left filter" },
3383 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
3384
3385 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
3386 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
3387 { "Mono ADC MIXR", NULL, "adc mono right filter" },
3388 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
3389
3390 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
3391 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
3392
3393 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3394 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3395 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3396 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3397 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3398
3399 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3400 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3401 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3402
3403 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3404 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3405
3406 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3407 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3408 { "IF1 ADC3 Mux", "OB45", "OB45" },
3409
3410 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3411 { "IF1 ADC4 Mux", "OB67", "OB67" },
3412 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3413
3414 { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" },
3415 { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" },
3416 { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" },
3417 { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" },
3418
3419 { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" },
3420 { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" },
3421 { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" },
3422 { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" },
3423
3424 { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" },
3425 { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" },
3426 { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" },
3427 { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" },
3428
3429 { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" },
3430 { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" },
3431 { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" },
3432 { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" },
3433
3434 { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" },
3435 { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" },
3436 { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" },
3437 { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" },
3438
3439 { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" },
3440 { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" },
3441 { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" },
3442 { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" },
3443 { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" },
3444 { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" },
3445 { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" },
3446 { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" },
3447
3448 { "AIF1TX", NULL, "I2S1" },
3449 { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" },
3450
3451 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3452 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3453 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3454
3455 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3456 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3457
3458 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3459 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3460 { "IF2 ADC3 Mux", "OB45", "OB45" },
3461
3462 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3463 { "IF2 ADC4 Mux", "OB67", "OB67" },
3464 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3465
3466 { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" },
3467 { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" },
3468 { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" },
3469 { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" },
3470
3471 { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" },
3472 { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" },
3473 { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" },
3474 { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" },
3475
3476 { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" },
3477 { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" },
3478 { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" },
3479 { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" },
3480
3481 { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" },
3482 { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" },
3483 { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" },
3484 { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" },
3485
3486 { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" },
3487 { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" },
3488 { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" },
3489 { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" },
3490
3491 { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" },
3492 { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" },
3493 { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" },
3494 { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" },
3495 { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" },
3496 { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" },
3497 { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" },
3498 { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" },
3499
3500 { "AIF2TX", NULL, "I2S2" },
3501 { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" },
3502
3503 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3504 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3505 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3506 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3507 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3508 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
3509 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
3510 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3511
3512 { "AIF3TX", NULL, "I2S3" },
3513 { "AIF3TX", NULL, "IF3 ADC Mux" },
3514
3515 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3516 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3517 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3518 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3519 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3520 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
3521 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
3522 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3523
3524 { "AIF4TX", NULL, "I2S4" },
3525 { "AIF4TX", NULL, "IF4 ADC Mux" },
3526
3527 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3528 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3529 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3530
3531 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3532 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3533
3534 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3535 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3536 { "SLB ADC3 Mux", "OB45", "OB45" },
3537
3538 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3539 { "SLB ADC4 Mux", "OB67", "OB67" },
3540 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3541
3542 { "SLBTX", NULL, "SLB" },
3543 { "SLBTX", NULL, "SLB ADC1 Mux" },
3544 { "SLBTX", NULL, "SLB ADC2 Mux" },
3545 { "SLBTX", NULL, "SLB ADC3 Mux" },
3546 { "SLBTX", NULL, "SLB ADC4 Mux" },
3547
3548 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
3549 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
3550 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
3551 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3552 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
3553
3554 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
3555 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
3556
3557 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
3558 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
3559 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
3560 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3561 { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
3562 { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
3563
3564 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
3565 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
3566
3567 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
3568 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
3569 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
3570 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3571 { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
3572
3573 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
3574 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
3575
3576 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3577 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
3578 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
3579 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3580 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
3581 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3582 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3583 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3584
3585 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3586 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
3587 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
3588 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3589 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
3590 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3591 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3592 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3593
3594 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3595 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3596 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3597 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3598 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3599 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
3600
3601 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3602 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3603 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3604 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3605 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3606 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
3607 { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
3608
3609 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3610 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3611 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3612 { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
3613 { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
3614 { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
3615 { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
3616
3617 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3618 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3619 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3620 { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
3621 { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
3622 { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
3623 { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
3624
3625 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3626 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3627 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3628 { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
3629 { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
3630 { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
3631 { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
3632
3633 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3634 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3635 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3636 { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
3637 { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
3638 { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
3639 { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
3640
3641 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3642 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3643 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3644 { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
3645 { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
3646 { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
3647 { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
3648
3649 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3650 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3651 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3652 { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
3653 { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
3654 { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
3655 { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
3656
3657 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
3658 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
3659 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
3660 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
3661
3662 { "OutBound2", NULL, "OB23 Bypass Mux" },
3663 { "OutBound3", NULL, "OB23 Bypass Mux" },
3664 { "OutBound4", NULL, "OB4 MIX" },
3665 { "OutBound5", NULL, "OB5 MIX" },
3666 { "OutBound6", NULL, "OB6 MIX" },
3667 { "OutBound7", NULL, "OB7 MIX" },
3668
3669 { "OB45", NULL, "OutBound4" },
3670 { "OB45", NULL, "OutBound5" },
3671 { "OB67", NULL, "OutBound6" },
3672 { "OB67", NULL, "OutBound7" },
3673
3674 { "IF1 DAC0", NULL, "AIF1RX" },
3675 { "IF1 DAC1", NULL, "AIF1RX" },
3676 { "IF1 DAC2", NULL, "AIF1RX" },
3677 { "IF1 DAC3", NULL, "AIF1RX" },
3678 { "IF1 DAC4", NULL, "AIF1RX" },
3679 { "IF1 DAC5", NULL, "AIF1RX" },
3680 { "IF1 DAC6", NULL, "AIF1RX" },
3681 { "IF1 DAC7", NULL, "AIF1RX" },
3682 { "IF1 DAC0", NULL, "I2S1" },
3683 { "IF1 DAC1", NULL, "I2S1" },
3684 { "IF1 DAC2", NULL, "I2S1" },
3685 { "IF1 DAC3", NULL, "I2S1" },
3686 { "IF1 DAC4", NULL, "I2S1" },
3687 { "IF1 DAC5", NULL, "I2S1" },
3688 { "IF1 DAC6", NULL, "I2S1" },
3689 { "IF1 DAC7", NULL, "I2S1" },
3690
3691 { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" },
3692 { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" },
3693 { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" },
3694 { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" },
3695 { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" },
3696 { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" },
3697 { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" },
3698 { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" },
3699
3700 { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" },
3701 { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" },
3702 { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" },
3703 { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" },
3704 { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" },
3705 { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" },
3706 { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" },
3707 { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" },
3708
3709 { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" },
3710 { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" },
3711 { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" },
3712 { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" },
3713 { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" },
3714 { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" },
3715 { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" },
3716 { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" },
3717
3718 { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" },
3719 { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" },
3720 { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" },
3721 { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" },
3722 { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" },
3723 { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" },
3724 { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" },
3725 { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" },
3726
3727 { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" },
3728 { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" },
3729 { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" },
3730 { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" },
3731 { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" },
3732 { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" },
3733 { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" },
3734 { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" },
3735
3736 { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" },
3737 { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" },
3738 { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" },
3739 { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" },
3740 { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" },
3741 { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" },
3742 { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" },
3743 { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" },
3744
3745 { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" },
3746 { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" },
3747 { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" },
3748 { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" },
3749 { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" },
3750 { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" },
3751 { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" },
3752 { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" },
3753
3754 { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" },
3755 { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" },
3756 { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" },
3757 { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" },
3758 { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" },
3759 { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" },
3760 { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" },
3761 { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" },
3762
3763 { "IF1 DAC01", NULL, "IF1 DAC0 Mux" },
3764 { "IF1 DAC01", NULL, "IF1 DAC1 Mux" },
3765 { "IF1 DAC23", NULL, "IF1 DAC2 Mux" },
3766 { "IF1 DAC23", NULL, "IF1 DAC3 Mux" },
3767 { "IF1 DAC45", NULL, "IF1 DAC4 Mux" },
3768 { "IF1 DAC45", NULL, "IF1 DAC5 Mux" },
3769 { "IF1 DAC67", NULL, "IF1 DAC6 Mux" },
3770 { "IF1 DAC67", NULL, "IF1 DAC7 Mux" },
3771
3772 { "IF2 DAC0", NULL, "AIF2RX" },
3773 { "IF2 DAC1", NULL, "AIF2RX" },
3774 { "IF2 DAC2", NULL, "AIF2RX" },
3775 { "IF2 DAC3", NULL, "AIF2RX" },
3776 { "IF2 DAC4", NULL, "AIF2RX" },
3777 { "IF2 DAC5", NULL, "AIF2RX" },
3778 { "IF2 DAC6", NULL, "AIF2RX" },
3779 { "IF2 DAC7", NULL, "AIF2RX" },
3780 { "IF2 DAC0", NULL, "I2S2" },
3781 { "IF2 DAC1", NULL, "I2S2" },
3782 { "IF2 DAC2", NULL, "I2S2" },
3783 { "IF2 DAC3", NULL, "I2S2" },
3784 { "IF2 DAC4", NULL, "I2S2" },
3785 { "IF2 DAC5", NULL, "I2S2" },
3786 { "IF2 DAC6", NULL, "I2S2" },
3787 { "IF2 DAC7", NULL, "I2S2" },
3788
3789 { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" },
3790 { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" },
3791 { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" },
3792 { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" },
3793 { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" },
3794 { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" },
3795 { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" },
3796 { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" },
3797
3798 { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" },
3799 { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" },
3800 { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" },
3801 { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" },
3802 { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" },
3803 { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" },
3804 { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" },
3805 { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" },
3806
3807 { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" },
3808 { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" },
3809 { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" },
3810 { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" },
3811 { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" },
3812 { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" },
3813 { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" },
3814 { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" },
3815
3816 { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" },
3817 { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" },
3818 { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" },
3819 { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" },
3820 { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" },
3821 { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" },
3822 { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" },
3823 { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" },
3824
3825 { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" },
3826 { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" },
3827 { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" },
3828 { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" },
3829 { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" },
3830 { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" },
3831 { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" },
3832 { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" },
3833
3834 { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" },
3835 { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" },
3836 { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" },
3837 { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" },
3838 { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" },
3839 { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" },
3840 { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" },
3841 { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" },
3842
3843 { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" },
3844 { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" },
3845 { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" },
3846 { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" },
3847 { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" },
3848 { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" },
3849 { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" },
3850 { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" },
3851
3852 { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" },
3853 { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" },
3854 { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" },
3855 { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" },
3856 { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" },
3857 { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" },
3858 { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" },
3859 { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" },
3860
3861 { "IF2 DAC01", NULL, "IF2 DAC0 Mux" },
3862 { "IF2 DAC01", NULL, "IF2 DAC1 Mux" },
3863 { "IF2 DAC23", NULL, "IF2 DAC2 Mux" },
3864 { "IF2 DAC23", NULL, "IF2 DAC3 Mux" },
3865 { "IF2 DAC45", NULL, "IF2 DAC4 Mux" },
3866 { "IF2 DAC45", NULL, "IF2 DAC5 Mux" },
3867 { "IF2 DAC67", NULL, "IF2 DAC6 Mux" },
3868 { "IF2 DAC67", NULL, "IF2 DAC7 Mux" },
3869
3870 { "IF3 DAC", NULL, "AIF3RX" },
3871 { "IF3 DAC", NULL, "I2S3" },
3872
3873 { "IF4 DAC", NULL, "AIF4RX" },
3874 { "IF4 DAC", NULL, "I2S4" },
3875
3876 { "IF3 DAC L", NULL, "IF3 DAC" },
3877 { "IF3 DAC R", NULL, "IF3 DAC" },
3878
3879 { "IF4 DAC L", NULL, "IF4 DAC" },
3880 { "IF4 DAC R", NULL, "IF4 DAC" },
3881
3882 { "SLB DAC0", NULL, "SLBRX" },
3883 { "SLB DAC1", NULL, "SLBRX" },
3884 { "SLB DAC2", NULL, "SLBRX" },
3885 { "SLB DAC3", NULL, "SLBRX" },
3886 { "SLB DAC4", NULL, "SLBRX" },
3887 { "SLB DAC5", NULL, "SLBRX" },
3888 { "SLB DAC6", NULL, "SLBRX" },
3889 { "SLB DAC7", NULL, "SLBRX" },
3890 { "SLB DAC0", NULL, "SLB" },
3891 { "SLB DAC1", NULL, "SLB" },
3892 { "SLB DAC2", NULL, "SLB" },
3893 { "SLB DAC3", NULL, "SLB" },
3894 { "SLB DAC4", NULL, "SLB" },
3895 { "SLB DAC5", NULL, "SLB" },
3896 { "SLB DAC6", NULL, "SLB" },
3897 { "SLB DAC7", NULL, "SLB" },
3898
3899 { "SLB DAC01", NULL, "SLB DAC0" },
3900 { "SLB DAC01", NULL, "SLB DAC1" },
3901 { "SLB DAC23", NULL, "SLB DAC2" },
3902 { "SLB DAC23", NULL, "SLB DAC3" },
3903 { "SLB DAC45", NULL, "SLB DAC4" },
3904 { "SLB DAC45", NULL, "SLB DAC5" },
3905 { "SLB DAC67", NULL, "SLB DAC6" },
3906 { "SLB DAC67", NULL, "SLB DAC7" },
3907
3908 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3909 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3910 { "ADDA1 Mux", "OB 67", "OB67" },
3911
3912 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
3913 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
3914 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
3915 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
3916 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
3917 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
3918
3919 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
3920 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
3921 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
3922 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
3923
3924 { "DAC1 FS", NULL, "DAC1 MIXL" },
3925 { "DAC1 FS", NULL, "DAC1 MIXR" },
3926
3927 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2 Mux" },
3928 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2 Mux" },
3929 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
3930 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
3931 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
3932 { "DAC2 L Mux", "OB 2", "OutBound2" },
3933
3934 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3 Mux" },
3935 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3 Mux" },
3936 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
3937 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
3938 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
3939 { "DAC2 R Mux", "OB 3", "OutBound3" },
3940 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
3941 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
3942
3943 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4 Mux" },
3944 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4 Mux" },
3945 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
3946 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
3947 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
3948 { "DAC3 L Mux", "OB 4", "OutBound4" },
3949
3950 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC5 Mux" },
3951 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC5 Mux" },
3952 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
3953 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
3954 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
3955 { "DAC3 R Mux", "OB 5", "OutBound5" },
3956
3957 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3958 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
3959 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
3960 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
3961 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
3962 { "DAC4 L Mux", "OB 6", "OutBound6" },
3963
3964 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3965 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
3966 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
3967 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
3968 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
3969 { "DAC4 R Mux", "OB 7", "OutBound7" },
3970
3971 { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
3972 { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
3973 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
3974 { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
3975 { "Sidetone Mux", "ADC1", "ADC 1" },
3976 { "Sidetone Mux", "ADC2", "ADC 2" },
3977 { "Sidetone Mux", NULL, "Sidetone Power" },
3978
3979 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
3980 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3981 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3982 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
3983 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
3984 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
3985 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3986 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3987 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
3988 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
3989 { "dac stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3990
3991 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
3992 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3993 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3994 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
3995 { "Mono DAC MIXL", NULL, "dac mono2 left filter" },
3996 { "dac mono2 left filter", NULL, "PLL1", is_sys_clk_from_pll },
3997 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
3998 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3999 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
4000 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
4001 { "Mono DAC MIXR", NULL, "dac mono2 right filter" },
4002 { "dac mono2 right filter", NULL, "PLL1", is_sys_clk_from_pll },
4003
4004 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
4005 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
4006 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
4007 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
4008 { "DD1 MIXL", NULL, "dac mono3 left filter" },
4009 { "dac mono3 left filter", NULL, "PLL1", is_sys_clk_from_pll },
4010 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
4011 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
4012 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
4013 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
4014 { "DD1 MIXR", NULL, "dac mono3 right filter" },
4015 { "dac mono3 right filter", NULL, "PLL1", is_sys_clk_from_pll },
4016
4017 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
4018 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
4019 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
4020 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
4021 { "DD2 MIXL", NULL, "dac mono4 left filter" },
4022 { "dac mono4 left filter", NULL, "PLL1", is_sys_clk_from_pll },
4023 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
4024 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
4025 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
4026 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
4027 { "DD2 MIXR", NULL, "dac mono4 right filter" },
4028 { "dac mono4 right filter", NULL, "PLL1", is_sys_clk_from_pll },
4029
4030 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
4031 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
4032 { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
4033 { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
4034 { "DD1 MIX", NULL, "DD1 MIXL" },
4035 { "DD1 MIX", NULL, "DD1 MIXR" },
4036 { "DD2 MIX", NULL, "DD2 MIXL" },
4037 { "DD2 MIX", NULL, "DD2 MIXR" },
4038
4039 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
4040 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
4041 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
4042 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
4043
4044 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
4045 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
4046 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
4047 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
4048
4049 { "DAC 1", NULL, "DAC12 SRC Mux" },
4050 { "DAC 2", NULL, "DAC12 SRC Mux" },
4051 { "DAC 3", NULL, "DAC3 SRC Mux" },
4052
4053 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
4054 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
4055 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
4056 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
4057 { "PDM1 L Mux", NULL, "PDM1 Power" },
4058 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
4059 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
4060 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
4061 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
4062 { "PDM1 R Mux", NULL, "PDM1 Power" },
4063 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
4064 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
4065 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
4066 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
4067 { "PDM2 L Mux", NULL, "PDM2 Power" },
4068 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
4069 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
4070 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
4071 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
4072 { "PDM2 R Mux", NULL, "PDM2 Power" },
4073
4074 { "LOUT1 amp", NULL, "DAC 1" },
4075 { "LOUT2 amp", NULL, "DAC 2" },
4076 { "LOUT3 amp", NULL, "DAC 3" },
4077
4078 { "LOUT1 vref", NULL, "LOUT1 amp" },
4079 { "LOUT2 vref", NULL, "LOUT2 amp" },
4080 { "LOUT3 vref", NULL, "LOUT3 amp" },
4081
4082 { "LOUT1", NULL, "LOUT1 vref" },
4083 { "LOUT2", NULL, "LOUT2 vref" },
4084 { "LOUT3", NULL, "LOUT3 vref" },
4085
4086 { "PDM1L", NULL, "PDM1 L Mux" },
4087 { "PDM1R", NULL, "PDM1 R Mux" },
4088 { "PDM2L", NULL, "PDM2 L Mux" },
4089 { "PDM2R", NULL, "PDM2 R Mux" },
4090 };
4091
4092 static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
4093 { "DMIC L2", NULL, "DMIC1 power" },
4094 { "DMIC R2", NULL, "DMIC1 power" },
4095 };
4096
4097 static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
4098 { "DMIC L2", NULL, "DMIC2 power" },
4099 { "DMIC R2", NULL, "DMIC2 power" },
4100 };
4101
4102 static int rt5677_hw_params(struct snd_pcm_substream *substream,
4103 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
4104 {
4105 struct snd_soc_component *component = dai->component;
4106 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4107 unsigned int val_len = 0, val_clk, mask_clk;
4108 int pre_div, bclk_ms, frame_size;
4109
4110 rt5677->lrck[dai->id] = params_rate(params);
4111 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
4112 if (pre_div < 0) {
4113 dev_err(component->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n",
4114 rt5677->sysclk, rt5677->lrck[dai->id]);
4115 return -EINVAL;
4116 }
4117 frame_size = snd_soc_params_to_frame_size(params);
4118 if (frame_size < 0) {
4119 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
4120 return -EINVAL;
4121 }
4122 bclk_ms = frame_size > 32;
4123 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
4124
4125 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
4126 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
4127 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
4128 bclk_ms, pre_div, dai->id);
4129
4130 switch (params_width(params)) {
4131 case 16:
4132 break;
4133 case 20:
4134 val_len |= RT5677_I2S_DL_20;
4135 break;
4136 case 24:
4137 val_len |= RT5677_I2S_DL_24;
4138 break;
4139 case 8:
4140 val_len |= RT5677_I2S_DL_8;
4141 break;
4142 default:
4143 return -EINVAL;
4144 }
4145
4146 switch (dai->id) {
4147 case RT5677_AIF1:
4148 mask_clk = RT5677_I2S_PD1_MASK;
4149 val_clk = pre_div << RT5677_I2S_PD1_SFT;
4150 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4151 RT5677_I2S_DL_MASK, val_len);
4152 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4153 mask_clk, val_clk);
4154 break;
4155 case RT5677_AIF2:
4156 mask_clk = RT5677_I2S_PD2_MASK;
4157 val_clk = pre_div << RT5677_I2S_PD2_SFT;
4158 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4159 RT5677_I2S_DL_MASK, val_len);
4160 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4161 mask_clk, val_clk);
4162 break;
4163 case RT5677_AIF3:
4164 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
4165 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
4166 pre_div << RT5677_I2S_PD3_SFT;
4167 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4168 RT5677_I2S_DL_MASK, val_len);
4169 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4170 mask_clk, val_clk);
4171 break;
4172 case RT5677_AIF4:
4173 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
4174 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
4175 pre_div << RT5677_I2S_PD4_SFT;
4176 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4177 RT5677_I2S_DL_MASK, val_len);
4178 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4179 mask_clk, val_clk);
4180 break;
4181 default:
4182 break;
4183 }
4184
4185 return 0;
4186 }
4187
4188 static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
4189 {
4190 struct snd_soc_component *component = dai->component;
4191 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4192 unsigned int reg_val = 0;
4193
4194 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4195 case SND_SOC_DAIFMT_CBM_CFM:
4196 rt5677->master[dai->id] = 1;
4197 break;
4198 case SND_SOC_DAIFMT_CBS_CFS:
4199 reg_val |= RT5677_I2S_MS_S;
4200 rt5677->master[dai->id] = 0;
4201 break;
4202 default:
4203 return -EINVAL;
4204 }
4205
4206 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
4207 case SND_SOC_DAIFMT_NB_NF:
4208 break;
4209 case SND_SOC_DAIFMT_IB_NF:
4210 reg_val |= RT5677_I2S_BP_INV;
4211 break;
4212 default:
4213 return -EINVAL;
4214 }
4215
4216 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
4217 case SND_SOC_DAIFMT_I2S:
4218 break;
4219 case SND_SOC_DAIFMT_LEFT_J:
4220 reg_val |= RT5677_I2S_DF_LEFT;
4221 break;
4222 case SND_SOC_DAIFMT_DSP_A:
4223 reg_val |= RT5677_I2S_DF_PCM_A;
4224 break;
4225 case SND_SOC_DAIFMT_DSP_B:
4226 reg_val |= RT5677_I2S_DF_PCM_B;
4227 break;
4228 default:
4229 return -EINVAL;
4230 }
4231
4232 switch (dai->id) {
4233 case RT5677_AIF1:
4234 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4235 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4236 RT5677_I2S_DF_MASK, reg_val);
4237 break;
4238 case RT5677_AIF2:
4239 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4240 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4241 RT5677_I2S_DF_MASK, reg_val);
4242 break;
4243 case RT5677_AIF3:
4244 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4245 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4246 RT5677_I2S_DF_MASK, reg_val);
4247 break;
4248 case RT5677_AIF4:
4249 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4250 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4251 RT5677_I2S_DF_MASK, reg_val);
4252 break;
4253 default:
4254 break;
4255 }
4256
4257
4258 return 0;
4259 }
4260
4261 static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
4262 int clk_id, unsigned int freq, int dir)
4263 {
4264 struct snd_soc_component *component = dai->component;
4265 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4266 unsigned int reg_val = 0;
4267
4268 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
4269 return 0;
4270
4271 switch (clk_id) {
4272 case RT5677_SCLK_S_MCLK:
4273 reg_val |= RT5677_SCLK_SRC_MCLK;
4274 break;
4275 case RT5677_SCLK_S_PLL1:
4276 reg_val |= RT5677_SCLK_SRC_PLL1;
4277 break;
4278 case RT5677_SCLK_S_RCCLK:
4279 reg_val |= RT5677_SCLK_SRC_RCCLK;
4280 break;
4281 default:
4282 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
4283 return -EINVAL;
4284 }
4285 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4286 RT5677_SCLK_SRC_MASK, reg_val);
4287 rt5677->sysclk = freq;
4288 rt5677->sysclk_src = clk_id;
4289
4290 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
4291
4292 return 0;
4293 }
4294
4295
4296
4297
4298
4299
4300
4301
4302
4303
4304
4305 static int rt5677_pll_calc(const unsigned int freq_in,
4306 const unsigned int freq_out, struct rl6231_pll_code *pll_code)
4307 {
4308 if (RT5677_PLL_INP_MIN > freq_in)
4309 return -EINVAL;
4310
4311 return rl6231_pll_calc(freq_in, freq_out, pll_code);
4312 }
4313
4314 static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
4315 unsigned int freq_in, unsigned int freq_out)
4316 {
4317 struct snd_soc_component *component = dai->component;
4318 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4319 struct rl6231_pll_code pll_code;
4320 int ret;
4321
4322 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
4323 freq_out == rt5677->pll_out)
4324 return 0;
4325
4326 if (!freq_in || !freq_out) {
4327 dev_dbg(component->dev, "PLL disabled\n");
4328
4329 rt5677->pll_in = 0;
4330 rt5677->pll_out = 0;
4331 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4332 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
4333 return 0;
4334 }
4335
4336 switch (source) {
4337 case RT5677_PLL1_S_MCLK:
4338 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4339 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
4340 break;
4341 case RT5677_PLL1_S_BCLK1:
4342 case RT5677_PLL1_S_BCLK2:
4343 case RT5677_PLL1_S_BCLK3:
4344 case RT5677_PLL1_S_BCLK4:
4345 switch (dai->id) {
4346 case RT5677_AIF1:
4347 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4348 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
4349 break;
4350 case RT5677_AIF2:
4351 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4352 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
4353 break;
4354 case RT5677_AIF3:
4355 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4356 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
4357 break;
4358 case RT5677_AIF4:
4359 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4360 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
4361 break;
4362 default:
4363 break;
4364 }
4365 break;
4366 default:
4367 dev_err(component->dev, "Unknown PLL source %d\n", source);
4368 return -EINVAL;
4369 }
4370
4371 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
4372 if (ret < 0) {
4373 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
4374 return ret;
4375 }
4376
4377 dev_dbg(component->dev, "m_bypass=%d m=%d n=%d k=%d\n",
4378 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4379 pll_code.n_code, pll_code.k_code);
4380
4381 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
4382 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
4383 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
4384 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
4385 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
4386
4387 rt5677->pll_in = freq_in;
4388 rt5677->pll_out = freq_out;
4389 rt5677->pll_src = source;
4390
4391 return 0;
4392 }
4393
4394 static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
4395 unsigned int rx_mask, int slots, int slot_width)
4396 {
4397 struct snd_soc_component *component = dai->component;
4398 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4399 unsigned int val = 0, slot_width_25 = 0;
4400
4401 if (rx_mask || tx_mask)
4402 val |= (1 << 12);
4403
4404 switch (slots) {
4405 case 4:
4406 val |= (1 << 10);
4407 break;
4408 case 6:
4409 val |= (2 << 10);
4410 break;
4411 case 8:
4412 val |= (3 << 10);
4413 break;
4414 case 2:
4415 default:
4416 break;
4417 }
4418
4419 switch (slot_width) {
4420 case 20:
4421 val |= (1 << 8);
4422 break;
4423 case 25:
4424 slot_width_25 = 0x8080;
4425
4426 case 24:
4427 val |= (2 << 8);
4428 break;
4429 case 32:
4430 val |= (3 << 8);
4431 break;
4432 case 16:
4433 default:
4434 break;
4435 }
4436
4437 switch (dai->id) {
4438 case RT5677_AIF1:
4439 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00,
4440 val);
4441 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000,
4442 slot_width_25);
4443 break;
4444 case RT5677_AIF2:
4445 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00,
4446 val);
4447 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80,
4448 slot_width_25);
4449 break;
4450 default:
4451 break;
4452 }
4453
4454 return 0;
4455 }
4456
4457 static int rt5677_set_bias_level(struct snd_soc_component *component,
4458 enum snd_soc_bias_level level)
4459 {
4460 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4461
4462 switch (level) {
4463 case SND_SOC_BIAS_ON:
4464 break;
4465
4466 case SND_SOC_BIAS_PREPARE:
4467 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) {
4468 rt5677_set_dsp_vad(component, false);
4469
4470 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4471 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
4472 5 << RT5677_LDO1_SEL_SFT |
4473 5 << RT5677_LDO2_SEL_SFT);
4474 regmap_update_bits(rt5677->regmap,
4475 RT5677_PR_BASE + RT5677_BIAS_CUR4,
4476 0x0f00, 0x0f00);
4477 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4478 RT5677_PWR_FV1 | RT5677_PWR_FV2 |
4479 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4480 RT5677_PWR_BG | RT5677_PWR_VREF2,
4481 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4482 RT5677_PWR_BG | RT5677_PWR_VREF2);
4483 rt5677->is_vref_slow = false;
4484 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4485 RT5677_PWR_CORE, RT5677_PWR_CORE);
4486 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4487 0x1, 0x1);
4488 }
4489 break;
4490
4491 case SND_SOC_BIAS_STANDBY:
4492 break;
4493
4494 case SND_SOC_BIAS_OFF:
4495 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
4496 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
4497 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1,
4498 2 << RT5677_LDO1_SEL_SFT |
4499 2 << RT5677_LDO2_SEL_SFT);
4500 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4501 RT5677_PWR_CORE, 0);
4502 regmap_update_bits(rt5677->regmap,
4503 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
4504
4505 if (rt5677->dsp_vad_en)
4506 rt5677_set_dsp_vad(component, true);
4507 break;
4508
4509 default:
4510 break;
4511 }
4512
4513 return 0;
4514 }
4515
4516 #ifdef CONFIG_GPIOLIB
4517 static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
4518 {
4519 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4520
4521 switch (offset) {
4522 case RT5677_GPIO1 ... RT5677_GPIO5:
4523 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4524 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1));
4525 break;
4526
4527 case RT5677_GPIO6:
4528 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4529 RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT);
4530 break;
4531
4532 default:
4533 break;
4534 }
4535 }
4536
4537 static int rt5677_gpio_direction_out(struct gpio_chip *chip,
4538 unsigned offset, int value)
4539 {
4540 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4541
4542 switch (offset) {
4543 case RT5677_GPIO1 ... RT5677_GPIO5:
4544 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4545 0x3 << (offset * 3 + 1),
4546 (0x2 | !!value) << (offset * 3 + 1));
4547 break;
4548
4549 case RT5677_GPIO6:
4550 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4551 RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK,
4552 RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT);
4553 break;
4554
4555 default:
4556 break;
4557 }
4558
4559 return 0;
4560 }
4561
4562 static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
4563 {
4564 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4565 int value, ret;
4566
4567 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
4568 if (ret < 0)
4569 return ret;
4570
4571 return (value & (0x1 << offset)) >> offset;
4572 }
4573
4574 static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
4575 {
4576 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4577
4578 switch (offset) {
4579 case RT5677_GPIO1 ... RT5677_GPIO5:
4580 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4581 0x1 << (offset * 3 + 2), 0x0);
4582 break;
4583
4584 case RT5677_GPIO6:
4585 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4586 RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN);
4587 break;
4588
4589 default:
4590 break;
4591 }
4592
4593 return 0;
4594 }
4595
4596
4597
4598
4599
4600
4601 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4602 int value)
4603 {
4604 int shift;
4605
4606 switch (offset) {
4607 case RT5677_GPIO1 ... RT5677_GPIO2:
4608 shift = 2 * (1 - offset);
4609 regmap_update_bits(rt5677->regmap,
4610 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2,
4611 0x3 << shift,
4612 (value & 0x3) << shift);
4613 break;
4614
4615 case RT5677_GPIO3 ... RT5677_GPIO6:
4616 shift = 2 * (9 - offset);
4617 regmap_update_bits(rt5677->regmap,
4618 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3,
4619 0x3 << shift,
4620 (value & 0x3) << shift);
4621 break;
4622
4623 default:
4624 break;
4625 }
4626 }
4627
4628 static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset)
4629 {
4630 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4631 int irq;
4632
4633 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
4634 (rt5677->pdata.jd1_gpio == 2 &&
4635 offset == RT5677_GPIO2) ||
4636 (rt5677->pdata.jd1_gpio == 3 &&
4637 offset == RT5677_GPIO3)) {
4638 irq = RT5677_IRQ_JD1;
4639 } else if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
4640 (rt5677->pdata.jd2_gpio == 2 &&
4641 offset == RT5677_GPIO5) ||
4642 (rt5677->pdata.jd2_gpio == 3 &&
4643 offset == RT5677_GPIO6)) {
4644 irq = RT5677_IRQ_JD2;
4645 } else if ((rt5677->pdata.jd3_gpio == 1 &&
4646 offset == RT5677_GPIO4) ||
4647 (rt5677->pdata.jd3_gpio == 2 &&
4648 offset == RT5677_GPIO5) ||
4649 (rt5677->pdata.jd3_gpio == 3 &&
4650 offset == RT5677_GPIO6)) {
4651 irq = RT5677_IRQ_JD3;
4652 } else {
4653 return -ENXIO;
4654 }
4655
4656 return irq_create_mapping(rt5677->domain, irq);
4657 }
4658
4659 static const struct gpio_chip rt5677_template_chip = {
4660 .label = RT5677_DRV_NAME,
4661 .owner = THIS_MODULE,
4662 .direction_output = rt5677_gpio_direction_out,
4663 .set = rt5677_gpio_set,
4664 .direction_input = rt5677_gpio_direction_in,
4665 .get = rt5677_gpio_get,
4666 .to_irq = rt5677_to_irq,
4667 .can_sleep = 1,
4668 };
4669
4670 static void rt5677_init_gpio(struct i2c_client *i2c)
4671 {
4672 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4673 int ret;
4674
4675 rt5677->gpio_chip = rt5677_template_chip;
4676 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
4677 rt5677->gpio_chip.parent = &i2c->dev;
4678 rt5677->gpio_chip.base = -1;
4679
4680 ret = gpiochip_add_data(&rt5677->gpio_chip, rt5677);
4681 if (ret != 0)
4682 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
4683 }
4684
4685 static void rt5677_free_gpio(struct i2c_client *i2c)
4686 {
4687 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4688
4689 gpiochip_remove(&rt5677->gpio_chip);
4690 }
4691 #else
4692 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4693 int value)
4694 {
4695 }
4696
4697 static void rt5677_init_gpio(struct i2c_client *i2c)
4698 {
4699 }
4700
4701 static void rt5677_free_gpio(struct i2c_client *i2c)
4702 {
4703 }
4704 #endif
4705
4706 static int rt5677_probe(struct snd_soc_component *component)
4707 {
4708 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
4709 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4710 int i;
4711
4712 rt5677->component = component;
4713
4714 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4715 snd_soc_dapm_add_routes(dapm,
4716 rt5677_dmic2_clk_2,
4717 ARRAY_SIZE(rt5677_dmic2_clk_2));
4718 } else {
4719 snd_soc_dapm_add_routes(dapm,
4720 rt5677_dmic2_clk_1,
4721 ARRAY_SIZE(rt5677_dmic2_clk_1));
4722 }
4723
4724 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
4725
4726 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4727 ~RT5677_IRQ_DEBOUNCE_SEL_MASK, 0x0020);
4728 regmap_write(rt5677->regmap, RT5677_PWR_DSP2,
4729 RT5677_PWR_SLIM_ISO | RT5677_PWR_CORE_ISO);
4730
4731 for (i = 0; i < RT5677_GPIO_NUM; i++)
4732 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
4733
4734 mutex_init(&rt5677->dsp_cmd_lock);
4735 mutex_init(&rt5677->dsp_pri_lock);
4736
4737 return 0;
4738 }
4739
4740 static void rt5677_remove(struct snd_soc_component *component)
4741 {
4742 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4743
4744 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
4745 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
4746 gpiod_set_value_cansleep(rt5677->reset_pin, 1);
4747 }
4748
4749 #ifdef CONFIG_PM
4750 static int rt5677_suspend(struct snd_soc_component *component)
4751 {
4752 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4753
4754 if (!rt5677->dsp_vad_en) {
4755 regcache_cache_only(rt5677->regmap, true);
4756 regcache_mark_dirty(rt5677->regmap);
4757
4758 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
4759 gpiod_set_value_cansleep(rt5677->reset_pin, 1);
4760 }
4761
4762 return 0;
4763 }
4764
4765 static int rt5677_resume(struct snd_soc_component *component)
4766 {
4767 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
4768
4769 if (!rt5677->dsp_vad_en) {
4770 rt5677->pll_src = 0;
4771 rt5677->pll_in = 0;
4772 rt5677->pll_out = 0;
4773 gpiod_set_value_cansleep(rt5677->pow_ldo2, 1);
4774 gpiod_set_value_cansleep(rt5677->reset_pin, 0);
4775 if (rt5677->pow_ldo2 || rt5677->reset_pin)
4776 msleep(10);
4777
4778 regcache_cache_only(rt5677->regmap, false);
4779 regcache_sync(rt5677->regmap);
4780 }
4781
4782 return 0;
4783 }
4784 #else
4785 #define rt5677_suspend NULL
4786 #define rt5677_resume NULL
4787 #endif
4788
4789 static int rt5677_read(void *context, unsigned int reg, unsigned int *val)
4790 {
4791 struct i2c_client *client = context;
4792 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4793
4794 if (rt5677->is_dsp_mode) {
4795 if (reg > 0xff) {
4796 mutex_lock(&rt5677->dsp_pri_lock);
4797 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4798 reg & 0xff);
4799 rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val);
4800 mutex_unlock(&rt5677->dsp_pri_lock);
4801 } else {
4802 rt5677_dsp_mode_i2c_read(rt5677, reg, val);
4803 }
4804 } else {
4805 regmap_read(rt5677->regmap_physical, reg, val);
4806 }
4807
4808 return 0;
4809 }
4810
4811 static int rt5677_write(void *context, unsigned int reg, unsigned int val)
4812 {
4813 struct i2c_client *client = context;
4814 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4815
4816 if (rt5677->is_dsp_mode) {
4817 if (reg > 0xff) {
4818 mutex_lock(&rt5677->dsp_pri_lock);
4819 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4820 reg & 0xff);
4821 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA,
4822 val);
4823 mutex_unlock(&rt5677->dsp_pri_lock);
4824 } else {
4825 rt5677_dsp_mode_i2c_write(rt5677, reg, val);
4826 }
4827 } else {
4828 regmap_write(rt5677->regmap_physical, reg, val);
4829 }
4830
4831 return 0;
4832 }
4833
4834 #define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
4835 #define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4836 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4837
4838 static const struct snd_soc_dai_ops rt5677_aif_dai_ops = {
4839 .hw_params = rt5677_hw_params,
4840 .set_fmt = rt5677_set_dai_fmt,
4841 .set_sysclk = rt5677_set_dai_sysclk,
4842 .set_pll = rt5677_set_dai_pll,
4843 .set_tdm_slot = rt5677_set_tdm_slot,
4844 };
4845
4846 static struct snd_soc_dai_driver rt5677_dai[] = {
4847 {
4848 .name = "rt5677-aif1",
4849 .id = RT5677_AIF1,
4850 .playback = {
4851 .stream_name = "AIF1 Playback",
4852 .channels_min = 1,
4853 .channels_max = 2,
4854 .rates = RT5677_STEREO_RATES,
4855 .formats = RT5677_FORMATS,
4856 },
4857 .capture = {
4858 .stream_name = "AIF1 Capture",
4859 .channels_min = 1,
4860 .channels_max = 2,
4861 .rates = RT5677_STEREO_RATES,
4862 .formats = RT5677_FORMATS,
4863 },
4864 .ops = &rt5677_aif_dai_ops,
4865 },
4866 {
4867 .name = "rt5677-aif2",
4868 .id = RT5677_AIF2,
4869 .playback = {
4870 .stream_name = "AIF2 Playback",
4871 .channels_min = 1,
4872 .channels_max = 2,
4873 .rates = RT5677_STEREO_RATES,
4874 .formats = RT5677_FORMATS,
4875 },
4876 .capture = {
4877 .stream_name = "AIF2 Capture",
4878 .channels_min = 1,
4879 .channels_max = 2,
4880 .rates = RT5677_STEREO_RATES,
4881 .formats = RT5677_FORMATS,
4882 },
4883 .ops = &rt5677_aif_dai_ops,
4884 },
4885 {
4886 .name = "rt5677-aif3",
4887 .id = RT5677_AIF3,
4888 .playback = {
4889 .stream_name = "AIF3 Playback",
4890 .channels_min = 1,
4891 .channels_max = 2,
4892 .rates = RT5677_STEREO_RATES,
4893 .formats = RT5677_FORMATS,
4894 },
4895 .capture = {
4896 .stream_name = "AIF3 Capture",
4897 .channels_min = 1,
4898 .channels_max = 2,
4899 .rates = RT5677_STEREO_RATES,
4900 .formats = RT5677_FORMATS,
4901 },
4902 .ops = &rt5677_aif_dai_ops,
4903 },
4904 {
4905 .name = "rt5677-aif4",
4906 .id = RT5677_AIF4,
4907 .playback = {
4908 .stream_name = "AIF4 Playback",
4909 .channels_min = 1,
4910 .channels_max = 2,
4911 .rates = RT5677_STEREO_RATES,
4912 .formats = RT5677_FORMATS,
4913 },
4914 .capture = {
4915 .stream_name = "AIF4 Capture",
4916 .channels_min = 1,
4917 .channels_max = 2,
4918 .rates = RT5677_STEREO_RATES,
4919 .formats = RT5677_FORMATS,
4920 },
4921 .ops = &rt5677_aif_dai_ops,
4922 },
4923 {
4924 .name = "rt5677-slimbus",
4925 .id = RT5677_AIF5,
4926 .playback = {
4927 .stream_name = "SLIMBus Playback",
4928 .channels_min = 1,
4929 .channels_max = 2,
4930 .rates = RT5677_STEREO_RATES,
4931 .formats = RT5677_FORMATS,
4932 },
4933 .capture = {
4934 .stream_name = "SLIMBus Capture",
4935 .channels_min = 1,
4936 .channels_max = 2,
4937 .rates = RT5677_STEREO_RATES,
4938 .formats = RT5677_FORMATS,
4939 },
4940 .ops = &rt5677_aif_dai_ops,
4941 },
4942 };
4943
4944 static const struct snd_soc_component_driver soc_component_dev_rt5677 = {
4945 .name = RT5677_DRV_NAME,
4946 .probe = rt5677_probe,
4947 .remove = rt5677_remove,
4948 .suspend = rt5677_suspend,
4949 .resume = rt5677_resume,
4950 .set_bias_level = rt5677_set_bias_level,
4951 .controls = rt5677_snd_controls,
4952 .num_controls = ARRAY_SIZE(rt5677_snd_controls),
4953 .dapm_widgets = rt5677_dapm_widgets,
4954 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
4955 .dapm_routes = rt5677_dapm_routes,
4956 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
4957 .use_pmdown_time = 1,
4958 .endianness = 1,
4959 .non_legacy_dai_naming = 1,
4960 };
4961
4962 static const struct regmap_config rt5677_regmap_physical = {
4963 .name = "physical",
4964 .reg_bits = 8,
4965 .val_bits = 16,
4966
4967 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4968 RT5677_PR_SPACING),
4969 .readable_reg = rt5677_readable_register,
4970
4971 .cache_type = REGCACHE_NONE,
4972 .ranges = rt5677_ranges,
4973 .num_ranges = ARRAY_SIZE(rt5677_ranges),
4974 };
4975
4976 static const struct regmap_config rt5677_regmap = {
4977 .reg_bits = 8,
4978 .val_bits = 16,
4979
4980 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4981 RT5677_PR_SPACING),
4982
4983 .volatile_reg = rt5677_volatile_register,
4984 .readable_reg = rt5677_readable_register,
4985 .reg_read = rt5677_read,
4986 .reg_write = rt5677_write,
4987
4988 .cache_type = REGCACHE_RBTREE,
4989 .reg_defaults = rt5677_reg,
4990 .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
4991 .ranges = rt5677_ranges,
4992 .num_ranges = ARRAY_SIZE(rt5677_ranges),
4993 };
4994
4995 static const struct of_device_id rt5677_of_match[] = {
4996 { .compatible = "realtek,rt5677", .data = (const void *)RT5677 },
4997 { }
4998 };
4999 MODULE_DEVICE_TABLE(of, rt5677_of_match);
5000
5001 static const struct acpi_device_id rt5677_acpi_match[] = {
5002 { "RT5677CE", RT5677 },
5003 { }
5004 };
5005 MODULE_DEVICE_TABLE(acpi, rt5677_acpi_match);
5006
5007 static void rt5677_read_device_properties(struct rt5677_priv *rt5677,
5008 struct device *dev)
5009 {
5010 u32 val;
5011
5012 rt5677->pdata.in1_diff =
5013 device_property_read_bool(dev, "IN1") ||
5014 device_property_read_bool(dev, "realtek,in1-differential");
5015
5016 rt5677->pdata.in2_diff =
5017 device_property_read_bool(dev, "IN2") ||
5018 device_property_read_bool(dev, "realtek,in2-differential");
5019
5020 rt5677->pdata.lout1_diff =
5021 device_property_read_bool(dev, "OUT1") ||
5022 device_property_read_bool(dev, "realtek,lout1-differential");
5023
5024 rt5677->pdata.lout2_diff =
5025 device_property_read_bool(dev, "OUT2") ||
5026 device_property_read_bool(dev, "realtek,lout2-differential");
5027
5028 rt5677->pdata.lout3_diff =
5029 device_property_read_bool(dev, "OUT3") ||
5030 device_property_read_bool(dev, "realtek,lout3-differential");
5031
5032 device_property_read_u8_array(dev, "realtek,gpio-config",
5033 rt5677->pdata.gpio_config,
5034 RT5677_GPIO_NUM);
5035
5036 if (!device_property_read_u32(dev, "DCLK", &val) ||
5037 !device_property_read_u32(dev, "realtek,dmic2_clk_pin", &val))
5038 rt5677->pdata.dmic2_clk_pin = val;
5039
5040 if (!device_property_read_u32(dev, "JD1", &val) ||
5041 !device_property_read_u32(dev, "realtek,jd1-gpio", &val))
5042 rt5677->pdata.jd1_gpio = val;
5043
5044 if (!device_property_read_u32(dev, "JD2", &val) ||
5045 !device_property_read_u32(dev, "realtek,jd2-gpio", &val))
5046 rt5677->pdata.jd2_gpio = val;
5047
5048 if (!device_property_read_u32(dev, "JD3", &val) ||
5049 !device_property_read_u32(dev, "realtek,jd3-gpio", &val))
5050 rt5677->pdata.jd3_gpio = val;
5051 }
5052
5053 struct rt5677_irq_desc {
5054 unsigned int enable_mask;
5055 unsigned int status_mask;
5056 unsigned int polarity_mask;
5057 };
5058
5059 static const struct rt5677_irq_desc rt5677_irq_descs[] = {
5060 [RT5677_IRQ_JD1] = {
5061 .enable_mask = RT5677_EN_IRQ_GPIO_JD1,
5062 .status_mask = RT5677_STA_GPIO_JD1,
5063 .polarity_mask = RT5677_INV_GPIO_JD1,
5064 },
5065 [RT5677_IRQ_JD2] = {
5066 .enable_mask = RT5677_EN_IRQ_GPIO_JD2,
5067 .status_mask = RT5677_STA_GPIO_JD2,
5068 .polarity_mask = RT5677_INV_GPIO_JD2,
5069 },
5070 [RT5677_IRQ_JD3] = {
5071 .enable_mask = RT5677_EN_IRQ_GPIO_JD3,
5072 .status_mask = RT5677_STA_GPIO_JD3,
5073 .polarity_mask = RT5677_INV_GPIO_JD3,
5074 },
5075 };
5076
5077 static irqreturn_t rt5677_irq(int unused, void *data)
5078 {
5079 struct rt5677_priv *rt5677 = data;
5080 int ret = 0, loop, i, reg_irq, virq;
5081 bool irq_fired = false;
5082
5083 mutex_lock(&rt5677->irq_lock);
5084
5085
5086
5087
5088
5089
5090
5091
5092
5093
5094
5095
5096
5097
5098
5099 for (loop = 0; loop < 20; loop++) {
5100
5101 ret = regmap_read(rt5677->regmap, RT5677_IRQ_CTRL1, ®_irq);
5102 if (ret) {
5103 dev_err(rt5677->dev, "failed reading IRQ status: %d\n",
5104 ret);
5105 goto exit;
5106 }
5107
5108 irq_fired = false;
5109 for (i = 0; i < RT5677_IRQ_NUM; i++) {
5110 if (reg_irq & rt5677_irq_descs[i].status_mask) {
5111 irq_fired = true;
5112 virq = irq_find_mapping(rt5677->domain, i);
5113 if (virq)
5114 handle_nested_irq(virq);
5115
5116
5117
5118
5119 reg_irq ^= rt5677_irq_descs[i].polarity_mask;
5120 }
5121 }
5122 if (!irq_fired)
5123 goto exit;
5124
5125 ret = regmap_write(rt5677->regmap, RT5677_IRQ_CTRL1, reg_irq);
5126 if (ret) {
5127 dev_err(rt5677->dev, "failed updating IRQ status: %d\n",
5128 ret);
5129 goto exit;
5130 }
5131 }
5132 exit:
5133 mutex_unlock(&rt5677->irq_lock);
5134 if (irq_fired)
5135 return IRQ_HANDLED;
5136 else
5137 return IRQ_NONE;
5138 }
5139
5140 static void rt5677_irq_bus_lock(struct irq_data *data)
5141 {
5142 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data);
5143
5144 mutex_lock(&rt5677->irq_lock);
5145 }
5146
5147 static void rt5677_irq_bus_sync_unlock(struct irq_data *data)
5148 {
5149 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data);
5150
5151
5152 regmap_update_bits(rt5677->regmap, RT5677_IRQ_CTRL1,
5153 RT5677_EN_IRQ_GPIO_JD1 | RT5677_EN_IRQ_GPIO_JD2 |
5154 RT5677_EN_IRQ_GPIO_JD3, rt5677->irq_en);
5155 mutex_unlock(&rt5677->irq_lock);
5156 }
5157
5158 static void rt5677_irq_enable(struct irq_data *data)
5159 {
5160 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data);
5161
5162 rt5677->irq_en |= rt5677_irq_descs[data->hwirq].enable_mask;
5163 }
5164
5165 static void rt5677_irq_disable(struct irq_data *data)
5166 {
5167 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data);
5168
5169 rt5677->irq_en &= ~rt5677_irq_descs[data->hwirq].enable_mask;
5170 }
5171
5172 static struct irq_chip rt5677_irq_chip = {
5173 .name = "rt5677_irq_chip",
5174 .irq_bus_lock = rt5677_irq_bus_lock,
5175 .irq_bus_sync_unlock = rt5677_irq_bus_sync_unlock,
5176 .irq_disable = rt5677_irq_disable,
5177 .irq_enable = rt5677_irq_enable,
5178 };
5179
5180 static int rt5677_irq_map(struct irq_domain *h, unsigned int virq,
5181 irq_hw_number_t hw)
5182 {
5183 struct rt5677_priv *rt5677 = h->host_data;
5184
5185 irq_set_chip_data(virq, rt5677);
5186 irq_set_chip(virq, &rt5677_irq_chip);
5187 irq_set_nested_thread(virq, 1);
5188 irq_set_noprobe(virq);
5189 return 0;
5190 }
5191
5192
5193 static const struct irq_domain_ops rt5677_domain_ops = {
5194 .map = rt5677_irq_map,
5195 .xlate = irq_domain_xlate_twocell,
5196 };
5197
5198 static int rt5677_init_irq(struct i2c_client *i2c)
5199 {
5200 int ret;
5201 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
5202 unsigned int jd_mask = 0, jd_val = 0;
5203
5204 if (!rt5677->pdata.jd1_gpio &&
5205 !rt5677->pdata.jd2_gpio &&
5206 !rt5677->pdata.jd3_gpio)
5207 return 0;
5208
5209 if (!i2c->irq) {
5210 dev_err(&i2c->dev, "No interrupt specified\n");
5211 return -EINVAL;
5212 }
5213
5214 mutex_init(&rt5677->irq_lock);
5215
5216
5217
5218
5219
5220
5221 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
5222 RT5677_IRQ_DEBOUNCE_SEL_MASK,
5223 RT5677_IRQ_DEBOUNCE_SEL_RC);
5224
5225 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL1, 0xff, 0xff);
5226
5227
5228 if (rt5677->pdata.jd1_gpio) {
5229 jd_mask |= RT5677_SEL_GPIO_JD1_MASK;
5230 jd_val |= rt5677->pdata.jd1_gpio << RT5677_SEL_GPIO_JD1_SFT;
5231 }
5232 if (rt5677->pdata.jd2_gpio) {
5233 jd_mask |= RT5677_SEL_GPIO_JD2_MASK;
5234 jd_val |= rt5677->pdata.jd2_gpio << RT5677_SEL_GPIO_JD2_SFT;
5235 }
5236 if (rt5677->pdata.jd3_gpio) {
5237 jd_mask |= RT5677_SEL_GPIO_JD3_MASK;
5238 jd_val |= rt5677->pdata.jd3_gpio << RT5677_SEL_GPIO_JD3_SFT;
5239 }
5240 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, jd_mask, jd_val);
5241
5242
5243 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1,
5244 RT5677_GPIO1_PIN_MASK, RT5677_GPIO1_PIN_IRQ);
5245
5246
5247 rt5677->domain = irq_domain_add_linear(i2c->dev.of_node,
5248 RT5677_IRQ_NUM, &rt5677_domain_ops, rt5677);
5249 if (!rt5677->domain) {
5250 dev_err(&i2c->dev, "Failed to create IRQ domain\n");
5251 return -ENOMEM;
5252 }
5253
5254 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, rt5677_irq,
5255 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
5256 "rt5677", rt5677);
5257 if (ret)
5258 dev_err(&i2c->dev, "Failed to request IRQ: %d\n", ret);
5259
5260 return ret;
5261 }
5262
5263 static int rt5677_i2c_probe(struct i2c_client *i2c)
5264 {
5265 struct rt5677_priv *rt5677;
5266 int ret;
5267 unsigned int val;
5268
5269 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
5270 GFP_KERNEL);
5271 if (rt5677 == NULL)
5272 return -ENOMEM;
5273
5274 rt5677->dev = &i2c->dev;
5275 i2c_set_clientdata(i2c, rt5677);
5276
5277 if (i2c->dev.of_node) {
5278 const struct of_device_id *match_id;
5279
5280 match_id = of_match_device(rt5677_of_match, &i2c->dev);
5281 if (match_id)
5282 rt5677->type = (enum rt5677_type)match_id->data;
5283 } else if (ACPI_HANDLE(&i2c->dev)) {
5284 const struct acpi_device_id *acpi_id;
5285
5286 acpi_id = acpi_match_device(rt5677_acpi_match, &i2c->dev);
5287 if (acpi_id)
5288 rt5677->type = (enum rt5677_type)acpi_id->driver_data;
5289 } else {
5290 return -EINVAL;
5291 }
5292
5293 rt5677_read_device_properties(rt5677, &i2c->dev);
5294
5295
5296
5297
5298
5299 rt5677->pow_ldo2 = devm_gpiod_get_optional(&i2c->dev,
5300 "realtek,pow-ldo2", GPIOD_OUT_HIGH);
5301 if (IS_ERR(rt5677->pow_ldo2)) {
5302 ret = PTR_ERR(rt5677->pow_ldo2);
5303 dev_err(&i2c->dev, "Failed to request POW_LDO2: %d\n", ret);
5304 return ret;
5305 }
5306 rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev,
5307 "realtek,reset", GPIOD_OUT_LOW);
5308 if (IS_ERR(rt5677->reset_pin)) {
5309 ret = PTR_ERR(rt5677->reset_pin);
5310 dev_err(&i2c->dev, "Failed to request RESET: %d\n", ret);
5311 return ret;
5312 }
5313
5314 if (rt5677->pow_ldo2 || rt5677->reset_pin) {
5315
5316
5317
5318
5319 msleep(10);
5320 }
5321
5322 rt5677->regmap_physical = devm_regmap_init_i2c(i2c,
5323 &rt5677_regmap_physical);
5324 if (IS_ERR(rt5677->regmap_physical)) {
5325 ret = PTR_ERR(rt5677->regmap_physical);
5326 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5327 ret);
5328 return ret;
5329 }
5330
5331 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap);
5332 if (IS_ERR(rt5677->regmap)) {
5333 ret = PTR_ERR(rt5677->regmap);
5334 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5335 ret);
5336 return ret;
5337 }
5338
5339 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
5340 if (val != RT5677_DEVICE_ID) {
5341 dev_err(&i2c->dev,
5342 "Device with ID register %#x is not rt5677\n", val);
5343 return -ENODEV;
5344 }
5345
5346 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
5347
5348 ret = regmap_register_patch(rt5677->regmap, init_list,
5349 ARRAY_SIZE(init_list));
5350 if (ret != 0)
5351 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
5352
5353 if (rt5677->pdata.in1_diff)
5354 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5355 RT5677_IN_DF1, RT5677_IN_DF1);
5356
5357 if (rt5677->pdata.in2_diff)
5358 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5359 RT5677_IN_DF2, RT5677_IN_DF2);
5360
5361 if (rt5677->pdata.lout1_diff)
5362 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5363 RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF);
5364
5365 if (rt5677->pdata.lout2_diff)
5366 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5367 RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF);
5368
5369 if (rt5677->pdata.lout3_diff)
5370 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5371 RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF);
5372
5373 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
5374 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
5375 RT5677_GPIO5_FUNC_MASK,
5376 RT5677_GPIO5_FUNC_DMIC);
5377 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
5378 RT5677_GPIO5_DIR_MASK,
5379 RT5677_GPIO5_DIR_OUT);
5380 }
5381
5382 if (rt5677->pdata.micbias1_vdd_3v3)
5383 regmap_update_bits(rt5677->regmap, RT5677_MICBIAS,
5384 RT5677_MICBIAS1_CTRL_VDD_MASK,
5385 RT5677_MICBIAS1_CTRL_VDD_3_3V);
5386
5387 rt5677_init_gpio(i2c);
5388 ret = rt5677_init_irq(i2c);
5389 if (ret)
5390 dev_err(&i2c->dev, "Failed to initialize irq: %d\n", ret);
5391
5392 return devm_snd_soc_register_component(&i2c->dev,
5393 &soc_component_dev_rt5677,
5394 rt5677_dai, ARRAY_SIZE(rt5677_dai));
5395 }
5396
5397 static int rt5677_i2c_remove(struct i2c_client *i2c)
5398 {
5399 rt5677_free_gpio(i2c);
5400
5401 return 0;
5402 }
5403
5404 static struct i2c_driver rt5677_i2c_driver = {
5405 .driver = {
5406 .name = RT5677_DRV_NAME,
5407 .of_match_table = rt5677_of_match,
5408 .acpi_match_table = ACPI_PTR(rt5677_acpi_match),
5409 },
5410 .probe_new = rt5677_i2c_probe,
5411 .remove = rt5677_i2c_remove,
5412 };
5413 module_i2c_driver(rt5677_i2c_driver);
5414
5415 MODULE_DESCRIPTION("ASoC RT5677 driver");
5416 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
5417 MODULE_LICENSE("GPL v2");