root/sound/soc/sof/intel/apl.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
   2 //
   3 // This file is provided under a dual BSD/GPLv2 license.  When using or
   4 // redistributing this file, you may do so under either license.
   5 //
   6 // Copyright(c) 2018 Intel Corporation. All rights reserved.
   7 //
   8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
   9 //          Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
  10 //          Rander Wang <rander.wang@intel.com>
  11 //          Keyon Jie <yang.jie@linux.intel.com>
  12 //
  13 
  14 /*
  15  * Hardware interface for audio DSP on Apollolake and GeminiLake
  16  */
  17 
  18 #include "../sof-priv.h"
  19 #include "hda.h"
  20 
  21 static const struct snd_sof_debugfs_map apl_dsp_debugfs[] = {
  22         {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
  23         {"pp", HDA_DSP_PP_BAR,  0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
  24         {"dsp", HDA_DSP_BAR,  0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
  25 };
  26 
  27 /* apollolake ops */
  28 const struct snd_sof_dsp_ops sof_apl_ops = {
  29         /* probe and remove */
  30         .probe          = hda_dsp_probe,
  31         .remove         = hda_dsp_remove,
  32 
  33         /* Register IO */
  34         .write          = sof_io_write,
  35         .read           = sof_io_read,
  36         .write64        = sof_io_write64,
  37         .read64         = sof_io_read64,
  38 
  39         /* Block IO */
  40         .block_read     = sof_block_read,
  41         .block_write    = sof_block_write,
  42 
  43         /* doorbell */
  44         .irq_handler    = hda_dsp_ipc_irq_handler,
  45         .irq_thread     = hda_dsp_ipc_irq_thread,
  46 
  47         /* ipc */
  48         .send_msg       = hda_dsp_ipc_send_msg,
  49         .fw_ready       = sof_fw_ready,
  50         .get_mailbox_offset = hda_dsp_ipc_get_mailbox_offset,
  51         .get_window_offset = hda_dsp_ipc_get_window_offset,
  52 
  53         .ipc_msg_data   = hda_ipc_msg_data,
  54         .ipc_pcm_params = hda_ipc_pcm_params,
  55 
  56         /* debug */
  57         .debug_map      = apl_dsp_debugfs,
  58         .debug_map_count        = ARRAY_SIZE(apl_dsp_debugfs),
  59         .dbg_dump       = hda_dsp_dump,
  60         .ipc_dump       = hda_ipc_dump,
  61 
  62         /* stream callbacks */
  63         .pcm_open       = hda_dsp_pcm_open,
  64         .pcm_close      = hda_dsp_pcm_close,
  65         .pcm_hw_params  = hda_dsp_pcm_hw_params,
  66         .pcm_hw_free    = hda_dsp_stream_hw_free,
  67         .pcm_trigger    = hda_dsp_pcm_trigger,
  68         .pcm_pointer    = hda_dsp_pcm_pointer,
  69 
  70         /* firmware loading */
  71         .load_firmware = snd_sof_load_firmware_raw,
  72 
  73         /* firmware run */
  74         .run = hda_dsp_cl_boot_firmware,
  75 
  76         /* pre/post fw run */
  77         .pre_fw_run = hda_dsp_pre_fw_run,
  78         .post_fw_run = hda_dsp_post_fw_run,
  79 
  80         /* dsp core power up/down */
  81         .core_power_up = hda_dsp_enable_core,
  82         .core_power_down = hda_dsp_core_reset_power_down,
  83 
  84         /* trace callback */
  85         .trace_init = hda_dsp_trace_init,
  86         .trace_release = hda_dsp_trace_release,
  87         .trace_trigger = hda_dsp_trace_trigger,
  88 
  89         /* DAI drivers */
  90         .drv            = skl_dai,
  91         .num_drv        = SOF_SKL_NUM_DAIS,
  92 
  93         /* PM */
  94         .suspend                = hda_dsp_suspend,
  95         .resume                 = hda_dsp_resume,
  96         .runtime_suspend        = hda_dsp_runtime_suspend,
  97         .runtime_resume         = hda_dsp_runtime_resume,
  98         .runtime_idle           = hda_dsp_runtime_idle,
  99         .set_hw_params_upon_resume = hda_dsp_set_hw_params_upon_resume,
 100 };
 101 EXPORT_SYMBOL(sof_apl_ops);
 102 
 103 const struct sof_intel_dsp_desc apl_chip_info = {
 104         /* Apollolake */
 105         .cores_num = 2,
 106         .init_core_mask = 1,
 107         .cores_mask = HDA_DSP_CORE_MASK(0) | HDA_DSP_CORE_MASK(1),
 108         .ipc_req = HDA_DSP_REG_HIPCI,
 109         .ipc_req_mask = HDA_DSP_REG_HIPCI_BUSY,
 110         .ipc_ack = HDA_DSP_REG_HIPCIE,
 111         .ipc_ack_mask = HDA_DSP_REG_HIPCIE_DONE,
 112         .ipc_ctl = HDA_DSP_REG_HIPCCTL,
 113         .rom_init_timeout       = 150,
 114         .ssp_count = APL_SSP_COUNT,
 115         .ssp_base_offset = APL_SSP_BASE_OFFSET,
 116 };
 117 EXPORT_SYMBOL(apl_chip_info);