root/sound/soc/atmel/mchp-i2s-mcc.c

/* [<][>][^][v][top][bottom][index][help] */

DEFINITIONS

This source file includes following definitions.
  1. mchp_i2s_mcc_interrupt
  2. mchp_i2s_mcc_set_sysclk
  3. mchp_i2s_mcc_set_bclk_ratio
  4. mchp_i2s_mcc_set_dai_fmt
  5. mchp_i2s_mcc_set_dai_tdm_slot
  6. mchp_i2s_mcc_clk_get_rate_diff
  7. mchp_i2s_mcc_config_divs
  8. mchp_i2s_mcc_is_running
  9. mchp_i2s_mcc_hw_params
  10. mchp_i2s_mcc_hw_free
  11. mchp_i2s_mcc_trigger
  12. mchp_i2s_mcc_startup
  13. mchp_i2s_mcc_dai_probe
  14. mchp_i2s_mcc_probe
  15. mchp_i2s_mcc_remove

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Driver for Microchip I2S Multi-channel controller
   4 //
   5 // Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
   6 //
   7 // Author: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
   8 
   9 #include <linux/init.h>
  10 #include <linux/module.h>
  11 #include <linux/device.h>
  12 #include <linux/slab.h>
  13 
  14 #include <linux/delay.h>
  15 #include <linux/io.h>
  16 #include <linux/clk.h>
  17 #include <linux/mfd/syscon.h>
  18 #include <linux/lcm.h>
  19 
  20 #include <sound/core.h>
  21 #include <sound/pcm.h>
  22 #include <sound/pcm_params.h>
  23 #include <sound/initval.h>
  24 #include <sound/soc.h>
  25 #include <sound/dmaengine_pcm.h>
  26 
  27 /*
  28  * ---- I2S Controller Register map ----
  29  */
  30 #define MCHP_I2SMCC_CR          0x0000  /* Control Register */
  31 #define MCHP_I2SMCC_MRA         0x0004  /* Mode Register A */
  32 #define MCHP_I2SMCC_MRB         0x0008  /* Mode Register B */
  33 #define MCHP_I2SMCC_SR          0x000C  /* Status Register */
  34 #define MCHP_I2SMCC_IERA        0x0010  /* Interrupt Enable Register A */
  35 #define MCHP_I2SMCC_IDRA        0x0014  /* Interrupt Disable Register A */
  36 #define MCHP_I2SMCC_IMRA        0x0018  /* Interrupt Mask Register A */
  37 #define MCHP_I2SMCC_ISRA        0X001C  /* Interrupt Status Register A */
  38 
  39 #define MCHP_I2SMCC_IERB        0x0020  /* Interrupt Enable Register B */
  40 #define MCHP_I2SMCC_IDRB        0x0024  /* Interrupt Disable Register B */
  41 #define MCHP_I2SMCC_IMRB        0x0028  /* Interrupt Mask Register B */
  42 #define MCHP_I2SMCC_ISRB        0X002C  /* Interrupt Status Register B */
  43 
  44 #define MCHP_I2SMCC_RHR         0x0030  /* Receiver Holding Register */
  45 #define MCHP_I2SMCC_THR         0x0034  /* Transmitter Holding Register */
  46 
  47 #define MCHP_I2SMCC_RHL0R       0x0040  /* Receiver Holding Left 0 Register */
  48 #define MCHP_I2SMCC_RHR0R       0x0044  /* Receiver Holding Right 0 Register */
  49 
  50 #define MCHP_I2SMCC_RHL1R       0x0048  /* Receiver Holding Left 1 Register */
  51 #define MCHP_I2SMCC_RHR1R       0x004C  /* Receiver Holding Right 1 Register */
  52 
  53 #define MCHP_I2SMCC_RHL2R       0x0050  /* Receiver Holding Left 2 Register */
  54 #define MCHP_I2SMCC_RHR2R       0x0054  /* Receiver Holding Right 2 Register */
  55 
  56 #define MCHP_I2SMCC_RHL3R       0x0058  /* Receiver Holding Left 3 Register */
  57 #define MCHP_I2SMCC_RHR3R       0x005C  /* Receiver Holding Right 3 Register */
  58 
  59 #define MCHP_I2SMCC_THL0R       0x0060  /* Transmitter Holding Left 0 Register */
  60 #define MCHP_I2SMCC_THR0R       0x0064  /* Transmitter Holding Right 0 Register */
  61 
  62 #define MCHP_I2SMCC_THL1R       0x0068  /* Transmitter Holding Left 1 Register */
  63 #define MCHP_I2SMCC_THR1R       0x006C  /* Transmitter Holding Right 1 Register */
  64 
  65 #define MCHP_I2SMCC_THL2R       0x0070  /* Transmitter Holding Left 2 Register */
  66 #define MCHP_I2SMCC_THR2R       0x0074  /* Transmitter Holding Right 2 Register */
  67 
  68 #define MCHP_I2SMCC_THL3R       0x0078  /* Transmitter Holding Left 3 Register */
  69 #define MCHP_I2SMCC_THR3R       0x007C  /* Transmitter Holding Right 3 Register */
  70 
  71 #define MCHP_I2SMCC_VERSION     0x00FC  /* Version Register */
  72 
  73 /*
  74  * ---- Control Register (Write-only) ----
  75  */
  76 #define MCHP_I2SMCC_CR_RXEN             BIT(0)  /* Receiver Enable */
  77 #define MCHP_I2SMCC_CR_RXDIS            BIT(1)  /* Receiver Disable */
  78 #define MCHP_I2SMCC_CR_CKEN             BIT(2)  /* Clock Enable */
  79 #define MCHP_I2SMCC_CR_CKDIS            BIT(3)  /* Clock Disable */
  80 #define MCHP_I2SMCC_CR_TXEN             BIT(4)  /* Transmitter Enable */
  81 #define MCHP_I2SMCC_CR_TXDIS            BIT(5)  /* Transmitter Disable */
  82 #define MCHP_I2SMCC_CR_SWRST            BIT(7)  /* Software Reset */
  83 
  84 /*
  85  * ---- Mode Register A (Read/Write) ----
  86  */
  87 #define MCHP_I2SMCC_MRA_MODE_MASK               GENMASK(0, 0)
  88 #define MCHP_I2SMCC_MRA_MODE_SLAVE              (0 << 0)
  89 #define MCHP_I2SMCC_MRA_MODE_MASTER             (1 << 0)
  90 
  91 #define MCHP_I2SMCC_MRA_DATALENGTH_MASK                 GENMASK(3, 1)
  92 #define MCHP_I2SMCC_MRA_DATALENGTH_32_BITS              (0 << 1)
  93 #define MCHP_I2SMCC_MRA_DATALENGTH_24_BITS              (1 << 1)
  94 #define MCHP_I2SMCC_MRA_DATALENGTH_20_BITS              (2 << 1)
  95 #define MCHP_I2SMCC_MRA_DATALENGTH_18_BITS              (3 << 1)
  96 #define MCHP_I2SMCC_MRA_DATALENGTH_16_BITS              (4 << 1)
  97 #define MCHP_I2SMCC_MRA_DATALENGTH_16_BITS_COMPACT      (5 << 1)
  98 #define MCHP_I2SMCC_MRA_DATALENGTH_8_BITS               (6 << 1)
  99 #define MCHP_I2SMCC_MRA_DATALENGTH_8_BITS_COMPACT       (7 << 1)
 100 
 101 #define MCHP_I2SMCC_MRA_WIRECFG_MASK            GENMASK(5, 4)
 102 #define MCHP_I2SMCC_MRA_WIRECFG_I2S_1_TDM_0     (0 << 4)
 103 #define MCHP_I2SMCC_MRA_WIRECFG_I2S_2_TDM_1     (1 << 4)
 104 #define MCHP_I2SMCC_MRA_WIRECFG_I2S_4_TDM_2     (2 << 4)
 105 #define MCHP_I2SMCC_MRA_WIRECFG_TDM_3           (3 << 4)
 106 
 107 #define MCHP_I2SMCC_MRA_FORMAT_MASK             GENMASK(7, 6)
 108 #define MCHP_I2SMCC_MRA_FORMAT_I2S              (0 << 6)
 109 #define MCHP_I2SMCC_MRA_FORMAT_LJ               (1 << 6) /* Left Justified */
 110 #define MCHP_I2SMCC_MRA_FORMAT_TDM              (2 << 6)
 111 #define MCHP_I2SMCC_MRA_FORMAT_TDMLJ            (3 << 6)
 112 
 113 /* Transmitter uses one DMA channel ... */
 114 /* Left audio samples duplicated to right audio channel */
 115 #define MCHP_I2SMCC_MRA_RXMONO                  BIT(8)
 116 
 117 /* I2SDO output of I2SC is internally connected to I2SDI input */
 118 #define MCHP_I2SMCC_MRA_RXLOOP                  BIT(9)
 119 
 120 /* Receiver uses one DMA channel ... */
 121 /* Left audio samples duplicated to right audio channel */
 122 #define MCHP_I2SMCC_MRA_TXMONO                  BIT(10)
 123 
 124 /* x sample transmitted when underrun */
 125 #define MCHP_I2SMCC_MRA_TXSAME_ZERO             (0 << 11) /* Zero sample */
 126 #define MCHP_I2SMCC_MRA_TXSAME_PREVIOUS         (1 << 11) /* Previous sample */
 127 
 128 /* select between peripheral clock and generated clock */
 129 #define MCHP_I2SMCC_MRA_SRCCLK_PCLK             (0 << 12)
 130 #define MCHP_I2SMCC_MRA_SRCCLK_GCLK             (1 << 12)
 131 
 132 /* Number of TDM Channels - 1 */
 133 #define MCHP_I2SMCC_MRA_NBCHAN_MASK             GENMASK(15, 13)
 134 #define MCHP_I2SMCC_MRA_NBCHAN(ch) \
 135         ((((ch) - 1) << 13) & MCHP_I2SMCC_MRA_NBCHAN_MASK)
 136 
 137 /* Selected Clock to I2SMCC Master Clock ratio */
 138 #define MCHP_I2SMCC_MRA_IMCKDIV_MASK            GENMASK(21, 16)
 139 #define MCHP_I2SMCC_MRA_IMCKDIV(div) \
 140         (((div) << 16) & MCHP_I2SMCC_MRA_IMCKDIV_MASK)
 141 
 142 /* TDM Frame Synchronization */
 143 #define MCHP_I2SMCC_MRA_TDMFS_MASK              GENMASK(23, 22)
 144 #define MCHP_I2SMCC_MRA_TDMFS_SLOT              (0 << 22)
 145 #define MCHP_I2SMCC_MRA_TDMFS_HALF              (1 << 22)
 146 #define MCHP_I2SMCC_MRA_TDMFS_BIT               (2 << 22)
 147 
 148 /* Selected Clock to I2SMC Serial Clock ratio */
 149 #define MCHP_I2SMCC_MRA_ISCKDIV_MASK            GENMASK(29, 24)
 150 #define MCHP_I2SMCC_MRA_ISCKDIV(div) \
 151         (((div) << 24) & MCHP_I2SMCC_MRA_ISCKDIV_MASK)
 152 
 153 /* Master Clock mode */
 154 #define MCHP_I2SMCC_MRA_IMCKMODE_MASK           GENMASK(30, 30)
 155 /* 0: No master clock generated*/
 156 #define MCHP_I2SMCC_MRA_IMCKMODE_NONE           (0 << 30)
 157 /* 1: master clock generated (internally generated clock drives I2SMCK pin) */
 158 #define MCHP_I2SMCC_MRA_IMCKMODE_GEN            (1 << 30)
 159 
 160 /* Slot Width */
 161 /* 0: slot is 32 bits wide for DATALENGTH = 18/20/24 bits. */
 162 /* 1: slot is 24 bits wide for DATALENGTH = 18/20/24 bits. */
 163 #define MCHP_I2SMCC_MRA_IWS                     BIT(31)
 164 
 165 /*
 166  * ---- Mode Register B (Read/Write) ----
 167  */
 168 /* all enabled I2S left channels are filled first, then I2S right channels */
 169 #define MCHP_I2SMCC_MRB_CRAMODE_LEFT_FIRST      (0 << 0)
 170 /*
 171  * an enabled I2S left channel is filled, then the corresponding right
 172  * channel, until all channels are filled
 173  */
 174 #define MCHP_I2SMCC_MRB_CRAMODE_REGULAR         (1 << 0)
 175 
 176 #define MCHP_I2SMCC_MRB_FIFOEN                  BIT(1)
 177 
 178 #define MCHP_I2SMCC_MRB_DMACHUNK_MASK           GENMASK(9, 8)
 179 #define MCHP_I2SMCC_MRB_DMACHUNK(no_words) \
 180         (((fls(no_words) - 1) << 8) & MCHP_I2SMCC_MRB_DMACHUNK_MASK)
 181 
 182 #define MCHP_I2SMCC_MRB_CLKSEL_MASK             GENMASK(16, 16)
 183 #define MCHP_I2SMCC_MRB_CLKSEL_EXT              (0 << 16)
 184 #define MCHP_I2SMCC_MRB_CLKSEL_INT              (1 << 16)
 185 
 186 /*
 187  * ---- Status Registers (Read-only) ----
 188  */
 189 #define MCHP_I2SMCC_SR_RXEN             BIT(0)  /* Receiver Enabled */
 190 #define MCHP_I2SMCC_SR_TXEN             BIT(4)  /* Transmitter Enabled */
 191 
 192 /*
 193  * ---- Interrupt Enable/Disable/Mask/Status Registers A ----
 194  */
 195 #define MCHP_I2SMCC_INT_TXRDY_MASK(ch)          GENMASK((ch) - 1, 0)
 196 #define MCHP_I2SMCC_INT_TXRDYCH(ch)             BIT(ch)
 197 #define MCHP_I2SMCC_INT_TXUNF_MASK(ch)          GENMASK((ch) + 7, 8)
 198 #define MCHP_I2SMCC_INT_TXUNFCH(ch)             BIT((ch) + 8)
 199 #define MCHP_I2SMCC_INT_RXRDY_MASK(ch)          GENMASK((ch) + 15, 16)
 200 #define MCHP_I2SMCC_INT_RXRDYCH(ch)             BIT((ch) + 16)
 201 #define MCHP_I2SMCC_INT_RXOVF_MASK(ch)          GENMASK((ch) + 23, 24)
 202 #define MCHP_I2SMCC_INT_RXOVFCH(ch)             BIT((ch) + 24)
 203 
 204 /*
 205  * ---- Interrupt Enable/Disable/Mask/Status Registers B ----
 206  */
 207 #define MCHP_I2SMCC_INT_WERR                    BIT(0)
 208 #define MCHP_I2SMCC_INT_TXFFRDY                 BIT(8)
 209 #define MCHP_I2SMCC_INT_TXFFEMP                 BIT(9)
 210 #define MCHP_I2SMCC_INT_RXFFRDY                 BIT(12)
 211 #define MCHP_I2SMCC_INT_RXFFFUL                 BIT(13)
 212 
 213 /*
 214  * ---- Version Register (Read-only) ----
 215  */
 216 #define MCHP_I2SMCC_VERSION_MASK                GENMASK(11, 0)
 217 
 218 #define MCHP_I2SMCC_MAX_CHANNELS                8
 219 #define MCHP_I2MCC_TDM_SLOT_WIDTH               32
 220 
 221 static const struct regmap_config mchp_i2s_mcc_regmap_config = {
 222         .reg_bits = 32,
 223         .reg_stride = 4,
 224         .val_bits = 32,
 225         .max_register = MCHP_I2SMCC_VERSION,
 226 };
 227 
 228 struct mchp_i2s_mcc_dev {
 229         struct wait_queue_head                  wq_txrdy;
 230         struct wait_queue_head                  wq_rxrdy;
 231         struct device                           *dev;
 232         struct regmap                           *regmap;
 233         struct clk                              *pclk;
 234         struct clk                              *gclk;
 235         struct snd_dmaengine_dai_dma_data       playback;
 236         struct snd_dmaengine_dai_dma_data       capture;
 237         unsigned int                            fmt;
 238         unsigned int                            sysclk;
 239         unsigned int                            frame_length;
 240         int                                     tdm_slots;
 241         int                                     channels;
 242         int                                     gclk_use:1;
 243         int                                     gclk_running:1;
 244         int                                     tx_rdy:1;
 245         int                                     rx_rdy:1;
 246 };
 247 
 248 static irqreturn_t mchp_i2s_mcc_interrupt(int irq, void *dev_id)
 249 {
 250         struct mchp_i2s_mcc_dev *dev = dev_id;
 251         u32 sra, imra, srb, imrb, pendinga, pendingb, idra = 0;
 252         irqreturn_t ret = IRQ_NONE;
 253 
 254         regmap_read(dev->regmap, MCHP_I2SMCC_IMRA, &imra);
 255         regmap_read(dev->regmap, MCHP_I2SMCC_ISRA, &sra);
 256         pendinga = imra & sra;
 257 
 258         regmap_read(dev->regmap, MCHP_I2SMCC_IMRB, &imrb);
 259         regmap_read(dev->regmap, MCHP_I2SMCC_ISRB, &srb);
 260         pendingb = imrb & srb;
 261 
 262         if (!pendinga && !pendingb)
 263                 return IRQ_NONE;
 264 
 265         /*
 266          * Tx/Rx ready interrupts are enabled when stopping only, to assure
 267          * availability and to disable clocks if necessary
 268          */
 269         idra |= pendinga & (MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels) |
 270                             MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels));
 271         if (idra)
 272                 ret = IRQ_HANDLED;
 273 
 274         if ((imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) &&
 275             (imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) ==
 276             (idra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels))) {
 277                 dev->tx_rdy = 1;
 278                 wake_up_interruptible(&dev->wq_txrdy);
 279         }
 280         if ((imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) &&
 281             (imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) ==
 282             (idra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels))) {
 283                 dev->rx_rdy = 1;
 284                 wake_up_interruptible(&dev->wq_rxrdy);
 285         }
 286         regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, idra);
 287 
 288         return ret;
 289 }
 290 
 291 static int mchp_i2s_mcc_set_sysclk(struct snd_soc_dai *dai,
 292                                    int clk_id, unsigned int freq, int dir)
 293 {
 294         struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
 295 
 296         dev_dbg(dev->dev, "%s() clk_id=%d freq=%u dir=%d\n",
 297                 __func__, clk_id, freq, dir);
 298 
 299         /* We do not need SYSCLK */
 300         if (dir == SND_SOC_CLOCK_IN)
 301                 return 0;
 302 
 303         dev->sysclk = freq;
 304 
 305         return 0;
 306 }
 307 
 308 static int mchp_i2s_mcc_set_bclk_ratio(struct snd_soc_dai *dai,
 309                                        unsigned int ratio)
 310 {
 311         struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
 312 
 313         dev_dbg(dev->dev, "%s() ratio=%u\n", __func__, ratio);
 314 
 315         dev->frame_length = ratio;
 316 
 317         return 0;
 318 }
 319 
 320 static int mchp_i2s_mcc_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 321 {
 322         struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
 323 
 324         dev_dbg(dev->dev, "%s() fmt=%#x\n", __func__, fmt);
 325 
 326         /* We don't support any kind of clock inversion */
 327         if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF)
 328                 return -EINVAL;
 329 
 330         /* We can't generate only FSYNC */
 331         if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBM_CFS)
 332                 return -EINVAL;
 333 
 334         /* We can only reconfigure the IP when it's stopped */
 335         if (fmt & SND_SOC_DAIFMT_CONT)
 336                 return -EINVAL;
 337 
 338         dev->fmt = fmt;
 339 
 340         return 0;
 341 }
 342 
 343 static int mchp_i2s_mcc_set_dai_tdm_slot(struct snd_soc_dai *dai,
 344                                          unsigned int tx_mask,
 345                                          unsigned int rx_mask,
 346                                          int slots, int slot_width)
 347 {
 348         struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
 349 
 350         dev_dbg(dev->dev,
 351                 "%s() tx_mask=0x%08x rx_mask=0x%08x slots=%d width=%d\n",
 352                 __func__, tx_mask, rx_mask, slots, slot_width);
 353 
 354         if (slots < 0 || slots > MCHP_I2SMCC_MAX_CHANNELS ||
 355             slot_width != MCHP_I2MCC_TDM_SLOT_WIDTH)
 356                 return -EINVAL;
 357 
 358         if (slots) {
 359                 /* We do not support daisy chain */
 360                 if (rx_mask != GENMASK(slots - 1, 0) ||
 361                     rx_mask != tx_mask)
 362                         return -EINVAL;
 363         }
 364 
 365         dev->tdm_slots = slots;
 366         dev->frame_length = slots * MCHP_I2MCC_TDM_SLOT_WIDTH;
 367 
 368         return 0;
 369 }
 370 
 371 static int mchp_i2s_mcc_clk_get_rate_diff(struct clk *clk,
 372                                           unsigned long rate,
 373                                           struct clk **best_clk,
 374                                           unsigned long *best_rate,
 375                                           unsigned long *best_diff_rate)
 376 {
 377         long round_rate;
 378         unsigned int diff_rate;
 379 
 380         round_rate = clk_round_rate(clk, rate);
 381         if (round_rate < 0)
 382                 return (int)round_rate;
 383 
 384         diff_rate = abs(rate - round_rate);
 385         if (diff_rate < *best_diff_rate) {
 386                 *best_clk = clk;
 387                 *best_diff_rate = diff_rate;
 388                 *best_rate = rate;
 389         }
 390 
 391         return 0;
 392 }
 393 
 394 static int mchp_i2s_mcc_config_divs(struct mchp_i2s_mcc_dev *dev,
 395                                     unsigned int bclk, unsigned int *mra,
 396                                     unsigned long *best_rate)
 397 {
 398         unsigned long clk_rate;
 399         unsigned long lcm_rate;
 400         unsigned long best_diff_rate = ~0;
 401         unsigned int sysclk;
 402         struct clk *best_clk = NULL;
 403         int ret;
 404 
 405         /* For code simplification */
 406         if (!dev->sysclk)
 407                 sysclk = bclk;
 408         else
 409                 sysclk = dev->sysclk;
 410 
 411         /*
 412          * MCLK is Selected CLK / (2 * IMCKDIV),
 413          * BCLK is Selected CLK / (2 * ISCKDIV);
 414          * if IMCKDIV or ISCKDIV are 0, MCLK or BCLK = Selected CLK
 415          */
 416         lcm_rate = lcm(sysclk, bclk);
 417         if ((lcm_rate / sysclk % 2 == 1 && lcm_rate / sysclk > 2) ||
 418             (lcm_rate / bclk % 2 == 1 && lcm_rate / bclk > 2))
 419                 lcm_rate *= 2;
 420 
 421         for (clk_rate = lcm_rate;
 422              (clk_rate == sysclk || clk_rate / (sysclk * 2) <= GENMASK(5, 0)) &&
 423              (clk_rate == bclk || clk_rate / (bclk * 2) <= GENMASK(5, 0));
 424              clk_rate += lcm_rate) {
 425                 ret = mchp_i2s_mcc_clk_get_rate_diff(dev->gclk, clk_rate,
 426                                                      &best_clk, best_rate,
 427                                                      &best_diff_rate);
 428                 if (ret) {
 429                         dev_err(dev->dev, "gclk error for rate %lu: %d",
 430                                 clk_rate, ret);
 431                 } else {
 432                         if (!best_diff_rate) {
 433                                 dev_dbg(dev->dev, "found perfect rate on gclk: %lu\n",
 434                                         clk_rate);
 435                                 break;
 436                         }
 437                 }
 438 
 439                 ret = mchp_i2s_mcc_clk_get_rate_diff(dev->pclk, clk_rate,
 440                                                      &best_clk, best_rate,
 441                                                      &best_diff_rate);
 442                 if (ret) {
 443                         dev_err(dev->dev, "pclk error for rate %lu: %d",
 444                                 clk_rate, ret);
 445                 } else {
 446                         if (!best_diff_rate) {
 447                                 dev_dbg(dev->dev, "found perfect rate on pclk: %lu\n",
 448                                         clk_rate);
 449                                 break;
 450                         }
 451                 }
 452         }
 453 
 454         /* check if clocks returned only errors */
 455         if (!best_clk) {
 456                 dev_err(dev->dev, "unable to change rate to clocks\n");
 457                 return -EINVAL;
 458         }
 459 
 460         dev_dbg(dev->dev, "source CLK is %s with rate %lu, diff %lu\n",
 461                 best_clk == dev->pclk ? "pclk" : "gclk",
 462                 *best_rate, best_diff_rate);
 463 
 464         /* Configure divisors */
 465         if (dev->sysclk)
 466                 *mra |= MCHP_I2SMCC_MRA_IMCKDIV(*best_rate / (2 * sysclk));
 467         *mra |= MCHP_I2SMCC_MRA_ISCKDIV(*best_rate / (2 * bclk));
 468 
 469         if (best_clk == dev->gclk)
 470                 *mra |= MCHP_I2SMCC_MRA_SRCCLK_GCLK;
 471         else
 472                 *mra |= MCHP_I2SMCC_MRA_SRCCLK_PCLK;
 473 
 474         return 0;
 475 }
 476 
 477 static int mchp_i2s_mcc_is_running(struct mchp_i2s_mcc_dev *dev)
 478 {
 479         u32 sr;
 480 
 481         regmap_read(dev->regmap, MCHP_I2SMCC_SR, &sr);
 482         return !!(sr & (MCHP_I2SMCC_SR_TXEN | MCHP_I2SMCC_SR_RXEN));
 483 }
 484 
 485 static int mchp_i2s_mcc_hw_params(struct snd_pcm_substream *substream,
 486                                   struct snd_pcm_hw_params *params,
 487                                   struct snd_soc_dai *dai)
 488 {
 489         unsigned long rate = 0;
 490         struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
 491         u32 mra = 0;
 492         u32 mrb = 0;
 493         unsigned int channels = params_channels(params);
 494         unsigned int frame_length = dev->frame_length;
 495         unsigned int bclk_rate;
 496         int set_divs = 0;
 497         int ret;
 498         bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 499 
 500         dev_dbg(dev->dev, "%s() rate=%u format=%#x width=%u channels=%u\n",
 501                 __func__, params_rate(params), params_format(params),
 502                 params_width(params), params_channels(params));
 503 
 504         switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 505         case SND_SOC_DAIFMT_I2S:
 506                 if (dev->tdm_slots) {
 507                         dev_err(dev->dev, "I2S with TDM is not supported\n");
 508                         return -EINVAL;
 509                 }
 510                 mra |= MCHP_I2SMCC_MRA_FORMAT_I2S;
 511                 break;
 512         case SND_SOC_DAIFMT_LEFT_J:
 513                 if (dev->tdm_slots) {
 514                         dev_err(dev->dev, "Left-Justified with TDM is not supported\n");
 515                         return -EINVAL;
 516                 }
 517                 mra |= MCHP_I2SMCC_MRA_FORMAT_LJ;
 518                 break;
 519         case SND_SOC_DAIFMT_DSP_A:
 520                 mra |= MCHP_I2SMCC_MRA_FORMAT_TDM;
 521                 break;
 522         default:
 523                 dev_err(dev->dev, "unsupported bus format\n");
 524                 return -EINVAL;
 525         }
 526 
 527         switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 528         case SND_SOC_DAIFMT_CBS_CFS:
 529                 /* cpu is BCLK and LRC master */
 530                 mra |= MCHP_I2SMCC_MRA_MODE_MASTER;
 531                 if (dev->sysclk)
 532                         mra |= MCHP_I2SMCC_MRA_IMCKMODE_GEN;
 533                 set_divs = 1;
 534                 break;
 535         case SND_SOC_DAIFMT_CBS_CFM:
 536                 /* cpu is BCLK master */
 537                 mrb |= MCHP_I2SMCC_MRB_CLKSEL_INT;
 538                 set_divs = 1;
 539                 /* fall through */
 540         case SND_SOC_DAIFMT_CBM_CFM:
 541                 /* cpu is slave */
 542                 mra |= MCHP_I2SMCC_MRA_MODE_SLAVE;
 543                 if (dev->sysclk)
 544                         dev_warn(dev->dev, "Unable to generate MCLK in Slave mode\n");
 545                 break;
 546         default:
 547                 dev_err(dev->dev, "unsupported master/slave mode\n");
 548                 return -EINVAL;
 549         }
 550 
 551         if (dev->fmt & (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_LEFT_J)) {
 552                 switch (channels) {
 553                 case 1:
 554                         if (is_playback)
 555                                 mra |= MCHP_I2SMCC_MRA_TXMONO;
 556                         else
 557                                 mra |= MCHP_I2SMCC_MRA_RXMONO;
 558                         break;
 559                 case 2:
 560                         break;
 561                 default:
 562                         dev_err(dev->dev, "unsupported number of audio channels\n");
 563                         return -EINVAL;
 564                 }
 565 
 566                 if (!frame_length)
 567                         frame_length = 2 * params_physical_width(params);
 568         } else if (dev->fmt & SND_SOC_DAIFMT_DSP_A) {
 569                 if (dev->tdm_slots) {
 570                         if (channels % 2 && channels * 2 <= dev->tdm_slots) {
 571                                 /*
 572                                  * Duplicate data for even-numbered channels
 573                                  * to odd-numbered channels
 574                                  */
 575                                 if (is_playback)
 576                                         mra |= MCHP_I2SMCC_MRA_TXMONO;
 577                                 else
 578                                         mra |= MCHP_I2SMCC_MRA_RXMONO;
 579                         }
 580                         channels = dev->tdm_slots;
 581                 }
 582 
 583                 mra |= MCHP_I2SMCC_MRA_NBCHAN(channels);
 584                 if (!frame_length)
 585                         frame_length = channels * MCHP_I2MCC_TDM_SLOT_WIDTH;
 586         }
 587 
 588         /*
 589          * We must have the same burst size configured
 590          * in the DMA transfer and in out IP
 591          */
 592         mrb |= MCHP_I2SMCC_MRB_DMACHUNK(channels);
 593         if (is_playback)
 594                 dev->playback.maxburst = 1 << (fls(channels) - 1);
 595         else
 596                 dev->capture.maxburst = 1 << (fls(channels) - 1);
 597 
 598         switch (params_format(params)) {
 599         case SNDRV_PCM_FORMAT_S8:
 600                 mra |= MCHP_I2SMCC_MRA_DATALENGTH_8_BITS;
 601                 break;
 602         case SNDRV_PCM_FORMAT_S16_LE:
 603                 mra |= MCHP_I2SMCC_MRA_DATALENGTH_16_BITS;
 604                 break;
 605         case SNDRV_PCM_FORMAT_S18_3LE:
 606                 mra |= MCHP_I2SMCC_MRA_DATALENGTH_18_BITS |
 607                        MCHP_I2SMCC_MRA_IWS;
 608                 break;
 609         case SNDRV_PCM_FORMAT_S20_3LE:
 610                 mra |= MCHP_I2SMCC_MRA_DATALENGTH_20_BITS |
 611                        MCHP_I2SMCC_MRA_IWS;
 612                 break;
 613         case SNDRV_PCM_FORMAT_S24_3LE:
 614                 mra |= MCHP_I2SMCC_MRA_DATALENGTH_24_BITS |
 615                        MCHP_I2SMCC_MRA_IWS;
 616                 break;
 617         case SNDRV_PCM_FORMAT_S24_LE:
 618                 mra |= MCHP_I2SMCC_MRA_DATALENGTH_24_BITS;
 619                 break;
 620         case SNDRV_PCM_FORMAT_S32_LE:
 621                 mra |= MCHP_I2SMCC_MRA_DATALENGTH_32_BITS;
 622                 break;
 623         default:
 624                 dev_err(dev->dev, "unsupported size/endianness for audio samples\n");
 625                 return -EINVAL;
 626         }
 627 
 628         if (set_divs) {
 629                 bclk_rate = frame_length * params_rate(params);
 630                 ret = mchp_i2s_mcc_config_divs(dev, bclk_rate, &mra,
 631                                                &rate);
 632                 if (ret) {
 633                         dev_err(dev->dev,
 634                                 "unable to configure the divisors: %d\n", ret);
 635                         return ret;
 636                 }
 637         }
 638 
 639         /*
 640          * If we are already running, the wanted setup must be
 641          * the same with the one that's currently ongoing
 642          */
 643         if (mchp_i2s_mcc_is_running(dev)) {
 644                 u32 mra_cur;
 645                 u32 mrb_cur;
 646 
 647                 regmap_read(dev->regmap, MCHP_I2SMCC_MRA, &mra_cur);
 648                 regmap_read(dev->regmap, MCHP_I2SMCC_MRB, &mrb_cur);
 649                 if (mra != mra_cur || mrb != mrb_cur)
 650                         return -EINVAL;
 651 
 652                 return 0;
 653         }
 654 
 655         if (mra & MCHP_I2SMCC_MRA_SRCCLK_GCLK && !dev->gclk_use) {
 656                 /* set the rate */
 657                 ret = clk_set_rate(dev->gclk, rate);
 658                 if (ret) {
 659                         dev_err(dev->dev,
 660                                 "unable to set rate %lu to GCLK: %d\n",
 661                                 rate, ret);
 662                         return ret;
 663                 }
 664 
 665                 ret = clk_prepare(dev->gclk);
 666                 if (ret < 0) {
 667                         dev_err(dev->dev, "unable to prepare GCLK: %d\n", ret);
 668                         return ret;
 669                 }
 670                 dev->gclk_use = 1;
 671         }
 672 
 673         /* Save the number of channels to know what interrupts to enable */
 674         dev->channels = channels;
 675 
 676         ret = regmap_write(dev->regmap, MCHP_I2SMCC_MRA, mra);
 677         if (ret < 0) {
 678                 if (dev->gclk_use) {
 679                         clk_unprepare(dev->gclk);
 680                         dev->gclk_use = 0;
 681                 }
 682                 return ret;
 683         }
 684         return regmap_write(dev->regmap, MCHP_I2SMCC_MRB, mrb);
 685 }
 686 
 687 static int mchp_i2s_mcc_hw_free(struct snd_pcm_substream *substream,
 688                                 struct snd_soc_dai *dai)
 689 {
 690         struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
 691         bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 692         long err;
 693 
 694         if (is_playback) {
 695                 err = wait_event_interruptible_timeout(dev->wq_txrdy,
 696                                                        dev->tx_rdy,
 697                                                        msecs_to_jiffies(500));
 698                 if (err == 0) {
 699                         dev_warn_once(dev->dev,
 700                                       "Timeout waiting for Tx ready\n");
 701                         regmap_write(dev->regmap, MCHP_I2SMCC_IDRA,
 702                                      MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels));
 703                         dev->tx_rdy = 1;
 704                 }
 705         } else {
 706                 err = wait_event_interruptible_timeout(dev->wq_rxrdy,
 707                                                        dev->rx_rdy,
 708                                                        msecs_to_jiffies(500));
 709                 if (err == 0) {
 710                         dev_warn_once(dev->dev,
 711                                       "Timeout waiting for Rx ready\n");
 712                         regmap_write(dev->regmap, MCHP_I2SMCC_IDRA,
 713                                      MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels));
 714                         dev->rx_rdy = 1;
 715                 }
 716         }
 717 
 718         if (!mchp_i2s_mcc_is_running(dev)) {
 719                 regmap_write(dev->regmap, MCHP_I2SMCC_CR, MCHP_I2SMCC_CR_CKDIS);
 720 
 721                 if (dev->gclk_running) {
 722                         clk_disable(dev->gclk);
 723                         dev->gclk_running = 0;
 724                 }
 725                 if (dev->gclk_use) {
 726                         clk_unprepare(dev->gclk);
 727                         dev->gclk_use = 0;
 728                 }
 729         }
 730 
 731         return 0;
 732 }
 733 
 734 static int mchp_i2s_mcc_trigger(struct snd_pcm_substream *substream, int cmd,
 735                                 struct snd_soc_dai *dai)
 736 {
 737         struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
 738         bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 739         u32 cr = 0;
 740         u32 iera = 0;
 741         u32 sr;
 742         int err;
 743 
 744         switch (cmd) {
 745         case SNDRV_PCM_TRIGGER_START:
 746         case SNDRV_PCM_TRIGGER_RESUME:
 747         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 748                 if (is_playback)
 749                         cr = MCHP_I2SMCC_CR_TXEN | MCHP_I2SMCC_CR_CKEN;
 750                 else
 751                         cr = MCHP_I2SMCC_CR_RXEN | MCHP_I2SMCC_CR_CKEN;
 752                 break;
 753         case SNDRV_PCM_TRIGGER_STOP:
 754         case SNDRV_PCM_TRIGGER_SUSPEND:
 755         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 756                 regmap_read(dev->regmap, MCHP_I2SMCC_SR, &sr);
 757                 if (is_playback && (sr & MCHP_I2SMCC_SR_TXEN)) {
 758                         cr = MCHP_I2SMCC_CR_TXDIS;
 759                         dev->tx_rdy = 0;
 760                         /*
 761                          * Enable Tx Ready interrupts on all channels
 762                          * to assure all data is sent
 763                          */
 764                         iera = MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels);
 765                 } else if (!is_playback && (sr & MCHP_I2SMCC_SR_RXEN)) {
 766                         cr = MCHP_I2SMCC_CR_RXDIS;
 767                         dev->rx_rdy = 0;
 768                         /*
 769                          * Enable Rx Ready interrupts on all channels
 770                          * to assure all data is received
 771                          */
 772                         iera = MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels);
 773                 }
 774                 break;
 775         default:
 776                 return -EINVAL;
 777         }
 778 
 779         if ((cr & MCHP_I2SMCC_CR_CKEN) && dev->gclk_use &&
 780             !dev->gclk_running) {
 781                 err = clk_enable(dev->gclk);
 782                 if (err) {
 783                         dev_err_once(dev->dev, "failed to enable GCLK: %d\n",
 784                                      err);
 785                 } else {
 786                         dev->gclk_running = 1;
 787                 }
 788         }
 789 
 790         regmap_write(dev->regmap, MCHP_I2SMCC_IERA, iera);
 791         regmap_write(dev->regmap, MCHP_I2SMCC_CR, cr);
 792 
 793         return 0;
 794 }
 795 
 796 static int mchp_i2s_mcc_startup(struct snd_pcm_substream *substream,
 797                                 struct snd_soc_dai *dai)
 798 {
 799         struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
 800 
 801         /* Software reset the IP if it's not running */
 802         if (!mchp_i2s_mcc_is_running(dev)) {
 803                 return regmap_write(dev->regmap, MCHP_I2SMCC_CR,
 804                                     MCHP_I2SMCC_CR_SWRST);
 805         }
 806 
 807         return 0;
 808 }
 809 
 810 static const struct snd_soc_dai_ops mchp_i2s_mcc_dai_ops = {
 811         .set_sysclk     = mchp_i2s_mcc_set_sysclk,
 812         .set_bclk_ratio = mchp_i2s_mcc_set_bclk_ratio,
 813         .startup        = mchp_i2s_mcc_startup,
 814         .trigger        = mchp_i2s_mcc_trigger,
 815         .hw_params      = mchp_i2s_mcc_hw_params,
 816         .hw_free        = mchp_i2s_mcc_hw_free,
 817         .set_fmt        = mchp_i2s_mcc_set_dai_fmt,
 818         .set_tdm_slot   = mchp_i2s_mcc_set_dai_tdm_slot,
 819 };
 820 
 821 static int mchp_i2s_mcc_dai_probe(struct snd_soc_dai *dai)
 822 {
 823         struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
 824 
 825         init_waitqueue_head(&dev->wq_txrdy);
 826         init_waitqueue_head(&dev->wq_rxrdy);
 827         dev->tx_rdy = 1;
 828         dev->rx_rdy = 1;
 829 
 830         snd_soc_dai_init_dma_data(dai, &dev->playback, &dev->capture);
 831 
 832         return 0;
 833 }
 834 
 835 #define MCHP_I2SMCC_RATES              SNDRV_PCM_RATE_8000_192000
 836 
 837 #define MCHP_I2SMCC_FORMATS     (SNDRV_PCM_FMTBIT_S8 |          \
 838                                  SNDRV_PCM_FMTBIT_S16_LE |      \
 839                                  SNDRV_PCM_FMTBIT_S18_3LE |     \
 840                                  SNDRV_PCM_FMTBIT_S20_3LE |     \
 841                                  SNDRV_PCM_FMTBIT_S24_3LE |     \
 842                                  SNDRV_PCM_FMTBIT_S24_LE |      \
 843                                  SNDRV_PCM_FMTBIT_S32_LE)
 844 
 845 static struct snd_soc_dai_driver mchp_i2s_mcc_dai = {
 846         .probe  = mchp_i2s_mcc_dai_probe,
 847         .playback = {
 848                 .stream_name = "I2SMCC-Playback",
 849                 .channels_min = 1,
 850                 .channels_max = 8,
 851                 .rates = MCHP_I2SMCC_RATES,
 852                 .formats = MCHP_I2SMCC_FORMATS,
 853         },
 854         .capture = {
 855                 .stream_name = "I2SMCC-Capture",
 856                 .channels_min = 1,
 857                 .channels_max = 8,
 858                 .rates = MCHP_I2SMCC_RATES,
 859                 .formats = MCHP_I2SMCC_FORMATS,
 860         },
 861         .ops = &mchp_i2s_mcc_dai_ops,
 862         .symmetric_rates = 1,
 863         .symmetric_samplebits = 1,
 864         .symmetric_channels = 1,
 865 };
 866 
 867 static const struct snd_soc_component_driver mchp_i2s_mcc_component = {
 868         .name   = "mchp-i2s-mcc",
 869 };
 870 
 871 #ifdef CONFIG_OF
 872 static const struct of_device_id mchp_i2s_mcc_dt_ids[] = {
 873         {
 874                 .compatible = "microchip,sam9x60-i2smcc",
 875         },
 876         { /* sentinel */ }
 877 };
 878 MODULE_DEVICE_TABLE(of, mchp_i2s_mcc_dt_ids);
 879 #endif
 880 
 881 static int mchp_i2s_mcc_probe(struct platform_device *pdev)
 882 {
 883         struct mchp_i2s_mcc_dev *dev;
 884         struct resource *mem;
 885         struct regmap *regmap;
 886         void __iomem *base;
 887         u32 version;
 888         int irq;
 889         int err;
 890 
 891         dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
 892         if (!dev)
 893                 return -ENOMEM;
 894 
 895         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 896         base = devm_ioremap_resource(&pdev->dev, mem);
 897         if (IS_ERR(base))
 898                 return PTR_ERR(base);
 899 
 900         regmap = devm_regmap_init_mmio(&pdev->dev, base,
 901                                        &mchp_i2s_mcc_regmap_config);
 902         if (IS_ERR(regmap))
 903                 return PTR_ERR(regmap);
 904 
 905         irq = platform_get_irq(pdev, 0);
 906         if (irq < 0)
 907                 return irq;
 908 
 909         err = devm_request_irq(&pdev->dev, irq, mchp_i2s_mcc_interrupt, 0,
 910                                dev_name(&pdev->dev), dev);
 911         if (err)
 912                 return err;
 913 
 914         dev->pclk = devm_clk_get(&pdev->dev, "pclk");
 915         if (IS_ERR(dev->pclk)) {
 916                 err = PTR_ERR(dev->pclk);
 917                 dev_err(&pdev->dev,
 918                         "failed to get the peripheral clock: %d\n", err);
 919                 return err;
 920         }
 921 
 922         /* Get the optional generated clock */
 923         dev->gclk = devm_clk_get(&pdev->dev, "gclk");
 924         if (IS_ERR(dev->gclk)) {
 925                 if (PTR_ERR(dev->gclk) == -EPROBE_DEFER)
 926                         return -EPROBE_DEFER;
 927                 dev_warn(&pdev->dev,
 928                          "generated clock not found: %d\n", err);
 929                 dev->gclk = NULL;
 930         }
 931 
 932         dev->dev = &pdev->dev;
 933         dev->regmap = regmap;
 934         platform_set_drvdata(pdev, dev);
 935 
 936         err = clk_prepare_enable(dev->pclk);
 937         if (err) {
 938                 dev_err(&pdev->dev,
 939                         "failed to enable the peripheral clock: %d\n", err);
 940                 return err;
 941         }
 942 
 943         err = devm_snd_soc_register_component(&pdev->dev,
 944                                               &mchp_i2s_mcc_component,
 945                                               &mchp_i2s_mcc_dai, 1);
 946         if (err) {
 947                 dev_err(&pdev->dev, "failed to register DAI: %d\n", err);
 948                 clk_disable_unprepare(dev->pclk);
 949                 return err;
 950         }
 951 
 952         dev->playback.addr      = (dma_addr_t)mem->start + MCHP_I2SMCC_THR;
 953         dev->capture.addr       = (dma_addr_t)mem->start + MCHP_I2SMCC_RHR;
 954 
 955         err = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
 956         if (err) {
 957                 dev_err(&pdev->dev, "failed to register PCM: %d\n", err);
 958                 clk_disable_unprepare(dev->pclk);
 959                 return err;
 960         }
 961 
 962         /* Get IP version. */
 963         regmap_read(dev->regmap, MCHP_I2SMCC_VERSION, &version);
 964         dev_info(&pdev->dev, "hw version: %#lx\n",
 965                  version & MCHP_I2SMCC_VERSION_MASK);
 966 
 967         return 0;
 968 }
 969 
 970 static int mchp_i2s_mcc_remove(struct platform_device *pdev)
 971 {
 972         struct mchp_i2s_mcc_dev *dev = platform_get_drvdata(pdev);
 973 
 974         clk_disable_unprepare(dev->pclk);
 975 
 976         return 0;
 977 }
 978 
 979 static struct platform_driver mchp_i2s_mcc_driver = {
 980         .driver         = {
 981                 .name   = "mchp_i2s_mcc",
 982                 .of_match_table = of_match_ptr(mchp_i2s_mcc_dt_ids),
 983         },
 984         .probe          = mchp_i2s_mcc_probe,
 985         .remove         = mchp_i2s_mcc_remove,
 986 };
 987 module_platform_driver(mchp_i2s_mcc_driver);
 988 
 989 MODULE_DESCRIPTION("Microchip I2S Multi-Channel Controller driver");
 990 MODULE_AUTHOR("Codrin Ciubotariu <codrin.ciubotariu@microchip.com>");
 991 MODULE_LICENSE("GPL v2");

/* [<][>][^][v][top][bottom][index][help] */