root/sound/pci/hda/hda_intel.c

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DEFINITIONS

This source file includes following definitions.
  1. update_pci_byte
  2. azx_init_pci
  3. bxt_reduce_dma_latency
  4. intel_get_lctl_scf
  5. intel_ml_lctl_set_power
  6. intel_init_lctl
  7. hda_intel_init_chip
  8. azx_get_delay_from_lpib
  9. azx_position_check
  10. azx_position_ok
  11. azx_irq_pending_work
  12. azx_clear_irq_pending
  13. azx_acquire_irq
  14. azx_via_get_position
  15. azx_get_pos_fifo
  16. azx_get_delay_from_fifo
  17. azx_skl_get_dpib_pos
  18. azx_get_pos_skl
  19. azx_add_card_list
  20. azx_del_card_list
  21. param_set_xint
  22. azx_is_pm_ready
  23. __azx_runtime_suspend
  24. __azx_runtime_resume
  25. azx_suspend
  26. azx_resume
  27. azx_freeze_noirq
  28. azx_thaw_noirq
  29. azx_runtime_suspend
  30. azx_runtime_resume
  31. azx_runtime_idle
  32. azx_vs_set_state
  33. azx_vs_can_switch
  34. setup_vga_switcheroo_runtime_pm
  35. azx_vs_gpu_bound
  36. init_vga_switcheroo
  37. register_vga_switcheroo
  38. azx_free
  39. azx_dev_disconnect
  40. azx_dev_free
  41. get_bound_vga
  42. check_hdmi_disabled
  43. check_position_fix
  44. assign_position_fix
  45. check_probe_mask
  46. check_msi
  47. azx_check_snoop_available
  48. azx_probe_work
  49. default_bdl_pos_adj
  50. azx_create
  51. azx_first_init
  52. azx_firmware_cb
  53. disable_msi_reset_irq
  54. pcm_mmap_prepare
  55. azx_check_dmic
  56. azx_probe
  57. set_default_power_save
  58. azx_probe_continue
  59. azx_remove
  60. azx_shutdown

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *
   4  *  hda_intel.c - Implementation of primary alsa driver code base
   5  *                for Intel HD Audio.
   6  *
   7  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   8  *
   9  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
  10  *                     PeiSen Hou <pshou@realtek.com.tw>
  11  *
  12  *  CONTACTS:
  13  *
  14  *  Matt Jared          matt.jared@intel.com
  15  *  Andy Kopp           andy.kopp@intel.com
  16  *  Dan Kogan           dan.d.kogan@intel.com
  17  *
  18  *  CHANGES:
  19  *
  20  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  21  */
  22 
  23 #include <linux/delay.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/init.h>
  30 #include <linux/slab.h>
  31 #include <linux/pci.h>
  32 #include <linux/mutex.h>
  33 #include <linux/io.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/clocksource.h>
  36 #include <linux/time.h>
  37 #include <linux/completion.h>
  38 
  39 #ifdef CONFIG_X86
  40 /* for snoop control */
  41 #include <asm/pgtable.h>
  42 #include <asm/set_memory.h>
  43 #include <asm/cpufeature.h>
  44 #endif
  45 #include <sound/core.h>
  46 #include <sound/initval.h>
  47 #include <sound/hdaudio.h>
  48 #include <sound/hda_i915.h>
  49 #include <sound/intel-nhlt.h>
  50 #include <linux/vgaarb.h>
  51 #include <linux/vga_switcheroo.h>
  52 #include <linux/firmware.h>
  53 #include <sound/hda_codec.h>
  54 #include "hda_controller.h"
  55 #include "hda_intel.h"
  56 
  57 #define CREATE_TRACE_POINTS
  58 #include "hda_intel_trace.h"
  59 
  60 /* position fix mode */
  61 enum {
  62         POS_FIX_AUTO,
  63         POS_FIX_LPIB,
  64         POS_FIX_POSBUF,
  65         POS_FIX_VIACOMBO,
  66         POS_FIX_COMBO,
  67         POS_FIX_SKL,
  68         POS_FIX_FIFO,
  69 };
  70 
  71 /* Defines for ATI HD Audio support in SB450 south bridge */
  72 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  73 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  74 
  75 /* Defines for Nvidia HDA support */
  76 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  77 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  78 #define NVIDIA_HDA_ISTRM_COH          0x4d
  79 #define NVIDIA_HDA_OSTRM_COH          0x4c
  80 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  81 
  82 /* Defines for Intel SCH HDA snoop control */
  83 #define INTEL_HDA_CGCTL  0x48
  84 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  85 #define INTEL_SCH_HDA_DEVC      0x78
  86 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  87 
  88 /* Define VIA HD Audio Device ID*/
  89 #define VIA_HDAC_DEVICE_ID              0x3288
  90 
  91 /* max number of SDs */
  92 /* ICH, ATI and VIA have 4 playback and 4 capture */
  93 #define ICH6_NUM_CAPTURE        4
  94 #define ICH6_NUM_PLAYBACK       4
  95 
  96 /* ULI has 6 playback and 5 capture */
  97 #define ULI_NUM_CAPTURE         5
  98 #define ULI_NUM_PLAYBACK        6
  99 
 100 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 101 #define ATIHDMI_NUM_CAPTURE     0
 102 #define ATIHDMI_NUM_PLAYBACK    8
 103 
 104 /* TERA has 4 playback and 3 capture */
 105 #define TERA_NUM_CAPTURE        3
 106 #define TERA_NUM_PLAYBACK       4
 107 
 108 
 109 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 110 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 111 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 112 static char *model[SNDRV_CARDS];
 113 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 114 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 115 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 116 static int probe_only[SNDRV_CARDS];
 117 static int jackpoll_ms[SNDRV_CARDS];
 118 static int single_cmd = -1;
 119 static int enable_msi = -1;
 120 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 121 static char *patch[SNDRV_CARDS];
 122 #endif
 123 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 124 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 125                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 126 #endif
 127 static bool dmic_detect = IS_ENABLED(CONFIG_SND_HDA_INTEL_DETECT_DMIC);
 128 
 129 module_param_array(index, int, NULL, 0444);
 130 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 131 module_param_array(id, charp, NULL, 0444);
 132 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 133 module_param_array(enable, bool, NULL, 0444);
 134 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 135 module_param_array(model, charp, NULL, 0444);
 136 MODULE_PARM_DESC(model, "Use the given board model.");
 137 module_param_array(position_fix, int, NULL, 0444);
 138 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 139                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
 140 module_param_array(bdl_pos_adj, int, NULL, 0644);
 141 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 142 module_param_array(probe_mask, int, NULL, 0444);
 143 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 144 module_param_array(probe_only, int, NULL, 0444);
 145 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 146 module_param_array(jackpoll_ms, int, NULL, 0444);
 147 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 148 module_param(single_cmd, bint, 0444);
 149 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 150                  "(for debugging only).");
 151 module_param(enable_msi, bint, 0444);
 152 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 153 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 154 module_param_array(patch, charp, NULL, 0444);
 155 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 156 #endif
 157 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 158 module_param_array(beep_mode, bool, NULL, 0444);
 159 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 160                             "(0=off, 1=on) (default=1).");
 161 #endif
 162 module_param(dmic_detect, bool, 0444);
 163 MODULE_PARM_DESC(dmic_detect, "DMIC detect on SKL+ platforms");
 164 
 165 #ifdef CONFIG_PM
 166 static int param_set_xint(const char *val, const struct kernel_param *kp);
 167 static const struct kernel_param_ops param_ops_xint = {
 168         .set = param_set_xint,
 169         .get = param_get_int,
 170 };
 171 #define param_check_xint param_check_int
 172 
 173 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 174 module_param(power_save, xint, 0644);
 175 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 176                  "(in second, 0 = disable).");
 177 
 178 static bool pm_blacklist = true;
 179 module_param(pm_blacklist, bool, 0644);
 180 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
 181 
 182 /* reset the HD-audio controller in power save mode.
 183  * this may give more power-saving, but will take longer time to
 184  * wake up.
 185  */
 186 static bool power_save_controller = 1;
 187 module_param(power_save_controller, bool, 0644);
 188 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 189 #else
 190 #define power_save      0
 191 #endif /* CONFIG_PM */
 192 
 193 static int align_buffer_size = -1;
 194 module_param(align_buffer_size, bint, 0644);
 195 MODULE_PARM_DESC(align_buffer_size,
 196                 "Force buffer and period sizes to be multiple of 128 bytes.");
 197 
 198 #ifdef CONFIG_X86
 199 static int hda_snoop = -1;
 200 module_param_named(snoop, hda_snoop, bint, 0444);
 201 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 202 #else
 203 #define hda_snoop               true
 204 #endif
 205 
 206 
 207 MODULE_LICENSE("GPL");
 208 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 209                          "{Intel, ICH6M},"
 210                          "{Intel, ICH7},"
 211                          "{Intel, ESB2},"
 212                          "{Intel, ICH8},"
 213                          "{Intel, ICH9},"
 214                          "{Intel, ICH10},"
 215                          "{Intel, PCH},"
 216                          "{Intel, CPT},"
 217                          "{Intel, PPT},"
 218                          "{Intel, LPT},"
 219                          "{Intel, LPT_LP},"
 220                          "{Intel, WPT_LP},"
 221                          "{Intel, SPT},"
 222                          "{Intel, SPT_LP},"
 223                          "{Intel, HPT},"
 224                          "{Intel, PBG},"
 225                          "{Intel, SCH},"
 226                          "{ATI, SB450},"
 227                          "{ATI, SB600},"
 228                          "{ATI, RS600},"
 229                          "{ATI, RS690},"
 230                          "{ATI, RS780},"
 231                          "{ATI, R600},"
 232                          "{ATI, RV630},"
 233                          "{ATI, RV610},"
 234                          "{ATI, RV670},"
 235                          "{ATI, RV635},"
 236                          "{ATI, RV620},"
 237                          "{ATI, RV770},"
 238                          "{VIA, VT8251},"
 239                          "{VIA, VT8237A},"
 240                          "{SiS, SIS966},"
 241                          "{ULI, M5461}}");
 242 MODULE_DESCRIPTION("Intel HDA driver");
 243 
 244 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 245 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 246 #define SUPPORT_VGA_SWITCHEROO
 247 #endif
 248 #endif
 249 
 250 
 251 /*
 252  */
 253 
 254 /* driver types */
 255 enum {
 256         AZX_DRIVER_ICH,
 257         AZX_DRIVER_PCH,
 258         AZX_DRIVER_SCH,
 259         AZX_DRIVER_SKL,
 260         AZX_DRIVER_HDMI,
 261         AZX_DRIVER_ATI,
 262         AZX_DRIVER_ATIHDMI,
 263         AZX_DRIVER_ATIHDMI_NS,
 264         AZX_DRIVER_VIA,
 265         AZX_DRIVER_SIS,
 266         AZX_DRIVER_ULI,
 267         AZX_DRIVER_NVIDIA,
 268         AZX_DRIVER_TERA,
 269         AZX_DRIVER_CTX,
 270         AZX_DRIVER_CTHDA,
 271         AZX_DRIVER_CMEDIA,
 272         AZX_DRIVER_ZHAOXIN,
 273         AZX_DRIVER_GENERIC,
 274         AZX_NUM_DRIVERS, /* keep this as last entry */
 275 };
 276 
 277 #define azx_get_snoop_type(chip) \
 278         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 279 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 280 
 281 /* quirks for old Intel chipsets */
 282 #define AZX_DCAPS_INTEL_ICH \
 283         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE |\
 284          AZX_DCAPS_SYNC_WRITE)
 285 
 286 /* quirks for Intel PCH */
 287 #define AZX_DCAPS_INTEL_PCH_BASE \
 288         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 289          AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE)
 290 
 291 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
 292 #define AZX_DCAPS_INTEL_PCH_NOPM \
 293         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 294 
 295 /* PCH for HSW/BDW; with runtime PM */
 296 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
 297 #define AZX_DCAPS_INTEL_PCH \
 298         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 299 
 300 /* HSW HDMI */
 301 #define AZX_DCAPS_INTEL_HASWELL \
 302         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 303          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 304          AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE)
 305 
 306 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 307 #define AZX_DCAPS_INTEL_BROADWELL \
 308         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 309          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 310          AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE)
 311 
 312 #define AZX_DCAPS_INTEL_BAYTRAIL \
 313         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 314 
 315 #define AZX_DCAPS_INTEL_BRASWELL \
 316         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 317          AZX_DCAPS_I915_COMPONENT)
 318 
 319 #define AZX_DCAPS_INTEL_SKYLAKE \
 320         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 321          AZX_DCAPS_SYNC_WRITE |\
 322          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
 323 
 324 #define AZX_DCAPS_INTEL_BROXTON         AZX_DCAPS_INTEL_SKYLAKE
 325 
 326 /* quirks for ATI SB / AMD Hudson */
 327 #define AZX_DCAPS_PRESET_ATI_SB \
 328         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 329          AZX_DCAPS_SNOOP_TYPE(ATI))
 330 
 331 /* quirks for ATI/AMD HDMI */
 332 #define AZX_DCAPS_PRESET_ATI_HDMI \
 333         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 334          AZX_DCAPS_NO_MSI64)
 335 
 336 /* quirks for ATI HDMI with snoop off */
 337 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 338         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 339 
 340 /* quirks for AMD SB */
 341 #define AZX_DCAPS_PRESET_AMD_SB \
 342         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_AMD_WORKAROUND |\
 343          AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME)
 344 
 345 /* quirks for Nvidia */
 346 #define AZX_DCAPS_PRESET_NVIDIA \
 347         (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 348          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 349 
 350 #define AZX_DCAPS_PRESET_CTHDA \
 351         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 352          AZX_DCAPS_NO_64BIT |\
 353          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 354 
 355 /*
 356  * vga_switcheroo support
 357  */
 358 #ifdef SUPPORT_VGA_SWITCHEROO
 359 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 360 #define needs_eld_notify_link(chip)     ((chip)->bus.keep_power)
 361 #else
 362 #define use_vga_switcheroo(chip)        0
 363 #define needs_eld_notify_link(chip)     false
 364 #endif
 365 
 366 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 367                                         ((pci)->device == 0x0c0c) || \
 368                                         ((pci)->device == 0x0d0c) || \
 369                                         ((pci)->device == 0x160c))
 370 
 371 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 372 #define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
 373 #define IS_CNL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9dc8)
 374 
 375 static char *driver_short_names[] = {
 376         [AZX_DRIVER_ICH] = "HDA Intel",
 377         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 378         [AZX_DRIVER_SCH] = "HDA Intel MID",
 379         [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
 380         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 381         [AZX_DRIVER_ATI] = "HDA ATI SB",
 382         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 383         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 384         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 385         [AZX_DRIVER_SIS] = "HDA SIS966",
 386         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 387         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 388         [AZX_DRIVER_TERA] = "HDA Teradici", 
 389         [AZX_DRIVER_CTX] = "HDA Creative", 
 390         [AZX_DRIVER_CTHDA] = "HDA Creative",
 391         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 392         [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
 393         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 394 };
 395 
 396 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 397 static void set_default_power_save(struct azx *chip);
 398 
 399 /*
 400  * initialize the PCI registers
 401  */
 402 /* update bits in a PCI register byte */
 403 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 404                             unsigned char mask, unsigned char val)
 405 {
 406         unsigned char data;
 407 
 408         pci_read_config_byte(pci, reg, &data);
 409         data &= ~mask;
 410         data |= (val & mask);
 411         pci_write_config_byte(pci, reg, data);
 412 }
 413 
 414 static void azx_init_pci(struct azx *chip)
 415 {
 416         int snoop_type = azx_get_snoop_type(chip);
 417 
 418         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 419          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 420          * Ensuring these bits are 0 clears playback static on some HD Audio
 421          * codecs.
 422          * The PCI register TCSEL is defined in the Intel manuals.
 423          */
 424         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 425                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 426                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 427         }
 428 
 429         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 430          * we need to enable snoop.
 431          */
 432         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 433                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 434                         azx_snoop(chip));
 435                 update_pci_byte(chip->pci,
 436                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 437                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 438         }
 439 
 440         /* For NVIDIA HDA, enable snoop */
 441         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 442                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 443                         azx_snoop(chip));
 444                 update_pci_byte(chip->pci,
 445                                 NVIDIA_HDA_TRANSREG_ADDR,
 446                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 447                 update_pci_byte(chip->pci,
 448                                 NVIDIA_HDA_ISTRM_COH,
 449                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 450                 update_pci_byte(chip->pci,
 451                                 NVIDIA_HDA_OSTRM_COH,
 452                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 453         }
 454 
 455         /* Enable SCH/PCH snoop if needed */
 456         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 457                 unsigned short snoop;
 458                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 459                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 460                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 461                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 462                         if (!azx_snoop(chip))
 463                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 464                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 465                         pci_read_config_word(chip->pci,
 466                                 INTEL_SCH_HDA_DEVC, &snoop);
 467                 }
 468                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 469                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 470                         "Disabled" : "Enabled");
 471         }
 472 }
 473 
 474 /*
 475  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 476  * and makes an audio stream sensitive to system latencies when
 477  * 24/32 bits are playing.
 478  * Adjusting threshold of DMA fifo to force the DMA request
 479  * sooner to improve latency tolerance at the expense of power.
 480  */
 481 static void bxt_reduce_dma_latency(struct azx *chip)
 482 {
 483         u32 val;
 484 
 485         val = azx_readl(chip, VS_EM4L);
 486         val &= (0x3 << 20);
 487         azx_writel(chip, VS_EM4L, val);
 488 }
 489 
 490 /*
 491  * ML_LCAP bits:
 492  *  bit 0: 6 MHz Supported
 493  *  bit 1: 12 MHz Supported
 494  *  bit 2: 24 MHz Supported
 495  *  bit 3: 48 MHz Supported
 496  *  bit 4: 96 MHz Supported
 497  *  bit 5: 192 MHz Supported
 498  */
 499 static int intel_get_lctl_scf(struct azx *chip)
 500 {
 501         struct hdac_bus *bus = azx_bus(chip);
 502         static int preferred_bits[] = { 2, 3, 1, 4, 5 };
 503         u32 val, t;
 504         int i;
 505 
 506         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
 507 
 508         for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
 509                 t = preferred_bits[i];
 510                 if (val & (1 << t))
 511                         return t;
 512         }
 513 
 514         dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
 515         return 0;
 516 }
 517 
 518 static int intel_ml_lctl_set_power(struct azx *chip, int state)
 519 {
 520         struct hdac_bus *bus = azx_bus(chip);
 521         u32 val;
 522         int timeout;
 523 
 524         /*
 525          * the codecs are sharing the first link setting by default
 526          * If other links are enabled for stream, they need similar fix
 527          */
 528         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 529         val &= ~AZX_MLCTL_SPA;
 530         val |= state << AZX_MLCTL_SPA_SHIFT;
 531         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 532         /* wait for CPA */
 533         timeout = 50;
 534         while (timeout) {
 535                 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
 536                     AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
 537                         return 0;
 538                 timeout--;
 539                 udelay(10);
 540         }
 541 
 542         return -1;
 543 }
 544 
 545 static void intel_init_lctl(struct azx *chip)
 546 {
 547         struct hdac_bus *bus = azx_bus(chip);
 548         u32 val;
 549         int ret;
 550 
 551         /* 0. check lctl register value is correct or not */
 552         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 553         /* if SCF is already set, let's use it */
 554         if ((val & ML_LCTL_SCF_MASK) != 0)
 555                 return;
 556 
 557         /*
 558          * Before operating on SPA, CPA must match SPA.
 559          * Any deviation may result in undefined behavior.
 560          */
 561         if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
 562                 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
 563                 return;
 564 
 565         /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
 566         ret = intel_ml_lctl_set_power(chip, 0);
 567         udelay(100);
 568         if (ret)
 569                 goto set_spa;
 570 
 571         /* 2. update SCF to select a properly audio clock*/
 572         val &= ~ML_LCTL_SCF_MASK;
 573         val |= intel_get_lctl_scf(chip);
 574         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 575 
 576 set_spa:
 577         /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
 578         intel_ml_lctl_set_power(chip, 1);
 579         udelay(100);
 580 }
 581 
 582 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 583 {
 584         struct hdac_bus *bus = azx_bus(chip);
 585         struct pci_dev *pci = chip->pci;
 586         u32 val;
 587 
 588         snd_hdac_set_codec_wakeup(bus, true);
 589         if (chip->driver_type == AZX_DRIVER_SKL) {
 590                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 591                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 592                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 593         }
 594         azx_init_chip(chip, full_reset);
 595         if (chip->driver_type == AZX_DRIVER_SKL) {
 596                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 597                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 598                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 599         }
 600 
 601         snd_hdac_set_codec_wakeup(bus, false);
 602 
 603         /* reduce dma latency to avoid noise */
 604         if (IS_BXT(pci))
 605                 bxt_reduce_dma_latency(chip);
 606 
 607         if (bus->mlcap != NULL)
 608                 intel_init_lctl(chip);
 609 }
 610 
 611 /* calculate runtime delay from LPIB */
 612 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 613                                    unsigned int pos)
 614 {
 615         struct snd_pcm_substream *substream = azx_dev->core.substream;
 616         int stream = substream->stream;
 617         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 618         int delay;
 619 
 620         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 621                 delay = pos - lpib_pos;
 622         else
 623                 delay = lpib_pos - pos;
 624         if (delay < 0) {
 625                 if (delay >= azx_dev->core.delay_negative_threshold)
 626                         delay = 0;
 627                 else
 628                         delay += azx_dev->core.bufsize;
 629         }
 630 
 631         if (delay >= azx_dev->core.period_bytes) {
 632                 dev_info(chip->card->dev,
 633                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 634                          delay, azx_dev->core.period_bytes);
 635                 delay = 0;
 636                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 637                 chip->get_delay[stream] = NULL;
 638         }
 639 
 640         return bytes_to_frames(substream->runtime, delay);
 641 }
 642 
 643 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 644 
 645 /* called from IRQ */
 646 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 647 {
 648         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 649         int ok;
 650 
 651         ok = azx_position_ok(chip, azx_dev);
 652         if (ok == 1) {
 653                 azx_dev->irq_pending = 0;
 654                 return ok;
 655         } else if (ok == 0) {
 656                 /* bogus IRQ, process it later */
 657                 azx_dev->irq_pending = 1;
 658                 schedule_work(&hda->irq_pending_work);
 659         }
 660         return 0;
 661 }
 662 
 663 #define display_power(chip, enable) \
 664         snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
 665 
 666 /*
 667  * Check whether the current DMA position is acceptable for updating
 668  * periods.  Returns non-zero if it's OK.
 669  *
 670  * Many HD-audio controllers appear pretty inaccurate about
 671  * the update-IRQ timing.  The IRQ is issued before actually the
 672  * data is processed.  So, we need to process it afterwords in a
 673  * workqueue.
 674  */
 675 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 676 {
 677         struct snd_pcm_substream *substream = azx_dev->core.substream;
 678         int stream = substream->stream;
 679         u32 wallclk;
 680         unsigned int pos;
 681 
 682         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 683         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 684                 return -1;      /* bogus (too early) interrupt */
 685 
 686         if (chip->get_position[stream])
 687                 pos = chip->get_position[stream](chip, azx_dev);
 688         else { /* use the position buffer as default */
 689                 pos = azx_get_pos_posbuf(chip, azx_dev);
 690                 if (!pos || pos == (u32)-1) {
 691                         dev_info(chip->card->dev,
 692                                  "Invalid position buffer, using LPIB read method instead.\n");
 693                         chip->get_position[stream] = azx_get_pos_lpib;
 694                         if (chip->get_position[0] == azx_get_pos_lpib &&
 695                             chip->get_position[1] == azx_get_pos_lpib)
 696                                 azx_bus(chip)->use_posbuf = false;
 697                         pos = azx_get_pos_lpib(chip, azx_dev);
 698                         chip->get_delay[stream] = NULL;
 699                 } else {
 700                         chip->get_position[stream] = azx_get_pos_posbuf;
 701                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 702                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 703                 }
 704         }
 705 
 706         if (pos >= azx_dev->core.bufsize)
 707                 pos = 0;
 708 
 709         if (WARN_ONCE(!azx_dev->core.period_bytes,
 710                       "hda-intel: zero azx_dev->period_bytes"))
 711                 return -1; /* this shouldn't happen! */
 712         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 713             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 714                 /* NG - it's below the first next period boundary */
 715                 return chip->bdl_pos_adj ? 0 : -1;
 716         azx_dev->core.start_wallclk += wallclk;
 717         return 1; /* OK, it's fine */
 718 }
 719 
 720 /*
 721  * The work for pending PCM period updates.
 722  */
 723 static void azx_irq_pending_work(struct work_struct *work)
 724 {
 725         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 726         struct azx *chip = &hda->chip;
 727         struct hdac_bus *bus = azx_bus(chip);
 728         struct hdac_stream *s;
 729         int pending, ok;
 730 
 731         if (!hda->irq_pending_warned) {
 732                 dev_info(chip->card->dev,
 733                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 734                          chip->card->number);
 735                 hda->irq_pending_warned = 1;
 736         }
 737 
 738         for (;;) {
 739                 pending = 0;
 740                 spin_lock_irq(&bus->reg_lock);
 741                 list_for_each_entry(s, &bus->stream_list, list) {
 742                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 743                         if (!azx_dev->irq_pending ||
 744                             !s->substream ||
 745                             !s->running)
 746                                 continue;
 747                         ok = azx_position_ok(chip, azx_dev);
 748                         if (ok > 0) {
 749                                 azx_dev->irq_pending = 0;
 750                                 spin_unlock(&bus->reg_lock);
 751                                 snd_pcm_period_elapsed(s->substream);
 752                                 spin_lock(&bus->reg_lock);
 753                         } else if (ok < 0) {
 754                                 pending = 0;    /* too early */
 755                         } else
 756                                 pending++;
 757                 }
 758                 spin_unlock_irq(&bus->reg_lock);
 759                 if (!pending)
 760                         return;
 761                 msleep(1);
 762         }
 763 }
 764 
 765 /* clear irq_pending flags and assure no on-going workq */
 766 static void azx_clear_irq_pending(struct azx *chip)
 767 {
 768         struct hdac_bus *bus = azx_bus(chip);
 769         struct hdac_stream *s;
 770 
 771         spin_lock_irq(&bus->reg_lock);
 772         list_for_each_entry(s, &bus->stream_list, list) {
 773                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 774                 azx_dev->irq_pending = 0;
 775         }
 776         spin_unlock_irq(&bus->reg_lock);
 777 }
 778 
 779 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 780 {
 781         struct hdac_bus *bus = azx_bus(chip);
 782 
 783         if (request_irq(chip->pci->irq, azx_interrupt,
 784                         chip->msi ? 0 : IRQF_SHARED,
 785                         chip->card->irq_descr, chip)) {
 786                 dev_err(chip->card->dev,
 787                         "unable to grab IRQ %d, disabling device\n",
 788                         chip->pci->irq);
 789                 if (do_disconnect)
 790                         snd_card_disconnect(chip->card);
 791                 return -1;
 792         }
 793         bus->irq = chip->pci->irq;
 794         pci_intx(chip->pci, !chip->msi);
 795         return 0;
 796 }
 797 
 798 /* get the current DMA position with correction on VIA chips */
 799 static unsigned int azx_via_get_position(struct azx *chip,
 800                                          struct azx_dev *azx_dev)
 801 {
 802         unsigned int link_pos, mini_pos, bound_pos;
 803         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 804         unsigned int fifo_size;
 805 
 806         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 807         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 808                 /* Playback, no problem using link position */
 809                 return link_pos;
 810         }
 811 
 812         /* Capture */
 813         /* For new chipset,
 814          * use mod to get the DMA position just like old chipset
 815          */
 816         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 817         mod_dma_pos %= azx_dev->core.period_bytes;
 818 
 819         fifo_size = azx_stream(azx_dev)->fifo_size - 1;
 820 
 821         if (azx_dev->insufficient) {
 822                 /* Link position never gather than FIFO size */
 823                 if (link_pos <= fifo_size)
 824                         return 0;
 825 
 826                 azx_dev->insufficient = 0;
 827         }
 828 
 829         if (link_pos <= fifo_size)
 830                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 831         else
 832                 mini_pos = link_pos - fifo_size;
 833 
 834         /* Find nearest previous boudary */
 835         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 836         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 837         if (mod_link_pos >= fifo_size)
 838                 bound_pos = link_pos - mod_link_pos;
 839         else if (mod_dma_pos >= mod_mini_pos)
 840                 bound_pos = mini_pos - mod_mini_pos;
 841         else {
 842                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 843                 if (bound_pos >= azx_dev->core.bufsize)
 844                         bound_pos = 0;
 845         }
 846 
 847         /* Calculate real DMA position we want */
 848         return bound_pos + mod_dma_pos;
 849 }
 850 
 851 #define AMD_FIFO_SIZE   32
 852 
 853 /* get the current DMA position with FIFO size correction */
 854 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
 855 {
 856         struct snd_pcm_substream *substream = azx_dev->core.substream;
 857         struct snd_pcm_runtime *runtime = substream->runtime;
 858         unsigned int pos, delay;
 859 
 860         pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 861         if (!runtime)
 862                 return pos;
 863 
 864         runtime->delay = AMD_FIFO_SIZE;
 865         delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
 866         if (azx_dev->insufficient) {
 867                 if (pos < delay) {
 868                         delay = pos;
 869                         runtime->delay = bytes_to_frames(runtime, pos);
 870                 } else {
 871                         azx_dev->insufficient = 0;
 872                 }
 873         }
 874 
 875         /* correct the DMA position for capture stream */
 876         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 877                 if (pos < delay)
 878                         pos += azx_dev->core.bufsize;
 879                 pos -= delay;
 880         }
 881 
 882         return pos;
 883 }
 884 
 885 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
 886                                    unsigned int pos)
 887 {
 888         struct snd_pcm_substream *substream = azx_dev->core.substream;
 889 
 890         /* just read back the calculated value in the above */
 891         return substream->runtime->delay;
 892 }
 893 
 894 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
 895                                          struct azx_dev *azx_dev)
 896 {
 897         return _snd_hdac_chip_readl(azx_bus(chip),
 898                                     AZX_REG_VS_SDXDPIB_XBASE +
 899                                     (AZX_REG_VS_SDXDPIB_XINTERVAL *
 900                                      azx_dev->core.index));
 901 }
 902 
 903 /* get the current DMA position with correction on SKL+ chips */
 904 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
 905 {
 906         /* DPIB register gives a more accurate position for playback */
 907         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 908                 return azx_skl_get_dpib_pos(chip, azx_dev);
 909 
 910         /* For capture, we need to read posbuf, but it requires a delay
 911          * for the possible boundary overlap; the read of DPIB fetches the
 912          * actual posbuf
 913          */
 914         udelay(20);
 915         azx_skl_get_dpib_pos(chip, azx_dev);
 916         return azx_get_pos_posbuf(chip, azx_dev);
 917 }
 918 
 919 #ifdef CONFIG_PM
 920 static DEFINE_MUTEX(card_list_lock);
 921 static LIST_HEAD(card_list);
 922 
 923 static void azx_add_card_list(struct azx *chip)
 924 {
 925         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 926         mutex_lock(&card_list_lock);
 927         list_add(&hda->list, &card_list);
 928         mutex_unlock(&card_list_lock);
 929 }
 930 
 931 static void azx_del_card_list(struct azx *chip)
 932 {
 933         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 934         mutex_lock(&card_list_lock);
 935         list_del_init(&hda->list);
 936         mutex_unlock(&card_list_lock);
 937 }
 938 
 939 /* trigger power-save check at writing parameter */
 940 static int param_set_xint(const char *val, const struct kernel_param *kp)
 941 {
 942         struct hda_intel *hda;
 943         struct azx *chip;
 944         int prev = power_save;
 945         int ret = param_set_int(val, kp);
 946 
 947         if (ret || prev == power_save)
 948                 return ret;
 949 
 950         mutex_lock(&card_list_lock);
 951         list_for_each_entry(hda, &card_list, list) {
 952                 chip = &hda->chip;
 953                 if (!hda->probe_continued || chip->disabled)
 954                         continue;
 955                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 956         }
 957         mutex_unlock(&card_list_lock);
 958         return 0;
 959 }
 960 
 961 /*
 962  * power management
 963  */
 964 static bool azx_is_pm_ready(struct snd_card *card)
 965 {
 966         struct azx *chip;
 967         struct hda_intel *hda;
 968 
 969         if (!card)
 970                 return false;
 971         chip = card->private_data;
 972         hda = container_of(chip, struct hda_intel, chip);
 973         if (chip->disabled || hda->init_failed || !chip->running)
 974                 return false;
 975         return true;
 976 }
 977 
 978 static void __azx_runtime_suspend(struct azx *chip)
 979 {
 980         azx_stop_chip(chip);
 981         azx_enter_link_reset(chip);
 982         azx_clear_irq_pending(chip);
 983         display_power(chip, false);
 984 }
 985 
 986 static void __azx_runtime_resume(struct azx *chip, bool from_rt)
 987 {
 988         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 989         struct hdac_bus *bus = azx_bus(chip);
 990         struct hda_codec *codec;
 991         int status;
 992 
 993         display_power(chip, true);
 994         if (hda->need_i915_power)
 995                 snd_hdac_i915_set_bclk(bus);
 996 
 997         /* Read STATESTS before controller reset */
 998         status = azx_readw(chip, STATESTS);
 999 
1000         azx_init_pci(chip);
1001         hda_intel_init_chip(chip, true);
1002 
1003         if (status && from_rt) {
1004                 list_for_each_codec(codec, &chip->bus)
1005                         if (status & (1 << codec->addr))
1006                                 schedule_delayed_work(&codec->jackpoll_work,
1007                                                       codec->jackpoll_interval);
1008         }
1009 
1010         /* power down again for link-controlled chips */
1011         if (!hda->need_i915_power)
1012                 display_power(chip, false);
1013 }
1014 
1015 #ifdef CONFIG_PM_SLEEP
1016 static int azx_suspend(struct device *dev)
1017 {
1018         struct snd_card *card = dev_get_drvdata(dev);
1019         struct azx *chip;
1020         struct hdac_bus *bus;
1021 
1022         if (!azx_is_pm_ready(card))
1023                 return 0;
1024 
1025         chip = card->private_data;
1026         bus = azx_bus(chip);
1027         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1028         __azx_runtime_suspend(chip);
1029         if (bus->irq >= 0) {
1030                 free_irq(bus->irq, chip);
1031                 bus->irq = -1;
1032         }
1033 
1034         if (chip->msi)
1035                 pci_disable_msi(chip->pci);
1036 
1037         trace_azx_suspend(chip);
1038         return 0;
1039 }
1040 
1041 static int azx_resume(struct device *dev)
1042 {
1043         struct snd_card *card = dev_get_drvdata(dev);
1044         struct azx *chip;
1045 
1046         if (!azx_is_pm_ready(card))
1047                 return 0;
1048 
1049         chip = card->private_data;
1050         if (chip->msi)
1051                 if (pci_enable_msi(chip->pci) < 0)
1052                         chip->msi = 0;
1053         if (azx_acquire_irq(chip, 1) < 0)
1054                 return -EIO;
1055         __azx_runtime_resume(chip, false);
1056         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1057 
1058         trace_azx_resume(chip);
1059         return 0;
1060 }
1061 
1062 /* put codec down to D3 at hibernation for Intel SKL+;
1063  * otherwise BIOS may still access the codec and screw up the driver
1064  */
1065 static int azx_freeze_noirq(struct device *dev)
1066 {
1067         struct snd_card *card = dev_get_drvdata(dev);
1068         struct azx *chip = card->private_data;
1069         struct pci_dev *pci = to_pci_dev(dev);
1070 
1071         if (!azx_is_pm_ready(card))
1072                 return 0;
1073         if (chip->driver_type == AZX_DRIVER_SKL)
1074                 pci_set_power_state(pci, PCI_D3hot);
1075 
1076         return 0;
1077 }
1078 
1079 static int azx_thaw_noirq(struct device *dev)
1080 {
1081         struct snd_card *card = dev_get_drvdata(dev);
1082         struct azx *chip = card->private_data;
1083         struct pci_dev *pci = to_pci_dev(dev);
1084 
1085         if (!azx_is_pm_ready(card))
1086                 return 0;
1087         if (chip->driver_type == AZX_DRIVER_SKL)
1088                 pci_set_power_state(pci, PCI_D0);
1089 
1090         return 0;
1091 }
1092 #endif /* CONFIG_PM_SLEEP */
1093 
1094 static int azx_runtime_suspend(struct device *dev)
1095 {
1096         struct snd_card *card = dev_get_drvdata(dev);
1097         struct azx *chip;
1098 
1099         if (!azx_is_pm_ready(card))
1100                 return 0;
1101         chip = card->private_data;
1102         if (!azx_has_pm_runtime(chip))
1103                 return 0;
1104 
1105         /* enable controller wake up event */
1106         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1107                   STATESTS_INT_MASK);
1108 
1109         __azx_runtime_suspend(chip);
1110         trace_azx_runtime_suspend(chip);
1111         return 0;
1112 }
1113 
1114 static int azx_runtime_resume(struct device *dev)
1115 {
1116         struct snd_card *card = dev_get_drvdata(dev);
1117         struct azx *chip;
1118 
1119         if (!azx_is_pm_ready(card))
1120                 return 0;
1121         chip = card->private_data;
1122         if (!azx_has_pm_runtime(chip))
1123                 return 0;
1124         __azx_runtime_resume(chip, true);
1125 
1126         /* disable controller Wake Up event*/
1127         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1128                         ~STATESTS_INT_MASK);
1129 
1130         trace_azx_runtime_resume(chip);
1131         return 0;
1132 }
1133 
1134 static int azx_runtime_idle(struct device *dev)
1135 {
1136         struct snd_card *card = dev_get_drvdata(dev);
1137         struct azx *chip;
1138         struct hda_intel *hda;
1139 
1140         if (!card)
1141                 return 0;
1142 
1143         chip = card->private_data;
1144         hda = container_of(chip, struct hda_intel, chip);
1145         if (chip->disabled || hda->init_failed)
1146                 return 0;
1147 
1148         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1149             azx_bus(chip)->codec_powered || !chip->running)
1150                 return -EBUSY;
1151 
1152         /* ELD notification gets broken when HD-audio bus is off */
1153         if (needs_eld_notify_link(chip))
1154                 return -EBUSY;
1155 
1156         return 0;
1157 }
1158 
1159 static const struct dev_pm_ops azx_pm = {
1160         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1161 #ifdef CONFIG_PM_SLEEP
1162         .freeze_noirq = azx_freeze_noirq,
1163         .thaw_noirq = azx_thaw_noirq,
1164 #endif
1165         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1166 };
1167 
1168 #define AZX_PM_OPS      &azx_pm
1169 #else
1170 #define azx_add_card_list(chip) /* NOP */
1171 #define azx_del_card_list(chip) /* NOP */
1172 #define AZX_PM_OPS      NULL
1173 #endif /* CONFIG_PM */
1174 
1175 
1176 static int azx_probe_continue(struct azx *chip);
1177 
1178 #ifdef SUPPORT_VGA_SWITCHEROO
1179 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1180 
1181 static void azx_vs_set_state(struct pci_dev *pci,
1182                              enum vga_switcheroo_state state)
1183 {
1184         struct snd_card *card = pci_get_drvdata(pci);
1185         struct azx *chip = card->private_data;
1186         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1187         struct hda_codec *codec;
1188         bool disabled;
1189 
1190         wait_for_completion(&hda->probe_wait);
1191         if (hda->init_failed)
1192                 return;
1193 
1194         disabled = (state == VGA_SWITCHEROO_OFF);
1195         if (chip->disabled == disabled)
1196                 return;
1197 
1198         if (!hda->probe_continued) {
1199                 chip->disabled = disabled;
1200                 if (!disabled) {
1201                         dev_info(chip->card->dev,
1202                                  "Start delayed initialization\n");
1203                         if (azx_probe_continue(chip) < 0)
1204                                 dev_err(chip->card->dev, "initialization error\n");
1205                 }
1206         } else {
1207                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1208                          disabled ? "Disabling" : "Enabling");
1209                 if (disabled) {
1210                         list_for_each_codec(codec, &chip->bus) {
1211                                 pm_runtime_suspend(hda_codec_dev(codec));
1212                                 pm_runtime_disable(hda_codec_dev(codec));
1213                         }
1214                         pm_runtime_suspend(card->dev);
1215                         pm_runtime_disable(card->dev);
1216                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1217                          * however we have no ACPI handle, so pci/acpi can't put us there,
1218                          * put ourselves there */
1219                         pci->current_state = PCI_D3cold;
1220                         chip->disabled = true;
1221                         if (snd_hda_lock_devices(&chip->bus))
1222                                 dev_warn(chip->card->dev,
1223                                          "Cannot lock devices!\n");
1224                 } else {
1225                         snd_hda_unlock_devices(&chip->bus);
1226                         chip->disabled = false;
1227                         pm_runtime_enable(card->dev);
1228                         list_for_each_codec(codec, &chip->bus) {
1229                                 pm_runtime_enable(hda_codec_dev(codec));
1230                                 pm_runtime_resume(hda_codec_dev(codec));
1231                         }
1232                 }
1233         }
1234 }
1235 
1236 static bool azx_vs_can_switch(struct pci_dev *pci)
1237 {
1238         struct snd_card *card = pci_get_drvdata(pci);
1239         struct azx *chip = card->private_data;
1240         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1241 
1242         wait_for_completion(&hda->probe_wait);
1243         if (hda->init_failed)
1244                 return false;
1245         if (chip->disabled || !hda->probe_continued)
1246                 return true;
1247         if (snd_hda_lock_devices(&chip->bus))
1248                 return false;
1249         snd_hda_unlock_devices(&chip->bus);
1250         return true;
1251 }
1252 
1253 /*
1254  * The discrete GPU cannot power down unless the HDA controller runtime
1255  * suspends, so activate runtime PM on codecs even if power_save == 0.
1256  */
1257 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1258 {
1259         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1260         struct hda_codec *codec;
1261 
1262         if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
1263                 list_for_each_codec(codec, &chip->bus)
1264                         codec->auto_runtime_pm = 1;
1265                 /* reset the power save setup */
1266                 if (chip->running)
1267                         set_default_power_save(chip);
1268         }
1269 }
1270 
1271 static void azx_vs_gpu_bound(struct pci_dev *pci,
1272                              enum vga_switcheroo_client_id client_id)
1273 {
1274         struct snd_card *card = pci_get_drvdata(pci);
1275         struct azx *chip = card->private_data;
1276 
1277         if (client_id == VGA_SWITCHEROO_DIS)
1278                 chip->bus.keep_power = 0;
1279         setup_vga_switcheroo_runtime_pm(chip);
1280 }
1281 
1282 static void init_vga_switcheroo(struct azx *chip)
1283 {
1284         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1285         struct pci_dev *p = get_bound_vga(chip->pci);
1286         struct pci_dev *parent;
1287         if (p) {
1288                 dev_info(chip->card->dev,
1289                          "Handle vga_switcheroo audio client\n");
1290                 hda->use_vga_switcheroo = 1;
1291 
1292                 /* cleared in either gpu_bound op or codec probe, or when its
1293                  * upstream port has _PR3 (i.e. dGPU).
1294                  */
1295                 parent = pci_upstream_bridge(p);
1296                 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
1297                 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1298                 pci_dev_put(p);
1299         }
1300 }
1301 
1302 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1303         .set_gpu_state = azx_vs_set_state,
1304         .can_switch = azx_vs_can_switch,
1305         .gpu_bound = azx_vs_gpu_bound,
1306 };
1307 
1308 static int register_vga_switcheroo(struct azx *chip)
1309 {
1310         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1311         struct pci_dev *p;
1312         int err;
1313 
1314         if (!hda->use_vga_switcheroo)
1315                 return 0;
1316 
1317         p = get_bound_vga(chip->pci);
1318         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1319         pci_dev_put(p);
1320 
1321         if (err < 0)
1322                 return err;
1323         hda->vga_switcheroo_registered = 1;
1324 
1325         return 0;
1326 }
1327 #else
1328 #define init_vga_switcheroo(chip)               /* NOP */
1329 #define register_vga_switcheroo(chip)           0
1330 #define check_hdmi_disabled(pci)        false
1331 #define setup_vga_switcheroo_runtime_pm(chip)   /* NOP */
1332 #endif /* SUPPORT_VGA_SWITCHER */
1333 
1334 /*
1335  * destructor
1336  */
1337 static void azx_free(struct azx *chip)
1338 {
1339         struct pci_dev *pci = chip->pci;
1340         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1341         struct hdac_bus *bus = azx_bus(chip);
1342 
1343         if (hda->freed)
1344                 return;
1345 
1346         if (azx_has_pm_runtime(chip) && chip->running)
1347                 pm_runtime_get_noresume(&pci->dev);
1348         chip->running = 0;
1349 
1350         azx_del_card_list(chip);
1351 
1352         hda->init_failed = 1; /* to be sure */
1353         complete_all(&hda->probe_wait);
1354 
1355         if (use_vga_switcheroo(hda)) {
1356                 if (chip->disabled && hda->probe_continued)
1357                         snd_hda_unlock_devices(&chip->bus);
1358                 if (hda->vga_switcheroo_registered)
1359                         vga_switcheroo_unregister_client(chip->pci);
1360         }
1361 
1362         if (bus->chip_init) {
1363                 azx_clear_irq_pending(chip);
1364                 azx_stop_all_streams(chip);
1365                 azx_stop_chip(chip);
1366         }
1367 
1368         if (bus->irq >= 0)
1369                 free_irq(bus->irq, (void*)chip);
1370         if (chip->msi)
1371                 pci_disable_msi(chip->pci);
1372         iounmap(bus->remap_addr);
1373 
1374         azx_free_stream_pages(chip);
1375         azx_free_streams(chip);
1376         snd_hdac_bus_exit(bus);
1377 
1378         if (chip->region_requested)
1379                 pci_release_regions(chip->pci);
1380 
1381         pci_disable_device(chip->pci);
1382 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1383         release_firmware(chip->fw);
1384 #endif
1385         display_power(chip, false);
1386 
1387         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1388                 snd_hdac_i915_exit(bus);
1389 
1390         hda->freed = 1;
1391 }
1392 
1393 static int azx_dev_disconnect(struct snd_device *device)
1394 {
1395         struct azx *chip = device->device_data;
1396         struct hdac_bus *bus = azx_bus(chip);
1397 
1398         chip->bus.shutdown = 1;
1399         cancel_work_sync(&bus->unsol_work);
1400 
1401         return 0;
1402 }
1403 
1404 static int azx_dev_free(struct snd_device *device)
1405 {
1406         azx_free(device->device_data);
1407         return 0;
1408 }
1409 
1410 #ifdef SUPPORT_VGA_SWITCHEROO
1411 /*
1412  * Check of disabled HDMI controller by vga_switcheroo
1413  */
1414 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1415 {
1416         struct pci_dev *p;
1417 
1418         /* check only discrete GPU */
1419         switch (pci->vendor) {
1420         case PCI_VENDOR_ID_ATI:
1421         case PCI_VENDOR_ID_AMD:
1422         case PCI_VENDOR_ID_NVIDIA:
1423                 if (pci->devfn == 1) {
1424                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1425                                                         pci->bus->number, 0);
1426                         if (p) {
1427                                 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1428                                         return p;
1429                                 pci_dev_put(p);
1430                         }
1431                 }
1432                 break;
1433         }
1434         return NULL;
1435 }
1436 
1437 static bool check_hdmi_disabled(struct pci_dev *pci)
1438 {
1439         bool vga_inactive = false;
1440         struct pci_dev *p = get_bound_vga(pci);
1441 
1442         if (p) {
1443                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1444                         vga_inactive = true;
1445                 pci_dev_put(p);
1446         }
1447         return vga_inactive;
1448 }
1449 #endif /* SUPPORT_VGA_SWITCHEROO */
1450 
1451 /*
1452  * white/black-listing for position_fix
1453  */
1454 static struct snd_pci_quirk position_fix_list[] = {
1455         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1456         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1457         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1458         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1459         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1460         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1461         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1462         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1463         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1464         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1465         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1466         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1467         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1468         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1469         {}
1470 };
1471 
1472 static int check_position_fix(struct azx *chip, int fix)
1473 {
1474         const struct snd_pci_quirk *q;
1475 
1476         switch (fix) {
1477         case POS_FIX_AUTO:
1478         case POS_FIX_LPIB:
1479         case POS_FIX_POSBUF:
1480         case POS_FIX_VIACOMBO:
1481         case POS_FIX_COMBO:
1482         case POS_FIX_SKL:
1483         case POS_FIX_FIFO:
1484                 return fix;
1485         }
1486 
1487         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1488         if (q) {
1489                 dev_info(chip->card->dev,
1490                          "position_fix set to %d for device %04x:%04x\n",
1491                          q->value, q->subvendor, q->subdevice);
1492                 return q->value;
1493         }
1494 
1495         /* Check VIA/ATI HD Audio Controller exist */
1496         if (chip->driver_type == AZX_DRIVER_VIA) {
1497                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1498                 return POS_FIX_VIACOMBO;
1499         }
1500         if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1501                 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1502                 return POS_FIX_FIFO;
1503         }
1504         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1505                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1506                 return POS_FIX_LPIB;
1507         }
1508         if (chip->driver_type == AZX_DRIVER_SKL) {
1509                 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1510                 return POS_FIX_SKL;
1511         }
1512         return POS_FIX_AUTO;
1513 }
1514 
1515 static void assign_position_fix(struct azx *chip, int fix)
1516 {
1517         static azx_get_pos_callback_t callbacks[] = {
1518                 [POS_FIX_AUTO] = NULL,
1519                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1520                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1521                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1522                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1523                 [POS_FIX_SKL] = azx_get_pos_skl,
1524                 [POS_FIX_FIFO] = azx_get_pos_fifo,
1525         };
1526 
1527         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1528 
1529         /* combo mode uses LPIB only for playback */
1530         if (fix == POS_FIX_COMBO)
1531                 chip->get_position[1] = NULL;
1532 
1533         if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1534             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1535                 chip->get_delay[0] = chip->get_delay[1] =
1536                         azx_get_delay_from_lpib;
1537         }
1538 
1539         if (fix == POS_FIX_FIFO)
1540                 chip->get_delay[0] = chip->get_delay[1] =
1541                         azx_get_delay_from_fifo;
1542 }
1543 
1544 /*
1545  * black-lists for probe_mask
1546  */
1547 static struct snd_pci_quirk probe_mask_list[] = {
1548         /* Thinkpad often breaks the controller communication when accessing
1549          * to the non-working (or non-existing) modem codec slot.
1550          */
1551         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1552         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1553         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1554         /* broken BIOS */
1555         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1556         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1557         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1558         /* forced codec slots */
1559         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1560         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1561         /* WinFast VP200 H (Teradici) user reported broken communication */
1562         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1563         {}
1564 };
1565 
1566 #define AZX_FORCE_CODEC_MASK    0x100
1567 
1568 static void check_probe_mask(struct azx *chip, int dev)
1569 {
1570         const struct snd_pci_quirk *q;
1571 
1572         chip->codec_probe_mask = probe_mask[dev];
1573         if (chip->codec_probe_mask == -1) {
1574                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1575                 if (q) {
1576                         dev_info(chip->card->dev,
1577                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1578                                  q->value, q->subvendor, q->subdevice);
1579                         chip->codec_probe_mask = q->value;
1580                 }
1581         }
1582 
1583         /* check forced option */
1584         if (chip->codec_probe_mask != -1 &&
1585             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1586                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1587                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1588                          (int)azx_bus(chip)->codec_mask);
1589         }
1590 }
1591 
1592 /*
1593  * white/black-list for enable_msi
1594  */
1595 static struct snd_pci_quirk msi_black_list[] = {
1596         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1597         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1598         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1599         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1600         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1601         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1602         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1603         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1604         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1605         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1606         {}
1607 };
1608 
1609 static void check_msi(struct azx *chip)
1610 {
1611         const struct snd_pci_quirk *q;
1612 
1613         if (enable_msi >= 0) {
1614                 chip->msi = !!enable_msi;
1615                 return;
1616         }
1617         chip->msi = 1;  /* enable MSI as default */
1618         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1619         if (q) {
1620                 dev_info(chip->card->dev,
1621                          "msi for device %04x:%04x set to %d\n",
1622                          q->subvendor, q->subdevice, q->value);
1623                 chip->msi = q->value;
1624                 return;
1625         }
1626 
1627         /* NVidia chipsets seem to cause troubles with MSI */
1628         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1629                 dev_info(chip->card->dev, "Disabling MSI\n");
1630                 chip->msi = 0;
1631         }
1632 }
1633 
1634 /* check the snoop mode availability */
1635 static void azx_check_snoop_available(struct azx *chip)
1636 {
1637         int snoop = hda_snoop;
1638 
1639         if (snoop >= 0) {
1640                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1641                          snoop ? "snoop" : "non-snoop");
1642                 chip->snoop = snoop;
1643                 chip->uc_buffer = !snoop;
1644                 return;
1645         }
1646 
1647         snoop = true;
1648         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1649             chip->driver_type == AZX_DRIVER_VIA) {
1650                 /* force to non-snoop mode for a new VIA controller
1651                  * when BIOS is set
1652                  */
1653                 u8 val;
1654                 pci_read_config_byte(chip->pci, 0x42, &val);
1655                 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1656                                       chip->pci->revision == 0x20))
1657                         snoop = false;
1658         }
1659 
1660         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1661                 snoop = false;
1662 
1663         chip->snoop = snoop;
1664         if (!snoop) {
1665                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1666                 /* C-Media requires non-cached pages only for CORB/RIRB */
1667                 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1668                         chip->uc_buffer = true;
1669         }
1670 }
1671 
1672 static void azx_probe_work(struct work_struct *work)
1673 {
1674         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1675         azx_probe_continue(&hda->chip);
1676 }
1677 
1678 static int default_bdl_pos_adj(struct azx *chip)
1679 {
1680         /* some exceptions: Atoms seem problematic with value 1 */
1681         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1682                 switch (chip->pci->device) {
1683                 case 0x0f04: /* Baytrail */
1684                 case 0x2284: /* Braswell */
1685                         return 32;
1686                 }
1687         }
1688 
1689         switch (chip->driver_type) {
1690         case AZX_DRIVER_ICH:
1691         case AZX_DRIVER_PCH:
1692                 return 1;
1693         default:
1694                 return 32;
1695         }
1696 }
1697 
1698 /*
1699  * constructor
1700  */
1701 static const struct hda_controller_ops pci_hda_ops;
1702 
1703 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1704                       int dev, unsigned int driver_caps,
1705                       struct azx **rchip)
1706 {
1707         static struct snd_device_ops ops = {
1708                 .dev_disconnect = azx_dev_disconnect,
1709                 .dev_free = azx_dev_free,
1710         };
1711         struct hda_intel *hda;
1712         struct azx *chip;
1713         int err;
1714 
1715         *rchip = NULL;
1716 
1717         err = pci_enable_device(pci);
1718         if (err < 0)
1719                 return err;
1720 
1721         hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);
1722         if (!hda) {
1723                 pci_disable_device(pci);
1724                 return -ENOMEM;
1725         }
1726 
1727         chip = &hda->chip;
1728         mutex_init(&chip->open_mutex);
1729         chip->card = card;
1730         chip->pci = pci;
1731         chip->ops = &pci_hda_ops;
1732         chip->driver_caps = driver_caps;
1733         chip->driver_type = driver_caps & 0xff;
1734         check_msi(chip);
1735         chip->dev_index = dev;
1736         if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1737                 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1738         INIT_LIST_HEAD(&chip->pcm_list);
1739         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1740         INIT_LIST_HEAD(&hda->list);
1741         init_vga_switcheroo(chip);
1742         init_completion(&hda->probe_wait);
1743 
1744         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1745 
1746         check_probe_mask(chip, dev);
1747 
1748         if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1749                 chip->fallback_to_single_cmd = 1;
1750         else /* explicitly set to single_cmd or not */
1751                 chip->single_cmd = single_cmd;
1752 
1753         azx_check_snoop_available(chip);
1754 
1755         if (bdl_pos_adj[dev] < 0)
1756                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1757         else
1758                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1759 
1760         err = azx_bus_init(chip, model[dev]);
1761         if (err < 0) {
1762                 pci_disable_device(pci);
1763                 return err;
1764         }
1765 
1766         /* use the non-cached pages in non-snoop mode */
1767         if (!azx_snoop(chip))
1768                 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC;
1769 
1770         /* Workaround for a communication error on CFL (bko#199007) and CNL */
1771         if (IS_CFL(pci) || IS_CNL(pci))
1772                 azx_bus(chip)->polling_mode = 1;
1773 
1774         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1775                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1776                 chip->bus.needs_damn_long_delay = 1;
1777         }
1778 
1779         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1780         if (err < 0) {
1781                 dev_err(card->dev, "Error creating device [card]!\n");
1782                 azx_free(chip);
1783                 return err;
1784         }
1785 
1786         /* continue probing in work context as may trigger request module */
1787         INIT_WORK(&hda->probe_work, azx_probe_work);
1788 
1789         *rchip = chip;
1790 
1791         return 0;
1792 }
1793 
1794 static int azx_first_init(struct azx *chip)
1795 {
1796         int dev = chip->dev_index;
1797         struct pci_dev *pci = chip->pci;
1798         struct snd_card *card = chip->card;
1799         struct hdac_bus *bus = azx_bus(chip);
1800         int err;
1801         unsigned short gcap;
1802         unsigned int dma_bits = 64;
1803 
1804 #if BITS_PER_LONG != 64
1805         /* Fix up base address on ULI M5461 */
1806         if (chip->driver_type == AZX_DRIVER_ULI) {
1807                 u16 tmp3;
1808                 pci_read_config_word(pci, 0x40, &tmp3);
1809                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1810                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1811         }
1812 #endif
1813 
1814         err = pci_request_regions(pci, "ICH HD audio");
1815         if (err < 0)
1816                 return err;
1817         chip->region_requested = 1;
1818 
1819         bus->addr = pci_resource_start(pci, 0);
1820         bus->remap_addr = pci_ioremap_bar(pci, 0);
1821         if (bus->remap_addr == NULL) {
1822                 dev_err(card->dev, "ioremap error\n");
1823                 return -ENXIO;
1824         }
1825 
1826         if (chip->driver_type == AZX_DRIVER_SKL)
1827                 snd_hdac_bus_parse_capabilities(bus);
1828 
1829         /*
1830          * Some Intel CPUs has always running timer (ART) feature and
1831          * controller may have Global time sync reporting capability, so
1832          * check both of these before declaring synchronized time reporting
1833          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1834          */
1835         chip->gts_present = false;
1836 
1837 #ifdef CONFIG_X86
1838         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1839                 chip->gts_present = true;
1840 #endif
1841 
1842         if (chip->msi) {
1843                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1844                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1845                         pci->no_64bit_msi = true;
1846                 }
1847                 if (pci_enable_msi(pci) < 0)
1848                         chip->msi = 0;
1849         }
1850 
1851         pci_set_master(pci);
1852         synchronize_irq(bus->irq);
1853 
1854         gcap = azx_readw(chip, GCAP);
1855         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1856 
1857         /* AMD devices support 40 or 48bit DMA, take the safe one */
1858         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1859                 dma_bits = 40;
1860 
1861         /* disable SB600 64bit support for safety */
1862         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1863                 struct pci_dev *p_smbus;
1864                 dma_bits = 40;
1865                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1866                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1867                                          NULL);
1868                 if (p_smbus) {
1869                         if (p_smbus->revision < 0x30)
1870                                 gcap &= ~AZX_GCAP_64OK;
1871                         pci_dev_put(p_smbus);
1872                 }
1873         }
1874 
1875         /* NVidia hardware normally only supports up to 40 bits of DMA */
1876         if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1877                 dma_bits = 40;
1878 
1879         /* disable 64bit DMA address on some devices */
1880         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1881                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1882                 gcap &= ~AZX_GCAP_64OK;
1883         }
1884 
1885         /* disable buffer size rounding to 128-byte multiples if supported */
1886         if (align_buffer_size >= 0)
1887                 chip->align_buffer_size = !!align_buffer_size;
1888         else {
1889                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1890                         chip->align_buffer_size = 0;
1891                 else
1892                         chip->align_buffer_size = 1;
1893         }
1894 
1895         /* allow 64bit DMA address if supported by H/W */
1896         if (!(gcap & AZX_GCAP_64OK))
1897                 dma_bits = 32;
1898         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1899                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1900         } else {
1901                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1902                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1903         }
1904 
1905         /* read number of streams from GCAP register instead of using
1906          * hardcoded value
1907          */
1908         chip->capture_streams = (gcap >> 8) & 0x0f;
1909         chip->playback_streams = (gcap >> 12) & 0x0f;
1910         if (!chip->playback_streams && !chip->capture_streams) {
1911                 /* gcap didn't give any info, switching to old method */
1912 
1913                 switch (chip->driver_type) {
1914                 case AZX_DRIVER_ULI:
1915                         chip->playback_streams = ULI_NUM_PLAYBACK;
1916                         chip->capture_streams = ULI_NUM_CAPTURE;
1917                         break;
1918                 case AZX_DRIVER_ATIHDMI:
1919                 case AZX_DRIVER_ATIHDMI_NS:
1920                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1921                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1922                         break;
1923                 case AZX_DRIVER_GENERIC:
1924                 default:
1925                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1926                         chip->capture_streams = ICH6_NUM_CAPTURE;
1927                         break;
1928                 }
1929         }
1930         chip->capture_index_offset = 0;
1931         chip->playback_index_offset = chip->capture_streams;
1932         chip->num_streams = chip->playback_streams + chip->capture_streams;
1933 
1934         /* sanity check for the SDxCTL.STRM field overflow */
1935         if (chip->num_streams > 15 &&
1936             (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1937                 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1938                          "forcing separate stream tags", chip->num_streams);
1939                 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1940         }
1941 
1942         /* initialize streams */
1943         err = azx_init_streams(chip);
1944         if (err < 0)
1945                 return err;
1946 
1947         err = azx_alloc_stream_pages(chip);
1948         if (err < 0)
1949                 return err;
1950 
1951         /* initialize chip */
1952         azx_init_pci(chip);
1953 
1954         snd_hdac_i915_set_bclk(bus);
1955 
1956         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1957 
1958         /* codec detection */
1959         if (!azx_bus(chip)->codec_mask) {
1960                 dev_err(card->dev, "no codecs found!\n");
1961                 /* keep running the rest for the runtime PM */
1962         }
1963 
1964         if (azx_acquire_irq(chip, 0) < 0)
1965                 return -EBUSY;
1966 
1967         strcpy(card->driver, "HDA-Intel");
1968         strlcpy(card->shortname, driver_short_names[chip->driver_type],
1969                 sizeof(card->shortname));
1970         snprintf(card->longname, sizeof(card->longname),
1971                  "%s at 0x%lx irq %i",
1972                  card->shortname, bus->addr, bus->irq);
1973 
1974         return 0;
1975 }
1976 
1977 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1978 /* callback from request_firmware_nowait() */
1979 static void azx_firmware_cb(const struct firmware *fw, void *context)
1980 {
1981         struct snd_card *card = context;
1982         struct azx *chip = card->private_data;
1983 
1984         if (fw)
1985                 chip->fw = fw;
1986         else
1987                 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
1988         if (!chip->disabled) {
1989                 /* continue probing */
1990                 azx_probe_continue(chip);
1991         }
1992 }
1993 #endif
1994 
1995 static int disable_msi_reset_irq(struct azx *chip)
1996 {
1997         struct hdac_bus *bus = azx_bus(chip);
1998         int err;
1999 
2000         free_irq(bus->irq, chip);
2001         bus->irq = -1;
2002         pci_disable_msi(chip->pci);
2003         chip->msi = 0;
2004         err = azx_acquire_irq(chip, 1);
2005         if (err < 0)
2006                 return err;
2007 
2008         return 0;
2009 }
2010 
2011 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2012                              struct vm_area_struct *area)
2013 {
2014 #ifdef CONFIG_X86
2015         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2016         struct azx *chip = apcm->chip;
2017         if (chip->uc_buffer)
2018                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2019 #endif
2020 }
2021 
2022 /* Blacklist for skipping the whole probe:
2023  * some HD-audio PCI entries are exposed without any codecs, and such devices
2024  * should be ignored from the beginning.
2025  */
2026 static const struct pci_device_id driver_blacklist[] = {
2027         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2028         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2029         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
2030         {}
2031 };
2032 
2033 static const struct hda_controller_ops pci_hda_ops = {
2034         .disable_msi_reset_irq = disable_msi_reset_irq,
2035         .pcm_mmap_prepare = pcm_mmap_prepare,
2036         .position_check = azx_position_check,
2037 };
2038 
2039 static int azx_check_dmic(struct pci_dev *pci, struct azx *chip)
2040 {
2041         struct nhlt_acpi_table *nhlt;
2042         int ret = 0;
2043 
2044         if (chip->driver_type == AZX_DRIVER_SKL &&
2045             pci->class != 0x040300) {
2046                 nhlt = intel_nhlt_init(&pci->dev);
2047                 if (nhlt) {
2048                         if (intel_nhlt_get_dmic_geo(&pci->dev, nhlt)) {
2049                                 ret = -ENODEV;
2050                                 dev_info(&pci->dev, "Digital mics found on Skylake+ platform, aborting probe\n");
2051                         }
2052                         intel_nhlt_free(nhlt);
2053                 }
2054         }
2055         return ret;
2056 }
2057 
2058 static int azx_probe(struct pci_dev *pci,
2059                      const struct pci_device_id *pci_id)
2060 {
2061         static int dev;
2062         struct snd_card *card;
2063         struct hda_intel *hda;
2064         struct azx *chip;
2065         bool schedule_probe;
2066         int err;
2067 
2068         if (pci_match_id(driver_blacklist, pci)) {
2069                 dev_info(&pci->dev, "Skipping the blacklisted device\n");
2070                 return -ENODEV;
2071         }
2072 
2073         if (dev >= SNDRV_CARDS)
2074                 return -ENODEV;
2075         if (!enable[dev]) {
2076                 dev++;
2077                 return -ENOENT;
2078         }
2079 
2080         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2081                            0, &card);
2082         if (err < 0) {
2083                 dev_err(&pci->dev, "Error creating card!\n");
2084                 return err;
2085         }
2086 
2087         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2088         if (err < 0)
2089                 goto out_free;
2090         card->private_data = chip;
2091         hda = container_of(chip, struct hda_intel, chip);
2092 
2093         /*
2094          * stop probe if digital microphones detected on Skylake+ platform
2095          * with the DSP enabled. This is an opt-in behavior defined at build
2096          * time or at run-time with a module parameter
2097          */
2098         if (dmic_detect) {
2099                 err = azx_check_dmic(pci, chip);
2100                 if (err < 0)
2101                         goto out_free;
2102         }
2103 
2104         pci_set_drvdata(pci, card);
2105 
2106         err = register_vga_switcheroo(chip);
2107         if (err < 0) {
2108                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2109                 goto out_free;
2110         }
2111 
2112         if (check_hdmi_disabled(pci)) {
2113                 dev_info(card->dev, "VGA controller is disabled\n");
2114                 dev_info(card->dev, "Delaying initialization\n");
2115                 chip->disabled = true;
2116         }
2117 
2118         schedule_probe = !chip->disabled;
2119 
2120 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2121         if (patch[dev] && *patch[dev]) {
2122                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2123                          patch[dev]);
2124                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2125                                               &pci->dev, GFP_KERNEL, card,
2126                                               azx_firmware_cb);
2127                 if (err < 0)
2128                         goto out_free;
2129                 schedule_probe = false; /* continued in azx_firmware_cb() */
2130         }
2131 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2132 
2133 #ifndef CONFIG_SND_HDA_I915
2134         if (CONTROLLER_IN_GPU(pci))
2135                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2136 #endif
2137 
2138         if (schedule_probe)
2139                 schedule_work(&hda->probe_work);
2140 
2141         dev++;
2142         if (chip->disabled)
2143                 complete_all(&hda->probe_wait);
2144         return 0;
2145 
2146 out_free:
2147         snd_card_free(card);
2148         return err;
2149 }
2150 
2151 #ifdef CONFIG_PM
2152 /* On some boards setting power_save to a non 0 value leads to clicking /
2153  * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2154  * figure out how to avoid these sounds, but that is not always feasible.
2155  * So we keep a list of devices where we disable powersaving as its known
2156  * to causes problems on these devices.
2157  */
2158 static struct snd_pci_quirk power_save_blacklist[] = {
2159         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2160         SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2161         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2162         SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2163         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2164         SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2165         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2166         SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2167         /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */
2168         SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0),
2169         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2170         SND_PCI_QUIRK(0x1558, 0x6504, "Clevo W65_67SB", 0),
2171         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2172         SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2173         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2174         /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2175         SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2176         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2177         SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2178         /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2179         SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2180         /* https://bugs.launchpad.net/bugs/1821663 */
2181         SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2182         /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2183         SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2184         /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2185         SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2186         /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2187         SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2188         /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2189         SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2190         /* https://bugs.launchpad.net/bugs/1821663 */
2191         SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2192         {}
2193 };
2194 #endif /* CONFIG_PM */
2195 
2196 static void set_default_power_save(struct azx *chip)
2197 {
2198         int val = power_save;
2199 
2200 #ifdef CONFIG_PM
2201         if (pm_blacklist) {
2202                 const struct snd_pci_quirk *q;
2203 
2204                 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2205                 if (q && val) {
2206                         dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2207                                  q->subvendor, q->subdevice);
2208                         val = 0;
2209                 }
2210         }
2211 #endif /* CONFIG_PM */
2212         snd_hda_set_power_save(&chip->bus, val * 1000);
2213 }
2214 
2215 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2216 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2217         [AZX_DRIVER_NVIDIA] = 8,
2218         [AZX_DRIVER_TERA] = 1,
2219 };
2220 
2221 static int azx_probe_continue(struct azx *chip)
2222 {
2223         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2224         struct hdac_bus *bus = azx_bus(chip);
2225         struct pci_dev *pci = chip->pci;
2226         int dev = chip->dev_index;
2227         int err;
2228 
2229         to_hda_bus(bus)->bus_probing = 1;
2230         hda->probe_continued = 1;
2231 
2232         /* bind with i915 if needed */
2233         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2234                 err = snd_hdac_i915_init(bus);
2235                 if (err < 0) {
2236                         /* if the controller is bound only with HDMI/DP
2237                          * (for HSW and BDW), we need to abort the probe;
2238                          * for other chips, still continue probing as other
2239                          * codecs can be on the same link.
2240                          */
2241                         if (CONTROLLER_IN_GPU(pci)) {
2242                                 dev_err(chip->card->dev,
2243                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2244                                 goto out_free;
2245                         } else {
2246                                 /* don't bother any longer */
2247                                 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2248                         }
2249                 }
2250 
2251                 /* HSW/BDW controllers need this power */
2252                 if (CONTROLLER_IN_GPU(pci))
2253                         hda->need_i915_power = 1;
2254         }
2255 
2256         /* Request display power well for the HDA controller or codec. For
2257          * Haswell/Broadwell, both the display HDA controller and codec need
2258          * this power. For other platforms, like Baytrail/Braswell, only the
2259          * display codec needs the power and it can be released after probe.
2260          */
2261         display_power(chip, true);
2262 
2263         err = azx_first_init(chip);
2264         if (err < 0)
2265                 goto out_free;
2266 
2267 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2268         chip->beep_mode = beep_mode[dev];
2269 #endif
2270 
2271         /* create codec instances */
2272         if (bus->codec_mask) {
2273                 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2274                 if (err < 0)
2275                         goto out_free;
2276         }
2277 
2278 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2279         if (chip->fw) {
2280                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2281                                          chip->fw->data);
2282                 if (err < 0)
2283                         goto out_free;
2284 #ifndef CONFIG_PM
2285                 release_firmware(chip->fw); /* no longer needed */
2286                 chip->fw = NULL;
2287 #endif
2288         }
2289 #endif
2290         if (bus->codec_mask && !(probe_only[dev] & 1)) {
2291                 err = azx_codec_configure(chip);
2292                 if (err < 0)
2293                         goto out_free;
2294         }
2295 
2296         err = snd_card_register(chip->card);
2297         if (err < 0)
2298                 goto out_free;
2299 
2300         setup_vga_switcheroo_runtime_pm(chip);
2301 
2302         chip->running = 1;
2303         azx_add_card_list(chip);
2304 
2305         set_default_power_save(chip);
2306 
2307         if (azx_has_pm_runtime(chip)) {
2308                 pm_runtime_use_autosuspend(&pci->dev);
2309                 pm_runtime_allow(&pci->dev);
2310                 pm_runtime_put_autosuspend(&pci->dev);
2311         }
2312 
2313 out_free:
2314         if (err < 0) {
2315                 azx_free(chip);
2316                 return err;
2317         }
2318 
2319         if (!hda->need_i915_power)
2320                 display_power(chip, false);
2321         complete_all(&hda->probe_wait);
2322         to_hda_bus(bus)->bus_probing = 0;
2323         return 0;
2324 }
2325 
2326 static void azx_remove(struct pci_dev *pci)
2327 {
2328         struct snd_card *card = pci_get_drvdata(pci);
2329         struct azx *chip;
2330         struct hda_intel *hda;
2331 
2332         if (card) {
2333                 /* cancel the pending probing work */
2334                 chip = card->private_data;
2335                 hda = container_of(chip, struct hda_intel, chip);
2336                 /* FIXME: below is an ugly workaround.
2337                  * Both device_release_driver() and driver_probe_device()
2338                  * take *both* the device's and its parent's lock before
2339                  * calling the remove() and probe() callbacks.  The codec
2340                  * probe takes the locks of both the codec itself and its
2341                  * parent, i.e. the PCI controller dev.  Meanwhile, when
2342                  * the PCI controller is unbound, it takes its lock, too
2343                  * ==> ouch, a deadlock!
2344                  * As a workaround, we unlock temporarily here the controller
2345                  * device during cancel_work_sync() call.
2346                  */
2347                 device_unlock(&pci->dev);
2348                 cancel_work_sync(&hda->probe_work);
2349                 device_lock(&pci->dev);
2350 
2351                 snd_card_free(card);
2352         }
2353 }
2354 
2355 static void azx_shutdown(struct pci_dev *pci)
2356 {
2357         struct snd_card *card = pci_get_drvdata(pci);
2358         struct azx *chip;
2359 
2360         if (!card)
2361                 return;
2362         chip = card->private_data;
2363         if (chip && chip->running)
2364                 azx_stop_chip(chip);
2365 }
2366 
2367 /* PCI IDs */
2368 static const struct pci_device_id azx_ids[] = {
2369         /* CPT */
2370         { PCI_DEVICE(0x8086, 0x1c20),
2371           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2372         /* PBG */
2373         { PCI_DEVICE(0x8086, 0x1d20),
2374           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2375         /* Panther Point */
2376         { PCI_DEVICE(0x8086, 0x1e20),
2377           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2378         /* Lynx Point */
2379         { PCI_DEVICE(0x8086, 0x8c20),
2380           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2381         /* 9 Series */
2382         { PCI_DEVICE(0x8086, 0x8ca0),
2383           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2384         /* Wellsburg */
2385         { PCI_DEVICE(0x8086, 0x8d20),
2386           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2387         { PCI_DEVICE(0x8086, 0x8d21),
2388           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2389         /* Lewisburg */
2390         { PCI_DEVICE(0x8086, 0xa1f0),
2391           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2392         { PCI_DEVICE(0x8086, 0xa270),
2393           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2394         /* Lynx Point-LP */
2395         { PCI_DEVICE(0x8086, 0x9c20),
2396           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2397         /* Lynx Point-LP */
2398         { PCI_DEVICE(0x8086, 0x9c21),
2399           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2400         /* Wildcat Point-LP */
2401         { PCI_DEVICE(0x8086, 0x9ca0),
2402           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2403         /* Sunrise Point */
2404         { PCI_DEVICE(0x8086, 0xa170),
2405           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2406         /* Sunrise Point-LP */
2407         { PCI_DEVICE(0x8086, 0x9d70),
2408           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2409         /* Kabylake */
2410         { PCI_DEVICE(0x8086, 0xa171),
2411           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2412         /* Kabylake-LP */
2413         { PCI_DEVICE(0x8086, 0x9d71),
2414           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2415         /* Kabylake-H */
2416         { PCI_DEVICE(0x8086, 0xa2f0),
2417           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2418         /* Coffelake */
2419         { PCI_DEVICE(0x8086, 0xa348),
2420           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2421         /* Cannonlake */
2422         { PCI_DEVICE(0x8086, 0x9dc8),
2423           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2424         /* CometLake-LP */
2425         { PCI_DEVICE(0x8086, 0x02C8),
2426           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2427         /* CometLake-H */
2428         { PCI_DEVICE(0x8086, 0x06C8),
2429           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2430         /* CometLake-S */
2431         { PCI_DEVICE(0x8086, 0xa3f0),
2432           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2433         /* Icelake */
2434         { PCI_DEVICE(0x8086, 0x34c8),
2435           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2436         /* Jasperlake */
2437         { PCI_DEVICE(0x8086, 0x38c8),
2438           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2439         { PCI_DEVICE(0x8086, 0x4dc8),
2440           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2441         /* Tigerlake */
2442         { PCI_DEVICE(0x8086, 0xa0c8),
2443           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2444         /* Elkhart Lake */
2445         { PCI_DEVICE(0x8086, 0x4b55),
2446           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2447         /* Broxton-P(Apollolake) */
2448         { PCI_DEVICE(0x8086, 0x5a98),
2449           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2450         /* Broxton-T */
2451         { PCI_DEVICE(0x8086, 0x1a98),
2452           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2453         /* Gemini-Lake */
2454         { PCI_DEVICE(0x8086, 0x3198),
2455           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2456         /* Haswell */
2457         { PCI_DEVICE(0x8086, 0x0a0c),
2458           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2459         { PCI_DEVICE(0x8086, 0x0c0c),
2460           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2461         { PCI_DEVICE(0x8086, 0x0d0c),
2462           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2463         /* Broadwell */
2464         { PCI_DEVICE(0x8086, 0x160c),
2465           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2466         /* 5 Series/3400 */
2467         { PCI_DEVICE(0x8086, 0x3b56),
2468           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2469         /* Poulsbo */
2470         { PCI_DEVICE(0x8086, 0x811b),
2471           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2472         /* Oaktrail */
2473         { PCI_DEVICE(0x8086, 0x080a),
2474           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2475         /* BayTrail */
2476         { PCI_DEVICE(0x8086, 0x0f04),
2477           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2478         /* Braswell */
2479         { PCI_DEVICE(0x8086, 0x2284),
2480           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2481         /* ICH6 */
2482         { PCI_DEVICE(0x8086, 0x2668),
2483           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2484         /* ICH7 */
2485         { PCI_DEVICE(0x8086, 0x27d8),
2486           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2487         /* ESB2 */
2488         { PCI_DEVICE(0x8086, 0x269a),
2489           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2490         /* ICH8 */
2491         { PCI_DEVICE(0x8086, 0x284b),
2492           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2493         /* ICH9 */
2494         { PCI_DEVICE(0x8086, 0x293e),
2495           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2496         /* ICH9 */
2497         { PCI_DEVICE(0x8086, 0x293f),
2498           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2499         /* ICH10 */
2500         { PCI_DEVICE(0x8086, 0x3a3e),
2501           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2502         /* ICH10 */
2503         { PCI_DEVICE(0x8086, 0x3a6e),
2504           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2505         /* Generic Intel */
2506         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2507           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2508           .class_mask = 0xffffff,
2509           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2510         /* ATI SB 450/600/700/800/900 */
2511         { PCI_DEVICE(0x1002, 0x437b),
2512           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2513         { PCI_DEVICE(0x1002, 0x4383),
2514           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2515         /* AMD Hudson */
2516         { PCI_DEVICE(0x1022, 0x780d),
2517           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2518         /* AMD, X370 & co */
2519         { PCI_DEVICE(0x1022, 0x1457),
2520           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2521         /* AMD, X570 & co */
2522         { PCI_DEVICE(0x1022, 0x1487),
2523           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2524         /* AMD Stoney */
2525         { PCI_DEVICE(0x1022, 0x157a),
2526           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2527                          AZX_DCAPS_PM_RUNTIME },
2528         /* AMD Raven */
2529         { PCI_DEVICE(0x1022, 0x15e3),
2530           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2531         /* ATI HDMI */
2532         { PCI_DEVICE(0x1002, 0x0002),
2533           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2534         { PCI_DEVICE(0x1002, 0x1308),
2535           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2536         { PCI_DEVICE(0x1002, 0x157a),
2537           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2538         { PCI_DEVICE(0x1002, 0x15b3),
2539           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2540         { PCI_DEVICE(0x1002, 0x793b),
2541           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2542         { PCI_DEVICE(0x1002, 0x7919),
2543           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2544         { PCI_DEVICE(0x1002, 0x960f),
2545           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2546         { PCI_DEVICE(0x1002, 0x970f),
2547           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2548         { PCI_DEVICE(0x1002, 0x9840),
2549           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2550         { PCI_DEVICE(0x1002, 0xaa00),
2551           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2552         { PCI_DEVICE(0x1002, 0xaa08),
2553           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2554         { PCI_DEVICE(0x1002, 0xaa10),
2555           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2556         { PCI_DEVICE(0x1002, 0xaa18),
2557           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2558         { PCI_DEVICE(0x1002, 0xaa20),
2559           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2560         { PCI_DEVICE(0x1002, 0xaa28),
2561           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2562         { PCI_DEVICE(0x1002, 0xaa30),
2563           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2564         { PCI_DEVICE(0x1002, 0xaa38),
2565           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2566         { PCI_DEVICE(0x1002, 0xaa40),
2567           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2568         { PCI_DEVICE(0x1002, 0xaa48),
2569           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2570         { PCI_DEVICE(0x1002, 0xaa50),
2571           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2572         { PCI_DEVICE(0x1002, 0xaa58),
2573           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2574         { PCI_DEVICE(0x1002, 0xaa60),
2575           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2576         { PCI_DEVICE(0x1002, 0xaa68),
2577           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2578         { PCI_DEVICE(0x1002, 0xaa80),
2579           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2580         { PCI_DEVICE(0x1002, 0xaa88),
2581           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2582         { PCI_DEVICE(0x1002, 0xaa90),
2583           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2584         { PCI_DEVICE(0x1002, 0xaa98),
2585           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2586         { PCI_DEVICE(0x1002, 0x9902),
2587           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2588         { PCI_DEVICE(0x1002, 0xaaa0),
2589           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2590         { PCI_DEVICE(0x1002, 0xaaa8),
2591           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2592         { PCI_DEVICE(0x1002, 0xaab0),
2593           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2594         { PCI_DEVICE(0x1002, 0xaac0),
2595           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2596         { PCI_DEVICE(0x1002, 0xaac8),
2597           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2598         { PCI_DEVICE(0x1002, 0xaad8),
2599           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2600         { PCI_DEVICE(0x1002, 0xaae8),
2601           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2602         { PCI_DEVICE(0x1002, 0xaae0),
2603           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2604         { PCI_DEVICE(0x1002, 0xaaf0),
2605           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2606         /* VIA VT8251/VT8237A */
2607         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2608         /* VIA GFX VT7122/VX900 */
2609         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2610         /* VIA GFX VT6122/VX11 */
2611         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2612         /* SIS966 */
2613         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2614         /* ULI M5461 */
2615         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2616         /* NVIDIA MCP */
2617         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2618           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2619           .class_mask = 0xffffff,
2620           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2621         /* Teradici */
2622         { PCI_DEVICE(0x6549, 0x1200),
2623           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2624         { PCI_DEVICE(0x6549, 0x2200),
2625           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2626         /* Creative X-Fi (CA0110-IBG) */
2627         /* CTHDA chips */
2628         { PCI_DEVICE(0x1102, 0x0010),
2629           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2630         { PCI_DEVICE(0x1102, 0x0012),
2631           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2632 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2633         /* the following entry conflicts with snd-ctxfi driver,
2634          * as ctxfi driver mutates from HD-audio to native mode with
2635          * a special command sequence.
2636          */
2637         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2638           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2639           .class_mask = 0xffffff,
2640           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2641           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2642 #else
2643         /* this entry seems still valid -- i.e. without emu20kx chip */
2644         { PCI_DEVICE(0x1102, 0x0009),
2645           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2646           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2647 #endif
2648         /* CM8888 */
2649         { PCI_DEVICE(0x13f6, 0x5011),
2650           .driver_data = AZX_DRIVER_CMEDIA |
2651           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2652         /* Vortex86MX */
2653         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2654         /* VMware HDAudio */
2655         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2656         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2657         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2658           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2659           .class_mask = 0xffffff,
2660           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2661         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2662           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2663           .class_mask = 0xffffff,
2664           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2665         /* Zhaoxin */
2666         { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
2667         { 0, }
2668 };
2669 MODULE_DEVICE_TABLE(pci, azx_ids);
2670 
2671 /* pci_driver definition */
2672 static struct pci_driver azx_driver = {
2673         .name = KBUILD_MODNAME,
2674         .id_table = azx_ids,
2675         .probe = azx_probe,
2676         .remove = azx_remove,
2677         .shutdown = azx_shutdown,
2678         .driver = {
2679                 .pm = AZX_PM_OPS,
2680         },
2681 };
2682 
2683 module_pci_driver(azx_driver);

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