This source file includes following definitions.
- codec_has_acomp
- pin_id_to_pin_index
- hinfo_to_pcm_index
- hinfo_to_pin_index
- pcm_idx_to_pin
- cvt_nid_to_cvt_index
- hdmi_eld_ctl_info
- hdmi_eld_ctl_get
- hdmi_create_eld_ctl
- hdmi_get_dip_index
- hdmi_set_dip_index
- hdmi_write_dip_byte
- hdmi_init_pin
- print_eld_info
- write_eld_info
- eld_proc_new
- eld_proc_free
- eld_proc_new
- eld_proc_free
- hdmi_start_infoframe_trans
- hdmi_stop_infoframe_trans
- hdmi_debug_dip_size
- hdmi_clear_dip_buffers
- hdmi_checksum_audio_infoframe
- hdmi_fill_audio_infoframe
- hdmi_infoframe_uptodate
- hdmi_pin_setup_infoframe
- hdmi_setup_audio_infoframe
- check_presence_and_report
- jack_callback
- hdmi_intrinsic_event
- hdmi_non_intrinsic_event
- hdmi_unsol_event
- haswell_verify_D0
- hdmi_pin_hbr_setup
- hdmi_setup_stream
- hdmi_choose_cvt
- intel_verify_pin_cvt_connect
- intel_cvt_id_to_mux_idx
- intel_not_share_assigned_cvt
- intel_not_share_assigned_cvt_nid
- pin_cvt_fixup
- hdmi_pcm_open_no_pin
- hdmi_pcm_open
- hdmi_read_pin_conn
- hdmi_find_pcm_slot
- hdmi_attach_hda_pcm
- hdmi_detach_hda_pcm
- hdmi_get_pin_cvt_mux
- hdmi_pcm_setup_pin
- hdmi_pcm_reset_pin
- update_eld
- hdmi_present_sense_via_verbs
- pin_idx_to_jack
- sync_eld_via_acomp
- hdmi_present_sense
- hdmi_repoll_eld
- hdmi_add_pin
- hdmi_add_cvt
- hdmi_parse_codec
- check_non_pcm_per_cvt
- generic_hdmi_playback_pcm_prepare
- generic_hdmi_playback_pcm_cleanup
- hdmi_pcm_close
- hdmi_get_spk_alloc
- hdmi_get_chmap
- hdmi_set_chmap
- is_hdmi_pcm_attached
- generic_hdmi_build_pcms
- free_hdmi_jack_priv
- add_hdmi_jack_kctl
- generic_hdmi_build_jack
- generic_hdmi_build_controls
- generic_hdmi_init_per_pins
- generic_hdmi_init
- hdmi_array_init
- hdmi_array_free
- generic_spec_free
- generic_hdmi_free
- generic_hdmi_resume
- alloc_generic_hdmi
- patch_generic_hdmi
- reprogram_jack_detect
- generic_acomp_notifier_set
- generic_acomp_master_bind
- generic_acomp_master_unbind
- match_bound_vga
- generic_acomp_pin_eld_notify
- setup_drm_audio_ops
- generic_acomp_init
- intel_haswell_fixup_connect_list
- intel_haswell_enable_all_pins
- intel_haswell_fixup_enable_dp12
- haswell_set_power_state
- intel_base_nid
- intel_pin2port
- intel_port2pin
- intel_pin_eld_notify
- register_i915_notifier
- i915_hsw_setup_stream
- i915_pin_cvt_fixup
- alloc_intel_hdmi
- parse_intel_hdmi
- intel_hsw_common_init
- patch_i915_hsw_hdmi
- patch_i915_glk_hdmi
- patch_i915_icl_hdmi
- patch_i915_tgl_hdmi
- patch_i915_byt_hdmi
- patch_i915_cpt_hdmi
- simple_playback_build_pcms
- simple_hdmi_unsol_event
- simple_playback_build_controls
- simple_playback_init
- simple_playback_free
- nvhdmi_7x_init_2ch
- nvhdmi_7x_init_8ch
- simple_playback_pcm_open
- simple_playback_pcm_close
- simple_playback_pcm_prepare
- patch_simple_hdmi
- nvhdmi_8ch_7x_set_info_frame_parameters
- nvhdmi_8ch_7x_pcm_close
- nvhdmi_8ch_7x_pcm_prepare
- patch_nvhdmi_2ch
- nvhdmi_7x_8ch_build_pcms
- nvhdmi_7x_8ch_build_controls
- patch_nvhdmi_8ch_7x
- nvhdmi_chmap_cea_alloc_validate_get_type
- nvhdmi_chmap_validate
- patch_nvhdmi
- tegra_hdmi_set_format
- tegra_hdmi_pcm_prepare
- tegra_hdmi_pcm_cleanup
- hda_find_pcm_by_type
- tegra_hdmi_build_pcms
- patch_tegra_hdmi
- atihdmi_pin_get_eld
- atihdmi_pin_setup_infoframe
- atihdmi_paired_swap_fc_lfe
- atihdmi_paired_chmap_validate
- atihdmi_pin_set_slot_channel
- atihdmi_pin_get_slot_channel
- atihdmi_paired_chmap_cea_alloc_validate_get_type
- atihdmi_paired_cea_alloc_to_tlv_chmap
- atihdmi_pin_hbr_setup
- atihdmi_setup_stream
- atihdmi_init
- atihdmi_pin2port
- atihdmi_port2pin
- patch_atihdmi
- patch_via_hdmi
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19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/pci.h>
22 #include <linux/slab.h>
23 #include <linux/module.h>
24 #include <linux/pm_runtime.h>
25 #include <sound/core.h>
26 #include <sound/jack.h>
27 #include <sound/asoundef.h>
28 #include <sound/tlv.h>
29 #include <sound/hdaudio.h>
30 #include <sound/hda_i915.h>
31 #include <sound/hda_chmap.h>
32 #include <sound/hda_codec.h>
33 #include "hda_local.h"
34 #include "hda_jack.h"
35 #include "hda_controller.h"
36
37 static bool static_hdmi_pcm;
38 module_param(static_hdmi_pcm, bool, 0644);
39 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
40
41 #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
42 #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
43 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
44 #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
45 #define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
46 #define is_geminilake(codec) (((codec)->core.vendor_id == 0x8086280d) || \
47 ((codec)->core.vendor_id == 0x80862800))
48 #define is_cannonlake(codec) ((codec)->core.vendor_id == 0x8086280c)
49 #define is_icelake(codec) ((codec)->core.vendor_id == 0x8086280f)
50 #define is_tigerlake(codec) ((codec)->core.vendor_id == 0x80862812)
51 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
52 || is_skylake(codec) || is_broxton(codec) \
53 || is_kabylake(codec) || is_geminilake(codec) \
54 || is_cannonlake(codec) || is_icelake(codec) \
55 || is_tigerlake(codec))
56 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
57 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
58 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
59
60 static bool enable_acomp = true;
61 module_param(enable_acomp, bool, 0444);
62 MODULE_PARM_DESC(enable_acomp, "Enable audio component binding (default=yes)");
63
64 struct hdmi_spec_per_cvt {
65 hda_nid_t cvt_nid;
66 int assigned;
67 unsigned int channels_min;
68 unsigned int channels_max;
69 u32 rates;
70 u64 formats;
71 unsigned int maxbps;
72 };
73
74
75 #define HDA_MAX_CONNECTIONS 32
76
77 struct hdmi_spec_per_pin {
78 hda_nid_t pin_nid;
79 int dev_id;
80
81 int pin_nid_idx;
82 int num_mux_nids;
83 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
84 int mux_idx;
85 hda_nid_t cvt_nid;
86
87 struct hda_codec *codec;
88 struct hdmi_eld sink_eld;
89 struct mutex lock;
90 struct delayed_work work;
91 struct hdmi_pcm *pcm;
92 int pcm_idx;
93 int repoll_count;
94 bool setup;
95 int channels;
96 bool non_pcm;
97 bool chmap_set;
98 unsigned char chmap[8];
99 #ifdef CONFIG_SND_PROC_FS
100 struct snd_info_entry *proc_entry;
101 #endif
102 };
103
104
105 struct hdmi_ops {
106 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
107 unsigned char *buf, int *eld_size);
108
109 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
110 int ca, int active_channels, int conn_type);
111
112
113 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
114
115 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
116 hda_nid_t pin_nid, u32 stream_tag, int format);
117
118 void (*pin_cvt_fixup)(struct hda_codec *codec,
119 struct hdmi_spec_per_pin *per_pin,
120 hda_nid_t cvt_nid);
121 };
122
123 struct hdmi_pcm {
124 struct hda_pcm *pcm;
125 struct snd_jack *jack;
126 struct snd_kcontrol *eld_ctl;
127 };
128
129 struct hdmi_spec {
130 struct hda_codec *codec;
131 int num_cvts;
132 struct snd_array cvts;
133 hda_nid_t cvt_nids[4];
134
135
136
137
138
139
140 int num_pins;
141
142
143
144
145 int num_nids;
146
147
148
149
150
151 int dev_num;
152 struct snd_array pins;
153 struct hdmi_pcm pcm_rec[16];
154 struct mutex pcm_lock;
155 struct mutex bind_lock;
156
157 unsigned long pcm_bitmap;
158 int pcm_used;
159
160
161
162
163 unsigned long pcm_in_use;
164
165 struct hdmi_eld temp_eld;
166 struct hdmi_ops ops;
167
168 bool dyn_pin_out;
169 bool dyn_pcm_assign;
170
171
172
173 struct hda_multi_out multiout;
174 struct hda_pcm_stream pcm_playback;
175
176 bool use_jack_detect;
177 bool use_acomp_notifier;
178 bool acomp_registered;
179 struct drm_audio_component_audio_ops drm_audio_ops;
180 int (*port2pin)(struct hda_codec *, int);
181
182 struct hdac_chmap chmap;
183 hda_nid_t vendor_nid;
184 const int *port_map;
185 int port_num;
186 };
187
188 #ifdef CONFIG_SND_HDA_COMPONENT
189 static inline bool codec_has_acomp(struct hda_codec *codec)
190 {
191 struct hdmi_spec *spec = codec->spec;
192 return spec->use_acomp_notifier;
193 }
194 #else
195 #define codec_has_acomp(codec) false
196 #endif
197
198 struct hdmi_audio_infoframe {
199 u8 type;
200 u8 ver;
201 u8 len;
202
203 u8 checksum;
204
205 u8 CC02_CT47;
206 u8 SS01_SF24;
207 u8 CXT04;
208 u8 CA;
209 u8 LFEPBL01_LSV36_DM_INH7;
210 };
211
212 struct dp_audio_infoframe {
213 u8 type;
214 u8 len;
215 u8 ver;
216
217 u8 CC02_CT47;
218 u8 SS01_SF24;
219 u8 CXT04;
220 u8 CA;
221 u8 LFEPBL01_LSV36_DM_INH7;
222 };
223
224 union audio_infoframe {
225 struct hdmi_audio_infoframe hdmi;
226 struct dp_audio_infoframe dp;
227 u8 bytes[0];
228 };
229
230
231
232
233
234 #define get_pin(spec, idx) \
235 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
236 #define get_cvt(spec, idx) \
237 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
238
239 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
240
241 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
242
243 static int pin_id_to_pin_index(struct hda_codec *codec,
244 hda_nid_t pin_nid, int dev_id)
245 {
246 struct hdmi_spec *spec = codec->spec;
247 int pin_idx;
248 struct hdmi_spec_per_pin *per_pin;
249
250
251
252
253
254 if (dev_id == -1)
255 dev_id = 0;
256
257 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
258 per_pin = get_pin(spec, pin_idx);
259 if ((per_pin->pin_nid == pin_nid) &&
260 (per_pin->dev_id == dev_id))
261 return pin_idx;
262 }
263
264 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
265 return -EINVAL;
266 }
267
268 static int hinfo_to_pcm_index(struct hda_codec *codec,
269 struct hda_pcm_stream *hinfo)
270 {
271 struct hdmi_spec *spec = codec->spec;
272 int pcm_idx;
273
274 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
275 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
276 return pcm_idx;
277
278 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
279 return -EINVAL;
280 }
281
282 static int hinfo_to_pin_index(struct hda_codec *codec,
283 struct hda_pcm_stream *hinfo)
284 {
285 struct hdmi_spec *spec = codec->spec;
286 struct hdmi_spec_per_pin *per_pin;
287 int pin_idx;
288
289 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
290 per_pin = get_pin(spec, pin_idx);
291 if (per_pin->pcm &&
292 per_pin->pcm->pcm->stream == hinfo)
293 return pin_idx;
294 }
295
296 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo);
297 return -EINVAL;
298 }
299
300 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
301 int pcm_idx)
302 {
303 int i;
304 struct hdmi_spec_per_pin *per_pin;
305
306 for (i = 0; i < spec->num_pins; i++) {
307 per_pin = get_pin(spec, i);
308 if (per_pin->pcm_idx == pcm_idx)
309 return per_pin;
310 }
311 return NULL;
312 }
313
314 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
315 {
316 struct hdmi_spec *spec = codec->spec;
317 int cvt_idx;
318
319 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
320 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
321 return cvt_idx;
322
323 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
324 return -EINVAL;
325 }
326
327 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
328 struct snd_ctl_elem_info *uinfo)
329 {
330 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
331 struct hdmi_spec *spec = codec->spec;
332 struct hdmi_spec_per_pin *per_pin;
333 struct hdmi_eld *eld;
334 int pcm_idx;
335
336 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
337
338 pcm_idx = kcontrol->private_value;
339 mutex_lock(&spec->pcm_lock);
340 per_pin = pcm_idx_to_pin(spec, pcm_idx);
341 if (!per_pin) {
342
343 uinfo->count = 0;
344 goto unlock;
345 }
346 eld = &per_pin->sink_eld;
347 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
348
349 unlock:
350 mutex_unlock(&spec->pcm_lock);
351 return 0;
352 }
353
354 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
355 struct snd_ctl_elem_value *ucontrol)
356 {
357 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
358 struct hdmi_spec *spec = codec->spec;
359 struct hdmi_spec_per_pin *per_pin;
360 struct hdmi_eld *eld;
361 int pcm_idx;
362 int err = 0;
363
364 pcm_idx = kcontrol->private_value;
365 mutex_lock(&spec->pcm_lock);
366 per_pin = pcm_idx_to_pin(spec, pcm_idx);
367 if (!per_pin) {
368
369 memset(ucontrol->value.bytes.data, 0,
370 ARRAY_SIZE(ucontrol->value.bytes.data));
371 goto unlock;
372 }
373
374 eld = &per_pin->sink_eld;
375 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
376 eld->eld_size > ELD_MAX_SIZE) {
377 snd_BUG();
378 err = -EINVAL;
379 goto unlock;
380 }
381
382 memset(ucontrol->value.bytes.data, 0,
383 ARRAY_SIZE(ucontrol->value.bytes.data));
384 if (eld->eld_valid)
385 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
386 eld->eld_size);
387
388 unlock:
389 mutex_unlock(&spec->pcm_lock);
390 return err;
391 }
392
393 static const struct snd_kcontrol_new eld_bytes_ctl = {
394 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
395 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
396 .name = "ELD",
397 .info = hdmi_eld_ctl_info,
398 .get = hdmi_eld_ctl_get,
399 };
400
401 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
402 int device)
403 {
404 struct snd_kcontrol *kctl;
405 struct hdmi_spec *spec = codec->spec;
406 int err;
407
408 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
409 if (!kctl)
410 return -ENOMEM;
411 kctl->private_value = pcm_idx;
412 kctl->id.device = device;
413
414
415
416
417 err = snd_hda_ctl_add(codec, 0, kctl);
418 if (err < 0)
419 return err;
420
421 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
422 return 0;
423 }
424
425 #ifdef BE_PARANOID
426 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
427 int *packet_index, int *byte_index)
428 {
429 int val;
430
431 val = snd_hda_codec_read(codec, pin_nid, 0,
432 AC_VERB_GET_HDMI_DIP_INDEX, 0);
433
434 *packet_index = val >> 5;
435 *byte_index = val & 0x1f;
436 }
437 #endif
438
439 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
440 int packet_index, int byte_index)
441 {
442 int val;
443
444 val = (packet_index << 5) | (byte_index & 0x1f);
445
446 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
447 }
448
449 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
450 unsigned char val)
451 {
452 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
453 }
454
455 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
456 {
457 struct hdmi_spec *spec = codec->spec;
458 int pin_out;
459
460
461 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
462 snd_hda_codec_write(codec, pin_nid, 0,
463 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
464
465 if (spec->dyn_pin_out)
466
467 pin_out = 0;
468 else
469
470
471
472 pin_out = PIN_OUT;
473
474 snd_hda_codec_write(codec, pin_nid, 0,
475 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
476 }
477
478
479
480
481
482 #ifdef CONFIG_SND_PROC_FS
483 static void print_eld_info(struct snd_info_entry *entry,
484 struct snd_info_buffer *buffer)
485 {
486 struct hdmi_spec_per_pin *per_pin = entry->private_data;
487
488 mutex_lock(&per_pin->lock);
489 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
490 mutex_unlock(&per_pin->lock);
491 }
492
493 static void write_eld_info(struct snd_info_entry *entry,
494 struct snd_info_buffer *buffer)
495 {
496 struct hdmi_spec_per_pin *per_pin = entry->private_data;
497
498 mutex_lock(&per_pin->lock);
499 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
500 mutex_unlock(&per_pin->lock);
501 }
502
503 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
504 {
505 char name[32];
506 struct hda_codec *codec = per_pin->codec;
507 struct snd_info_entry *entry;
508 int err;
509
510 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
511 err = snd_card_proc_new(codec->card, name, &entry);
512 if (err < 0)
513 return err;
514
515 snd_info_set_text_ops(entry, per_pin, print_eld_info);
516 entry->c.text.write = write_eld_info;
517 entry->mode |= 0200;
518 per_pin->proc_entry = entry;
519
520 return 0;
521 }
522
523 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
524 {
525 if (!per_pin->codec->bus->shutdown) {
526 snd_info_free_entry(per_pin->proc_entry);
527 per_pin->proc_entry = NULL;
528 }
529 }
530 #else
531 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
532 int index)
533 {
534 return 0;
535 }
536 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
537 {
538 }
539 #endif
540
541
542
543
544
545
546
547
548 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
549 hda_nid_t pin_nid)
550 {
551 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
552 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
553 AC_DIPXMIT_BEST);
554 }
555
556
557
558
559 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
560 hda_nid_t pin_nid)
561 {
562 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
563 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
564 AC_DIPXMIT_DISABLE);
565 }
566
567 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
568 {
569 #ifdef CONFIG_SND_DEBUG_VERBOSE
570 int i;
571 int size;
572
573 size = snd_hdmi_get_eld_size(codec, pin_nid);
574 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
575
576 for (i = 0; i < 8; i++) {
577 size = snd_hda_codec_read(codec, pin_nid, 0,
578 AC_VERB_GET_HDMI_DIP_SIZE, i);
579 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
580 }
581 #endif
582 }
583
584 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
585 {
586 #ifdef BE_PARANOID
587 int i, j;
588 int size;
589 int pi, bi;
590 for (i = 0; i < 8; i++) {
591 size = snd_hda_codec_read(codec, pin_nid, 0,
592 AC_VERB_GET_HDMI_DIP_SIZE, i);
593 if (size == 0)
594 continue;
595
596 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
597 for (j = 1; j < 1000; j++) {
598 hdmi_write_dip_byte(codec, pin_nid, 0x0);
599 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
600 if (pi != i)
601 codec_dbg(codec, "dip index %d: %d != %d\n",
602 bi, pi, i);
603 if (bi == 0)
604 break;
605 }
606 codec_dbg(codec,
607 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
608 i, size, j);
609 }
610 #endif
611 }
612
613 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
614 {
615 u8 *bytes = (u8 *)hdmi_ai;
616 u8 sum = 0;
617 int i;
618
619 hdmi_ai->checksum = 0;
620
621 for (i = 0; i < sizeof(*hdmi_ai); i++)
622 sum += bytes[i];
623
624 hdmi_ai->checksum = -sum;
625 }
626
627 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
628 hda_nid_t pin_nid,
629 u8 *dip, int size)
630 {
631 int i;
632
633 hdmi_debug_dip_size(codec, pin_nid);
634 hdmi_clear_dip_buffers(codec, pin_nid);
635
636 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
637 for (i = 0; i < size; i++)
638 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
639 }
640
641 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
642 u8 *dip, int size)
643 {
644 u8 val;
645 int i;
646
647 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
648 != AC_DIPXMIT_BEST)
649 return false;
650
651 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
652 for (i = 0; i < size; i++) {
653 val = snd_hda_codec_read(codec, pin_nid, 0,
654 AC_VERB_GET_HDMI_DIP_DATA, 0);
655 if (val != dip[i])
656 return false;
657 }
658
659 return true;
660 }
661
662 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
663 hda_nid_t pin_nid,
664 int ca, int active_channels,
665 int conn_type)
666 {
667 union audio_infoframe ai;
668
669 memset(&ai, 0, sizeof(ai));
670 if (conn_type == 0) {
671 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
672
673 hdmi_ai->type = 0x84;
674 hdmi_ai->ver = 0x01;
675 hdmi_ai->len = 0x0a;
676 hdmi_ai->CC02_CT47 = active_channels - 1;
677 hdmi_ai->CA = ca;
678 hdmi_checksum_audio_infoframe(hdmi_ai);
679 } else if (conn_type == 1) {
680 struct dp_audio_infoframe *dp_ai = &ai.dp;
681
682 dp_ai->type = 0x84;
683 dp_ai->len = 0x1b;
684 dp_ai->ver = 0x11 << 2;
685 dp_ai->CC02_CT47 = active_channels - 1;
686 dp_ai->CA = ca;
687 } else {
688 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
689 pin_nid);
690 return;
691 }
692
693
694
695
696
697
698 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
699 sizeof(ai))) {
700 codec_dbg(codec,
701 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
702 pin_nid,
703 active_channels, ca);
704 hdmi_stop_infoframe_trans(codec, pin_nid);
705 hdmi_fill_audio_infoframe(codec, pin_nid,
706 ai.bytes, sizeof(ai));
707 hdmi_start_infoframe_trans(codec, pin_nid);
708 }
709 }
710
711 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
712 struct hdmi_spec_per_pin *per_pin,
713 bool non_pcm)
714 {
715 struct hdmi_spec *spec = codec->spec;
716 struct hdac_chmap *chmap = &spec->chmap;
717 hda_nid_t pin_nid = per_pin->pin_nid;
718 int channels = per_pin->channels;
719 int active_channels;
720 struct hdmi_eld *eld;
721 int ca;
722
723 if (!channels)
724 return;
725
726
727 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
728 snd_hda_codec_write(codec, pin_nid, 0,
729 AC_VERB_SET_AMP_GAIN_MUTE,
730 AMP_OUT_UNMUTE);
731
732 eld = &per_pin->sink_eld;
733
734 ca = snd_hdac_channel_allocation(&codec->core,
735 eld->info.spk_alloc, channels,
736 per_pin->chmap_set, non_pcm, per_pin->chmap);
737
738 active_channels = snd_hdac_get_active_channels(ca);
739
740 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
741 active_channels);
742
743
744
745
746
747 snd_hdac_setup_channel_mapping(&spec->chmap,
748 pin_nid, non_pcm, ca, channels,
749 per_pin->chmap, per_pin->chmap_set);
750
751 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
752 eld->info.conn_type);
753
754 per_pin->non_pcm = non_pcm;
755 }
756
757
758
759
760
761 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
762
763 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
764 int dev_id)
765 {
766 struct hdmi_spec *spec = codec->spec;
767 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
768
769 if (pin_idx < 0)
770 return;
771 mutex_lock(&spec->pcm_lock);
772 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
773 snd_hda_jack_report_sync(codec);
774 mutex_unlock(&spec->pcm_lock);
775 }
776
777 static void jack_callback(struct hda_codec *codec,
778 struct hda_jack_callback *jack)
779 {
780
781 if (codec_has_acomp(codec))
782 return;
783
784
785 check_presence_and_report(codec, jack->nid, 0);
786 }
787
788 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
789 {
790 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
791 struct hda_jack_tbl *jack;
792 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
793
794
795
796
797
798
799
800 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
801 if (!jack)
802 return;
803 jack->jack_dirty = 1;
804
805 codec_dbg(codec,
806 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
807 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
808 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
809
810
811 check_presence_and_report(codec, jack->nid, 0);
812 }
813
814 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
815 {
816 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
817 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
818 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
819 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
820
821 codec_info(codec,
822 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
823 codec->addr,
824 tag,
825 subtag,
826 cp_state,
827 cp_ready);
828
829
830 if (cp_state)
831 ;
832 if (cp_ready)
833 ;
834 }
835
836
837 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
838 {
839 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
840 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
841
842 if (codec_has_acomp(codec))
843 return;
844
845 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
846 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
847 return;
848 }
849
850 if (subtag == 0)
851 hdmi_intrinsic_event(codec, res);
852 else
853 hdmi_non_intrinsic_event(codec, res);
854 }
855
856 static void haswell_verify_D0(struct hda_codec *codec,
857 hda_nid_t cvt_nid, hda_nid_t nid)
858 {
859 int pwr;
860
861
862
863
864 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
865 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
866
867 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
868 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
869 AC_PWRST_D0);
870 msleep(40);
871 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
872 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
873 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
874 }
875 }
876
877
878
879
880
881
882 #define is_hbr_format(format) \
883 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
884
885 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
886 bool hbr)
887 {
888 int pinctl, new_pinctl;
889
890 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
891 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
892 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
893
894 if (pinctl < 0)
895 return hbr ? -EINVAL : 0;
896
897 new_pinctl = pinctl & ~AC_PINCTL_EPT;
898 if (hbr)
899 new_pinctl |= AC_PINCTL_EPT_HBR;
900 else
901 new_pinctl |= AC_PINCTL_EPT_NATIVE;
902
903 codec_dbg(codec,
904 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
905 pin_nid,
906 pinctl == new_pinctl ? "" : "new-",
907 new_pinctl);
908
909 if (pinctl != new_pinctl)
910 snd_hda_codec_write(codec, pin_nid, 0,
911 AC_VERB_SET_PIN_WIDGET_CONTROL,
912 new_pinctl);
913 } else if (hbr)
914 return -EINVAL;
915
916 return 0;
917 }
918
919 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
920 hda_nid_t pin_nid, u32 stream_tag, int format)
921 {
922 struct hdmi_spec *spec = codec->spec;
923 unsigned int param;
924 int err;
925
926 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
927
928 if (err) {
929 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
930 return err;
931 }
932
933 if (is_haswell_plus(codec)) {
934
935
936
937
938
939
940 param = snd_hda_codec_read(codec, cvt_nid, 0,
941 AC_VERB_GET_DIGI_CONVERT_1, 0);
942
943 param = (param >> 16) & ~(AC_DIG3_ICT);
944
945
946 if (is_hbr_format(format))
947 param |= 0x1;
948
949 snd_hda_codec_write(codec, cvt_nid, 0,
950 AC_VERB_SET_DIGI_CONVERT_3, param);
951 }
952
953 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
954 return 0;
955 }
956
957
958
959
960
961
962 static int hdmi_choose_cvt(struct hda_codec *codec,
963 int pin_idx, int *cvt_id)
964 {
965 struct hdmi_spec *spec = codec->spec;
966 struct hdmi_spec_per_pin *per_pin;
967 struct hdmi_spec_per_cvt *per_cvt = NULL;
968 int cvt_idx, mux_idx = 0;
969
970
971 if (pin_idx < 0)
972 per_pin = NULL;
973 else
974 per_pin = get_pin(spec, pin_idx);
975
976
977 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
978 per_cvt = get_cvt(spec, cvt_idx);
979
980
981 if (per_cvt->assigned)
982 continue;
983 if (per_pin == NULL)
984 break;
985
986 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
987 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
988 break;
989
990 if (mux_idx == per_pin->num_mux_nids)
991 continue;
992 break;
993 }
994
995
996 if (cvt_idx == spec->num_cvts)
997 return -EBUSY;
998
999 if (per_pin != NULL)
1000 per_pin->mux_idx = mux_idx;
1001
1002 if (cvt_id)
1003 *cvt_id = cvt_idx;
1004
1005 return 0;
1006 }
1007
1008
1009 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1010 struct hdmi_spec_per_pin *per_pin)
1011 {
1012 hda_nid_t pin_nid = per_pin->pin_nid;
1013 int mux_idx, curr;
1014
1015 mux_idx = per_pin->mux_idx;
1016 curr = snd_hda_codec_read(codec, pin_nid, 0,
1017 AC_VERB_GET_CONNECT_SEL, 0);
1018 if (curr != mux_idx)
1019 snd_hda_codec_write_cache(codec, pin_nid, 0,
1020 AC_VERB_SET_CONNECT_SEL,
1021 mux_idx);
1022 }
1023
1024
1025
1026
1027 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1028 hda_nid_t cvt_nid)
1029 {
1030 int i;
1031
1032 for (i = 0; i < spec->num_cvts; i++)
1033 if (spec->cvt_nids[i] == cvt_nid)
1034 return i;
1035 return -EINVAL;
1036 }
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1048 hda_nid_t pin_nid,
1049 int dev_id, int mux_idx)
1050 {
1051 struct hdmi_spec *spec = codec->spec;
1052 hda_nid_t nid;
1053 int cvt_idx, curr;
1054 struct hdmi_spec_per_cvt *per_cvt;
1055 struct hdmi_spec_per_pin *per_pin;
1056 int pin_idx;
1057
1058
1059 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1060 int dev_id_saved;
1061 int dev_num;
1062
1063 per_pin = get_pin(spec, pin_idx);
1064
1065
1066
1067
1068 if (!per_pin->pcm)
1069 continue;
1070
1071 if ((per_pin->pin_nid == pin_nid) &&
1072 (per_pin->dev_id == dev_id))
1073 continue;
1074
1075
1076
1077
1078
1079
1080
1081 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
1082 if (per_pin->dev_id >= dev_num)
1083 continue;
1084
1085 nid = per_pin->pin_nid;
1086
1087
1088
1089
1090
1091
1092
1093 dev_id_saved = snd_hda_get_dev_select(codec, nid);
1094 snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
1095 curr = snd_hda_codec_read(codec, nid, 0,
1096 AC_VERB_GET_CONNECT_SEL, 0);
1097 if (curr != mux_idx) {
1098 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1099 continue;
1100 }
1101
1102
1103
1104
1105
1106 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1107 per_cvt = get_cvt(spec, cvt_idx);
1108 if (!per_cvt->assigned) {
1109 codec_dbg(codec,
1110 "choose cvt %d for pin nid %d\n",
1111 cvt_idx, nid);
1112 snd_hda_codec_write_cache(codec, nid, 0,
1113 AC_VERB_SET_CONNECT_SEL,
1114 cvt_idx);
1115 break;
1116 }
1117 }
1118 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1119 }
1120 }
1121
1122
1123 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1124 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
1125 {
1126 int mux_idx;
1127 struct hdmi_spec *spec = codec->spec;
1128
1129
1130
1131
1132
1133
1134 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1135 if (mux_idx >= 0)
1136 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
1137 }
1138
1139
1140 static void pin_cvt_fixup(struct hda_codec *codec,
1141 struct hdmi_spec_per_pin *per_pin,
1142 hda_nid_t cvt_nid)
1143 {
1144 struct hdmi_spec *spec = codec->spec;
1145
1146 if (spec->ops.pin_cvt_fixup)
1147 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1148 }
1149
1150
1151
1152
1153 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1154 struct hda_codec *codec,
1155 struct snd_pcm_substream *substream)
1156 {
1157 struct hdmi_spec *spec = codec->spec;
1158 struct snd_pcm_runtime *runtime = substream->runtime;
1159 int cvt_idx, pcm_idx;
1160 struct hdmi_spec_per_cvt *per_cvt = NULL;
1161 int err;
1162
1163 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1164 if (pcm_idx < 0)
1165 return -EINVAL;
1166
1167 err = hdmi_choose_cvt(codec, -1, &cvt_idx);
1168 if (err)
1169 return err;
1170
1171 per_cvt = get_cvt(spec, cvt_idx);
1172 per_cvt->assigned = 1;
1173 hinfo->nid = per_cvt->cvt_nid;
1174
1175 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
1176
1177 set_bit(pcm_idx, &spec->pcm_in_use);
1178
1179
1180
1181 hinfo->channels_min = per_cvt->channels_min;
1182 hinfo->channels_max = per_cvt->channels_max;
1183 hinfo->rates = per_cvt->rates;
1184 hinfo->formats = per_cvt->formats;
1185 hinfo->maxbps = per_cvt->maxbps;
1186
1187
1188 runtime->hw.channels_min = hinfo->channels_min;
1189 runtime->hw.channels_max = hinfo->channels_max;
1190 runtime->hw.formats = hinfo->formats;
1191 runtime->hw.rates = hinfo->rates;
1192
1193 snd_pcm_hw_constraint_step(substream->runtime, 0,
1194 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1195 return 0;
1196 }
1197
1198
1199
1200
1201 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1202 struct hda_codec *codec,
1203 struct snd_pcm_substream *substream)
1204 {
1205 struct hdmi_spec *spec = codec->spec;
1206 struct snd_pcm_runtime *runtime = substream->runtime;
1207 int pin_idx, cvt_idx, pcm_idx;
1208 struct hdmi_spec_per_pin *per_pin;
1209 struct hdmi_eld *eld;
1210 struct hdmi_spec_per_cvt *per_cvt = NULL;
1211 int err;
1212
1213
1214 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1215 if (pcm_idx < 0)
1216 return -EINVAL;
1217
1218 mutex_lock(&spec->pcm_lock);
1219 pin_idx = hinfo_to_pin_index(codec, hinfo);
1220 if (!spec->dyn_pcm_assign) {
1221 if (snd_BUG_ON(pin_idx < 0)) {
1222 err = -EINVAL;
1223 goto unlock;
1224 }
1225 } else {
1226
1227
1228
1229 if (pin_idx < 0) {
1230 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1231 goto unlock;
1232 }
1233 }
1234
1235 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
1236 if (err < 0)
1237 goto unlock;
1238
1239 per_cvt = get_cvt(spec, cvt_idx);
1240
1241 per_cvt->assigned = 1;
1242
1243 set_bit(pcm_idx, &spec->pcm_in_use);
1244 per_pin = get_pin(spec, pin_idx);
1245 per_pin->cvt_nid = per_cvt->cvt_nid;
1246 hinfo->nid = per_cvt->cvt_nid;
1247
1248
1249 if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE)
1250 azx_stream(get_azx_dev(substream))->stripe = 1;
1251
1252 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1253 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1254 AC_VERB_SET_CONNECT_SEL,
1255 per_pin->mux_idx);
1256
1257
1258 pin_cvt_fixup(codec, per_pin, 0);
1259
1260 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1261
1262
1263 hinfo->channels_min = per_cvt->channels_min;
1264 hinfo->channels_max = per_cvt->channels_max;
1265 hinfo->rates = per_cvt->rates;
1266 hinfo->formats = per_cvt->formats;
1267 hinfo->maxbps = per_cvt->maxbps;
1268
1269 eld = &per_pin->sink_eld;
1270
1271 if (!static_hdmi_pcm && eld->eld_valid) {
1272 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1273 if (hinfo->channels_min > hinfo->channels_max ||
1274 !hinfo->rates || !hinfo->formats) {
1275 per_cvt->assigned = 0;
1276 hinfo->nid = 0;
1277 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1278 err = -ENODEV;
1279 goto unlock;
1280 }
1281 }
1282
1283
1284 runtime->hw.channels_min = hinfo->channels_min;
1285 runtime->hw.channels_max = hinfo->channels_max;
1286 runtime->hw.formats = hinfo->formats;
1287 runtime->hw.rates = hinfo->rates;
1288
1289 snd_pcm_hw_constraint_step(substream->runtime, 0,
1290 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1291 unlock:
1292 mutex_unlock(&spec->pcm_lock);
1293 return err;
1294 }
1295
1296
1297
1298
1299 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1300 {
1301 struct hdmi_spec *spec = codec->spec;
1302 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1303 hda_nid_t pin_nid = per_pin->pin_nid;
1304
1305 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1306 codec_warn(codec,
1307 "HDMI: pin %d wcaps %#x does not support connection list\n",
1308 pin_nid, get_wcaps(codec, pin_nid));
1309 return -EINVAL;
1310 }
1311
1312
1313 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1314 per_pin->mux_nids,
1315 HDA_MAX_CONNECTIONS);
1316
1317 return 0;
1318 }
1319
1320 static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1321 struct hdmi_spec_per_pin *per_pin)
1322 {
1323 int i;
1324
1325
1326 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1327 return per_pin->pin_nid_idx;
1328
1329
1330 for (i = spec->num_nids; i < spec->pcm_used; i++) {
1331 if (!test_bit(i, &spec->pcm_bitmap))
1332 return i;
1333 }
1334
1335
1336 for (i = 0; i < spec->num_nids; i++) {
1337 if (!test_bit(i, &spec->pcm_bitmap))
1338 return i;
1339 }
1340 return -EBUSY;
1341 }
1342
1343 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1344 struct hdmi_spec_per_pin *per_pin)
1345 {
1346 int idx;
1347
1348
1349 if (per_pin->pcm)
1350 return;
1351 idx = hdmi_find_pcm_slot(spec, per_pin);
1352 if (idx == -EBUSY)
1353 return;
1354 per_pin->pcm_idx = idx;
1355 per_pin->pcm = get_hdmi_pcm(spec, idx);
1356 set_bit(idx, &spec->pcm_bitmap);
1357 }
1358
1359 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1360 struct hdmi_spec_per_pin *per_pin)
1361 {
1362 int idx;
1363
1364
1365 if (!per_pin->pcm)
1366 return;
1367 idx = per_pin->pcm_idx;
1368 per_pin->pcm_idx = -1;
1369 per_pin->pcm = NULL;
1370 if (idx >= 0 && idx < spec->pcm_used)
1371 clear_bit(idx, &spec->pcm_bitmap);
1372 }
1373
1374 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1375 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1376 {
1377 int mux_idx;
1378
1379 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1380 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1381 break;
1382 return mux_idx;
1383 }
1384
1385 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1386
1387 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1388 struct hdmi_spec_per_pin *per_pin)
1389 {
1390 struct hda_codec *codec = per_pin->codec;
1391 struct hda_pcm *pcm;
1392 struct hda_pcm_stream *hinfo;
1393 struct snd_pcm_substream *substream;
1394 int mux_idx;
1395 bool non_pcm;
1396
1397 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1398 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1399 else
1400 return;
1401 if (!pcm->pcm)
1402 return;
1403 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1404 return;
1405
1406
1407 hinfo = pcm->stream;
1408 substream = pcm->pcm->streams[0].substream;
1409
1410 per_pin->cvt_nid = hinfo->nid;
1411
1412 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1413 if (mux_idx < per_pin->num_mux_nids) {
1414 snd_hda_set_dev_select(codec, per_pin->pin_nid,
1415 per_pin->dev_id);
1416 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1417 AC_VERB_SET_CONNECT_SEL,
1418 mux_idx);
1419 }
1420 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1421
1422 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1423 if (substream->runtime)
1424 per_pin->channels = substream->runtime->channels;
1425 per_pin->setup = true;
1426 per_pin->mux_idx = mux_idx;
1427
1428 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1429 }
1430
1431 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1432 struct hdmi_spec_per_pin *per_pin)
1433 {
1434 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1435 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1436
1437 per_pin->chmap_set = false;
1438 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1439
1440 per_pin->setup = false;
1441 per_pin->channels = 0;
1442 }
1443
1444
1445
1446
1447 static bool update_eld(struct hda_codec *codec,
1448 struct hdmi_spec_per_pin *per_pin,
1449 struct hdmi_eld *eld)
1450 {
1451 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1452 struct hdmi_spec *spec = codec->spec;
1453 bool old_eld_valid = pin_eld->eld_valid;
1454 bool eld_changed;
1455 int pcm_idx;
1456
1457
1458 pcm_idx = per_pin->pcm_idx;
1459 if (spec->dyn_pcm_assign) {
1460 if (eld->eld_valid) {
1461 hdmi_attach_hda_pcm(spec, per_pin);
1462 hdmi_pcm_setup_pin(spec, per_pin);
1463 } else {
1464 hdmi_pcm_reset_pin(spec, per_pin);
1465 hdmi_detach_hda_pcm(spec, per_pin);
1466 }
1467 }
1468
1469
1470
1471 if (pcm_idx == -1)
1472 pcm_idx = per_pin->pcm_idx;
1473
1474 if (eld->eld_valid)
1475 snd_hdmi_show_eld(codec, &eld->info);
1476
1477 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1478 eld_changed |= (pin_eld->monitor_present != eld->monitor_present);
1479 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid)
1480 if (pin_eld->eld_size != eld->eld_size ||
1481 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1482 eld->eld_size) != 0)
1483 eld_changed = true;
1484
1485 if (eld_changed) {
1486 pin_eld->monitor_present = eld->monitor_present;
1487 pin_eld->eld_valid = eld->eld_valid;
1488 pin_eld->eld_size = eld->eld_size;
1489 if (eld->eld_valid)
1490 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1491 eld->eld_size);
1492 pin_eld->info = eld->info;
1493 }
1494
1495
1496
1497
1498
1499
1500
1501 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1502 pin_cvt_fixup(codec, per_pin, 0);
1503 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1504 }
1505
1506 if (eld_changed && pcm_idx >= 0)
1507 snd_ctl_notify(codec->card,
1508 SNDRV_CTL_EVENT_MASK_VALUE |
1509 SNDRV_CTL_EVENT_MASK_INFO,
1510 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1511 return eld_changed;
1512 }
1513
1514
1515 static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1516 int repoll)
1517 {
1518 struct hda_jack_tbl *jack;
1519 struct hda_codec *codec = per_pin->codec;
1520 struct hdmi_spec *spec = codec->spec;
1521 struct hdmi_eld *eld = &spec->temp_eld;
1522 hda_nid_t pin_nid = per_pin->pin_nid;
1523
1524
1525
1526
1527
1528
1529
1530
1531 int present;
1532 bool ret;
1533 bool do_repoll = false;
1534
1535 present = snd_hda_pin_sense(codec, pin_nid);
1536
1537 mutex_lock(&per_pin->lock);
1538 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1539 if (eld->monitor_present)
1540 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1541 else
1542 eld->eld_valid = false;
1543
1544 codec_dbg(codec,
1545 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1546 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
1547
1548 if (eld->eld_valid) {
1549 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1550 &eld->eld_size) < 0)
1551 eld->eld_valid = false;
1552 else {
1553 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1554 eld->eld_size) < 0)
1555 eld->eld_valid = false;
1556 }
1557 if (!eld->eld_valid && repoll)
1558 do_repoll = true;
1559 }
1560
1561 if (do_repoll)
1562 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1563 else
1564 update_eld(codec, per_pin, eld);
1565
1566 ret = !repoll || !eld->monitor_present || eld->eld_valid;
1567
1568 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1569 if (jack) {
1570 jack->block_report = !ret;
1571 jack->pin_sense = (eld->monitor_present && eld->eld_valid) ?
1572 AC_PINSENSE_PRESENCE : 0;
1573 }
1574 mutex_unlock(&per_pin->lock);
1575 return ret;
1576 }
1577
1578 static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec,
1579 struct hdmi_spec_per_pin *per_pin)
1580 {
1581 struct hdmi_spec *spec = codec->spec;
1582 struct snd_jack *jack = NULL;
1583 struct hda_jack_tbl *jack_tbl;
1584
1585
1586
1587
1588
1589
1590
1591 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign)
1592 jack = spec->pcm_rec[per_pin->pcm_idx].jack;
1593 else if (!spec->dyn_pcm_assign) {
1594
1595
1596
1597
1598
1599 jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1600 if (jack_tbl)
1601 jack = jack_tbl->jack;
1602 }
1603 return jack;
1604 }
1605
1606
1607 static void sync_eld_via_acomp(struct hda_codec *codec,
1608 struct hdmi_spec_per_pin *per_pin)
1609 {
1610 struct hdmi_spec *spec = codec->spec;
1611 struct hdmi_eld *eld = &spec->temp_eld;
1612 struct snd_jack *jack = NULL;
1613 bool changed;
1614 int size;
1615
1616 mutex_lock(&per_pin->lock);
1617 eld->monitor_present = false;
1618 size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1619 per_pin->dev_id, &eld->monitor_present,
1620 eld->eld_buffer, ELD_MAX_SIZE);
1621 if (size > 0) {
1622 size = min(size, ELD_MAX_SIZE);
1623 if (snd_hdmi_parse_eld(codec, &eld->info,
1624 eld->eld_buffer, size) < 0)
1625 size = -EINVAL;
1626 }
1627
1628 if (size > 0) {
1629 eld->eld_valid = true;
1630 eld->eld_size = size;
1631 } else {
1632 eld->eld_valid = false;
1633 eld->eld_size = 0;
1634 }
1635
1636
1637
1638
1639 jack = pin_idx_to_jack(codec, per_pin);
1640 changed = update_eld(codec, per_pin, eld);
1641 if (jack == NULL)
1642 jack = pin_idx_to_jack(codec, per_pin);
1643 if (changed && jack)
1644 snd_jack_report(jack,
1645 (eld->monitor_present && eld->eld_valid) ?
1646 SND_JACK_AVOUT : 0);
1647 mutex_unlock(&per_pin->lock);
1648 }
1649
1650 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1651 {
1652 struct hda_codec *codec = per_pin->codec;
1653 int ret;
1654
1655
1656 if (!codec_has_acomp(codec)) {
1657 ret = snd_hda_power_up_pm(codec);
1658 if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) {
1659 snd_hda_power_down_pm(codec);
1660 return false;
1661 }
1662 ret = hdmi_present_sense_via_verbs(per_pin, repoll);
1663 snd_hda_power_down_pm(codec);
1664 } else {
1665 sync_eld_via_acomp(codec, per_pin);
1666 ret = false;
1667 }
1668
1669 return ret;
1670 }
1671
1672 static void hdmi_repoll_eld(struct work_struct *work)
1673 {
1674 struct hdmi_spec_per_pin *per_pin =
1675 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1676 struct hda_codec *codec = per_pin->codec;
1677 struct hdmi_spec *spec = codec->spec;
1678 struct hda_jack_tbl *jack;
1679
1680 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1681 if (jack)
1682 jack->jack_dirty = 1;
1683
1684 if (per_pin->repoll_count++ > 6)
1685 per_pin->repoll_count = 0;
1686
1687 mutex_lock(&spec->pcm_lock);
1688 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1689 snd_hda_jack_report_sync(per_pin->codec);
1690 mutex_unlock(&spec->pcm_lock);
1691 }
1692
1693 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1694 hda_nid_t nid);
1695
1696 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1697 {
1698 struct hdmi_spec *spec = codec->spec;
1699 unsigned int caps, config;
1700 int pin_idx;
1701 struct hdmi_spec_per_pin *per_pin;
1702 int err;
1703 int dev_num, i;
1704
1705 caps = snd_hda_query_pin_caps(codec, pin_nid);
1706 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1707 return 0;
1708
1709
1710
1711
1712
1713 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1714 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1715 return 0;
1716
1717
1718
1719
1720
1721 if (is_haswell_plus(codec)) {
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731 dev_num = 3;
1732 spec->dev_num = 3;
1733 } else if (spec->dyn_pcm_assign && codec->dp_mst) {
1734 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
1735
1736
1737
1738
1739 spec->dev_num = (spec->dev_num > dev_num) ?
1740 spec->dev_num : dev_num;
1741 } else {
1742
1743
1744
1745
1746
1747 dev_num = 1;
1748 spec->dev_num = 1;
1749 }
1750
1751 for (i = 0; i < dev_num; i++) {
1752 pin_idx = spec->num_pins;
1753 per_pin = snd_array_new(&spec->pins);
1754
1755 if (!per_pin)
1756 return -ENOMEM;
1757
1758 if (spec->dyn_pcm_assign) {
1759 per_pin->pcm = NULL;
1760 per_pin->pcm_idx = -1;
1761 } else {
1762 per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1763 per_pin->pcm_idx = pin_idx;
1764 }
1765 per_pin->pin_nid = pin_nid;
1766 per_pin->pin_nid_idx = spec->num_nids;
1767 per_pin->dev_id = i;
1768 per_pin->non_pcm = false;
1769 snd_hda_set_dev_select(codec, pin_nid, i);
1770 if (is_haswell_plus(codec))
1771 intel_haswell_fixup_connect_list(codec, pin_nid);
1772 err = hdmi_read_pin_conn(codec, pin_idx);
1773 if (err < 0)
1774 return err;
1775 spec->num_pins++;
1776 }
1777 spec->num_nids++;
1778
1779 return 0;
1780 }
1781
1782 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1783 {
1784 struct hdmi_spec *spec = codec->spec;
1785 struct hdmi_spec_per_cvt *per_cvt;
1786 unsigned int chans;
1787 int err;
1788
1789 chans = get_wcaps(codec, cvt_nid);
1790 chans = get_wcaps_channels(chans);
1791
1792 per_cvt = snd_array_new(&spec->cvts);
1793 if (!per_cvt)
1794 return -ENOMEM;
1795
1796 per_cvt->cvt_nid = cvt_nid;
1797 per_cvt->channels_min = 2;
1798 if (chans <= 16) {
1799 per_cvt->channels_max = chans;
1800 if (chans > spec->chmap.channels_max)
1801 spec->chmap.channels_max = chans;
1802 }
1803
1804 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1805 &per_cvt->rates,
1806 &per_cvt->formats,
1807 &per_cvt->maxbps);
1808 if (err < 0)
1809 return err;
1810
1811 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1812 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1813 spec->num_cvts++;
1814
1815 return 0;
1816 }
1817
1818 static int hdmi_parse_codec(struct hda_codec *codec)
1819 {
1820 hda_nid_t nid;
1821 int i, nodes;
1822
1823 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
1824 if (!nid || nodes < 0) {
1825 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1826 return -EINVAL;
1827 }
1828
1829 for (i = 0; i < nodes; i++, nid++) {
1830 unsigned int caps;
1831 unsigned int type;
1832
1833 caps = get_wcaps(codec, nid);
1834 type = get_wcaps_type(caps);
1835
1836 if (!(caps & AC_WCAP_DIGITAL))
1837 continue;
1838
1839 switch (type) {
1840 case AC_WID_AUD_OUT:
1841 hdmi_add_cvt(codec, nid);
1842 break;
1843 case AC_WID_PIN:
1844 hdmi_add_pin(codec, nid);
1845 break;
1846 }
1847 }
1848
1849 return 0;
1850 }
1851
1852
1853
1854 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1855 {
1856 struct hda_spdif_out *spdif;
1857 bool non_pcm;
1858
1859 mutex_lock(&codec->spdif_mutex);
1860 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1861
1862
1863
1864 if (WARN_ON(spdif == NULL)) {
1865 mutex_unlock(&codec->spdif_mutex);
1866 return true;
1867 }
1868 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1869 mutex_unlock(&codec->spdif_mutex);
1870 return non_pcm;
1871 }
1872
1873
1874
1875
1876
1877 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1878 struct hda_codec *codec,
1879 unsigned int stream_tag,
1880 unsigned int format,
1881 struct snd_pcm_substream *substream)
1882 {
1883 hda_nid_t cvt_nid = hinfo->nid;
1884 struct hdmi_spec *spec = codec->spec;
1885 int pin_idx;
1886 struct hdmi_spec_per_pin *per_pin;
1887 hda_nid_t pin_nid;
1888 struct snd_pcm_runtime *runtime = substream->runtime;
1889 bool non_pcm;
1890 int pinctl, stripe;
1891 int err = 0;
1892
1893 mutex_lock(&spec->pcm_lock);
1894 pin_idx = hinfo_to_pin_index(codec, hinfo);
1895 if (spec->dyn_pcm_assign && pin_idx < 0) {
1896
1897
1898
1899
1900 pin_cvt_fixup(codec, NULL, cvt_nid);
1901 snd_hda_codec_setup_stream(codec, cvt_nid,
1902 stream_tag, 0, format);
1903 goto unlock;
1904 }
1905
1906 if (snd_BUG_ON(pin_idx < 0)) {
1907 err = -EINVAL;
1908 goto unlock;
1909 }
1910 per_pin = get_pin(spec, pin_idx);
1911 pin_nid = per_pin->pin_nid;
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921 pin_cvt_fixup(codec, per_pin, 0);
1922
1923
1924
1925 if (codec_has_acomp(codec))
1926 snd_hdac_sync_audio_rate(&codec->core, pin_nid, per_pin->dev_id,
1927 runtime->rate);
1928
1929 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1930 mutex_lock(&per_pin->lock);
1931 per_pin->channels = substream->runtime->channels;
1932 per_pin->setup = true;
1933
1934 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) {
1935 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core,
1936 substream);
1937 snd_hda_codec_write(codec, cvt_nid, 0,
1938 AC_VERB_SET_STRIPE_CONTROL,
1939 stripe);
1940 }
1941
1942 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1943 mutex_unlock(&per_pin->lock);
1944 if (spec->dyn_pin_out) {
1945 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1946 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1947 snd_hda_codec_write(codec, pin_nid, 0,
1948 AC_VERB_SET_PIN_WIDGET_CONTROL,
1949 pinctl | PIN_OUT);
1950 }
1951
1952
1953 err = spec->ops.setup_stream(codec, cvt_nid, pin_nid,
1954 stream_tag, format);
1955 unlock:
1956 mutex_unlock(&spec->pcm_lock);
1957 return err;
1958 }
1959
1960 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1961 struct hda_codec *codec,
1962 struct snd_pcm_substream *substream)
1963 {
1964 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1965 return 0;
1966 }
1967
1968 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1969 struct hda_codec *codec,
1970 struct snd_pcm_substream *substream)
1971 {
1972 struct hdmi_spec *spec = codec->spec;
1973 int cvt_idx, pin_idx, pcm_idx;
1974 struct hdmi_spec_per_cvt *per_cvt;
1975 struct hdmi_spec_per_pin *per_pin;
1976 int pinctl;
1977 int err = 0;
1978
1979 if (hinfo->nid) {
1980 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1981 if (snd_BUG_ON(pcm_idx < 0))
1982 return -EINVAL;
1983 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1984 if (snd_BUG_ON(cvt_idx < 0))
1985 return -EINVAL;
1986 per_cvt = get_cvt(spec, cvt_idx);
1987
1988 snd_BUG_ON(!per_cvt->assigned);
1989 per_cvt->assigned = 0;
1990 hinfo->nid = 0;
1991
1992 azx_stream(get_azx_dev(substream))->stripe = 0;
1993
1994 mutex_lock(&spec->pcm_lock);
1995 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1996 clear_bit(pcm_idx, &spec->pcm_in_use);
1997 pin_idx = hinfo_to_pin_index(codec, hinfo);
1998 if (spec->dyn_pcm_assign && pin_idx < 0)
1999 goto unlock;
2000
2001 if (snd_BUG_ON(pin_idx < 0)) {
2002 err = -EINVAL;
2003 goto unlock;
2004 }
2005 per_pin = get_pin(spec, pin_idx);
2006
2007 if (spec->dyn_pin_out) {
2008 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
2009 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2010 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
2011 AC_VERB_SET_PIN_WIDGET_CONTROL,
2012 pinctl & ~PIN_OUT);
2013 }
2014
2015 mutex_lock(&per_pin->lock);
2016 per_pin->chmap_set = false;
2017 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
2018
2019 per_pin->setup = false;
2020 per_pin->channels = 0;
2021 mutex_unlock(&per_pin->lock);
2022 unlock:
2023 mutex_unlock(&spec->pcm_lock);
2024 }
2025
2026 return err;
2027 }
2028
2029 static const struct hda_pcm_ops generic_ops = {
2030 .open = hdmi_pcm_open,
2031 .close = hdmi_pcm_close,
2032 .prepare = generic_hdmi_playback_pcm_prepare,
2033 .cleanup = generic_hdmi_playback_pcm_cleanup,
2034 };
2035
2036 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
2037 {
2038 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2039 struct hdmi_spec *spec = codec->spec;
2040 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2041
2042 if (!per_pin)
2043 return 0;
2044
2045 return per_pin->sink_eld.info.spk_alloc;
2046 }
2047
2048 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
2049 unsigned char *chmap)
2050 {
2051 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2052 struct hdmi_spec *spec = codec->spec;
2053 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2054
2055
2056 if (!per_pin)
2057 return;
2058
2059 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
2060 }
2061
2062 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
2063 unsigned char *chmap, int prepared)
2064 {
2065 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2066 struct hdmi_spec *spec = codec->spec;
2067 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2068
2069 if (!per_pin)
2070 return;
2071 mutex_lock(&per_pin->lock);
2072 per_pin->chmap_set = true;
2073 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
2074 if (prepared)
2075 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2076 mutex_unlock(&per_pin->lock);
2077 }
2078
2079 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
2080 {
2081 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2082 struct hdmi_spec *spec = codec->spec;
2083 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2084
2085 return per_pin ? true:false;
2086 }
2087
2088 static int generic_hdmi_build_pcms(struct hda_codec *codec)
2089 {
2090 struct hdmi_spec *spec = codec->spec;
2091 int idx;
2092
2093
2094
2095
2096
2097
2098
2099 for (idx = 0; idx < spec->num_nids + spec->dev_num - 1; idx++) {
2100 struct hda_pcm *info;
2101 struct hda_pcm_stream *pstr;
2102
2103 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
2104 if (!info)
2105 return -ENOMEM;
2106
2107 spec->pcm_rec[idx].pcm = info;
2108 spec->pcm_used++;
2109 info->pcm_type = HDA_PCM_TYPE_HDMI;
2110 info->own_chmap = true;
2111
2112 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2113 pstr->substreams = 1;
2114 pstr->ops = generic_ops;
2115
2116 if (spec->pcm_used >= 16)
2117 break;
2118
2119 }
2120
2121 return 0;
2122 }
2123
2124 static void free_hdmi_jack_priv(struct snd_jack *jack)
2125 {
2126 struct hdmi_pcm *pcm = jack->private_data;
2127
2128 pcm->jack = NULL;
2129 }
2130
2131 static int add_hdmi_jack_kctl(struct hda_codec *codec,
2132 struct hdmi_spec *spec,
2133 int pcm_idx,
2134 const char *name)
2135 {
2136 struct snd_jack *jack;
2137 int err;
2138
2139 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack,
2140 true, false);
2141 if (err < 0)
2142 return err;
2143
2144 spec->pcm_rec[pcm_idx].jack = jack;
2145 jack->private_data = &spec->pcm_rec[pcm_idx];
2146 jack->private_free = free_hdmi_jack_priv;
2147 return 0;
2148 }
2149
2150 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
2151 {
2152 char hdmi_str[32] = "HDMI/DP";
2153 struct hdmi_spec *spec = codec->spec;
2154 struct hdmi_spec_per_pin *per_pin;
2155 struct hda_jack_tbl *jack;
2156 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
2157 bool phantom_jack;
2158 int ret;
2159
2160 if (pcmdev > 0)
2161 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2162
2163 if (spec->dyn_pcm_assign)
2164 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str);
2165
2166
2167
2168
2169
2170
2171 per_pin = get_pin(spec, pcm_idx);
2172 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
2173 if (phantom_jack)
2174 strncat(hdmi_str, " Phantom",
2175 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2176 ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
2177 phantom_jack, 0, NULL);
2178 if (ret < 0)
2179 return ret;
2180 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
2181 if (jack == NULL)
2182 return 0;
2183
2184
2185
2186 spec->pcm_rec[pcm_idx].jack = jack->jack;
2187 return 0;
2188 }
2189
2190 static int generic_hdmi_build_controls(struct hda_codec *codec)
2191 {
2192 struct hdmi_spec *spec = codec->spec;
2193 int dev, err;
2194 int pin_idx, pcm_idx;
2195
2196 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2197 if (!get_pcm_rec(spec, pcm_idx)->pcm) {
2198
2199 set_bit(pcm_idx, &spec->pcm_bitmap);
2200 continue;
2201 }
2202
2203 err = generic_hdmi_build_jack(codec, pcm_idx);
2204 if (err < 0)
2205 return err;
2206
2207
2208
2209
2210 if (spec->dyn_pcm_assign)
2211 err = snd_hda_create_dig_out_ctls(codec,
2212 0, spec->cvt_nids[0],
2213 HDA_PCM_TYPE_HDMI);
2214 else {
2215 struct hdmi_spec_per_pin *per_pin =
2216 get_pin(spec, pcm_idx);
2217 err = snd_hda_create_dig_out_ctls(codec,
2218 per_pin->pin_nid,
2219 per_pin->mux_nids[0],
2220 HDA_PCM_TYPE_HDMI);
2221 }
2222 if (err < 0)
2223 return err;
2224 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2225
2226 dev = get_pcm_rec(spec, pcm_idx)->device;
2227 if (dev != SNDRV_PCM_INVALID_DEVICE) {
2228
2229 err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
2230 if (err < 0)
2231 return err;
2232 }
2233 }
2234
2235 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2236 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2237 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
2238
2239 pin_eld->eld_valid = false;
2240 hdmi_present_sense(per_pin, 0);
2241 }
2242
2243
2244 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2245 struct hda_pcm *pcm;
2246
2247 pcm = get_pcm_rec(spec, pcm_idx);
2248 if (!pcm || !pcm->pcm)
2249 break;
2250 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2251 if (err < 0)
2252 return err;
2253 }
2254
2255 return 0;
2256 }
2257
2258 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2259 {
2260 struct hdmi_spec *spec = codec->spec;
2261 int pin_idx;
2262
2263 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2264 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2265
2266 per_pin->codec = codec;
2267 mutex_init(&per_pin->lock);
2268 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2269 eld_proc_new(per_pin, pin_idx);
2270 }
2271 return 0;
2272 }
2273
2274 static int generic_hdmi_init(struct hda_codec *codec)
2275 {
2276 struct hdmi_spec *spec = codec->spec;
2277 int pin_idx;
2278
2279 mutex_lock(&spec->bind_lock);
2280 spec->use_jack_detect = !codec->jackpoll_interval;
2281 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2282 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2283 hda_nid_t pin_nid = per_pin->pin_nid;
2284 int dev_id = per_pin->dev_id;
2285
2286 snd_hda_set_dev_select(codec, pin_nid, dev_id);
2287 hdmi_init_pin(codec, pin_nid);
2288 if (codec_has_acomp(codec))
2289 continue;
2290 if (spec->use_jack_detect)
2291 snd_hda_jack_detect_enable(codec, pin_nid);
2292 else
2293 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2294 jack_callback);
2295 }
2296 mutex_unlock(&spec->bind_lock);
2297 return 0;
2298 }
2299
2300 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2301 {
2302 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2303 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2304 }
2305
2306 static void hdmi_array_free(struct hdmi_spec *spec)
2307 {
2308 snd_array_free(&spec->pins);
2309 snd_array_free(&spec->cvts);
2310 }
2311
2312 static void generic_spec_free(struct hda_codec *codec)
2313 {
2314 struct hdmi_spec *spec = codec->spec;
2315
2316 if (spec) {
2317 hdmi_array_free(spec);
2318 kfree(spec);
2319 codec->spec = NULL;
2320 }
2321 codec->dp_mst = false;
2322 }
2323
2324 static void generic_hdmi_free(struct hda_codec *codec)
2325 {
2326 struct hdmi_spec *spec = codec->spec;
2327 int pin_idx, pcm_idx;
2328
2329 if (spec->acomp_registered) {
2330 snd_hdac_acomp_exit(&codec->bus->core);
2331 } else if (codec_has_acomp(codec)) {
2332 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL);
2333 codec->relaxed_resume = 0;
2334 }
2335
2336 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2337 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2338 cancel_delayed_work_sync(&per_pin->work);
2339 eld_proc_free(per_pin);
2340 }
2341
2342 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2343 if (spec->pcm_rec[pcm_idx].jack == NULL)
2344 continue;
2345 if (spec->dyn_pcm_assign)
2346 snd_device_free(codec->card,
2347 spec->pcm_rec[pcm_idx].jack);
2348 else
2349 spec->pcm_rec[pcm_idx].jack = NULL;
2350 }
2351
2352 generic_spec_free(codec);
2353 }
2354
2355 #ifdef CONFIG_PM
2356 static int generic_hdmi_resume(struct hda_codec *codec)
2357 {
2358 struct hdmi_spec *spec = codec->spec;
2359 int pin_idx;
2360
2361 codec->patch_ops.init(codec);
2362 snd_hda_regmap_sync(codec);
2363
2364 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2365 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2366 hdmi_present_sense(per_pin, 1);
2367 }
2368 return 0;
2369 }
2370 #endif
2371
2372 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2373 .init = generic_hdmi_init,
2374 .free = generic_hdmi_free,
2375 .build_pcms = generic_hdmi_build_pcms,
2376 .build_controls = generic_hdmi_build_controls,
2377 .unsol_event = hdmi_unsol_event,
2378 #ifdef CONFIG_PM
2379 .resume = generic_hdmi_resume,
2380 #endif
2381 };
2382
2383 static const struct hdmi_ops generic_standard_hdmi_ops = {
2384 .pin_get_eld = snd_hdmi_get_eld,
2385 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2386 .pin_hbr_setup = hdmi_pin_hbr_setup,
2387 .setup_stream = hdmi_setup_stream,
2388 };
2389
2390
2391 static int alloc_generic_hdmi(struct hda_codec *codec)
2392 {
2393 struct hdmi_spec *spec;
2394
2395 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2396 if (!spec)
2397 return -ENOMEM;
2398
2399 spec->codec = codec;
2400 spec->ops = generic_standard_hdmi_ops;
2401 spec->dev_num = 1;
2402 mutex_init(&spec->pcm_lock);
2403 mutex_init(&spec->bind_lock);
2404 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2405
2406 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2407 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2408 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2409 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc,
2410
2411 codec->spec = spec;
2412 hdmi_array_init(spec, 4);
2413
2414 codec->patch_ops = generic_hdmi_patch_ops;
2415
2416 return 0;
2417 }
2418
2419
2420 static int patch_generic_hdmi(struct hda_codec *codec)
2421 {
2422 int err;
2423
2424 err = alloc_generic_hdmi(codec);
2425 if (err < 0)
2426 return err;
2427
2428 err = hdmi_parse_codec(codec);
2429 if (err < 0) {
2430 generic_spec_free(codec);
2431 return err;
2432 }
2433
2434 generic_hdmi_init_per_pins(codec);
2435 return 0;
2436 }
2437
2438
2439
2440
2441
2442
2443 static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid,
2444 bool use_acomp)
2445 {
2446 struct hda_jack_tbl *tbl;
2447
2448 tbl = snd_hda_jack_tbl_get(codec, nid);
2449 if (tbl) {
2450
2451
2452
2453 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag);
2454 snd_hda_codec_write_cache(codec, nid, 0,
2455 AC_VERB_SET_UNSOLICITED_ENABLE, val);
2456 } else {
2457
2458
2459
2460 if (!use_acomp)
2461 snd_hda_jack_detect_enable(codec, nid);
2462 }
2463 }
2464
2465
2466 static void generic_acomp_notifier_set(struct drm_audio_component *acomp,
2467 bool use_acomp)
2468 {
2469 struct hdmi_spec *spec;
2470 int i;
2471
2472 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops);
2473 mutex_lock(&spec->bind_lock);
2474 spec->use_acomp_notifier = use_acomp;
2475 spec->codec->relaxed_resume = use_acomp;
2476
2477 if (spec->use_jack_detect) {
2478 for (i = 0; i < spec->num_pins; i++)
2479 reprogram_jack_detect(spec->codec,
2480 get_pin(spec, i)->pin_nid,
2481 use_acomp);
2482 }
2483 mutex_unlock(&spec->bind_lock);
2484 }
2485
2486
2487 static int generic_acomp_master_bind(struct device *dev,
2488 struct drm_audio_component *acomp)
2489 {
2490 generic_acomp_notifier_set(acomp, true);
2491 return 0;
2492 }
2493
2494 static void generic_acomp_master_unbind(struct device *dev,
2495 struct drm_audio_component *acomp)
2496 {
2497 generic_acomp_notifier_set(acomp, false);
2498 }
2499
2500
2501 static int match_bound_vga(struct device *dev, int subtype, void *data)
2502 {
2503 struct hdac_bus *bus = data;
2504 struct pci_dev *pci, *master;
2505
2506 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev))
2507 return 0;
2508 master = to_pci_dev(bus->dev);
2509 pci = to_pci_dev(dev);
2510 return master->bus == pci->bus;
2511 }
2512
2513
2514 static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id)
2515 {
2516 struct hda_codec *codec = audio_ptr;
2517 struct hdmi_spec *spec = codec->spec;
2518 hda_nid_t pin_nid = spec->port2pin(codec, port);
2519
2520 if (!pin_nid)
2521 return;
2522 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN)
2523 return;
2524
2525
2526
2527 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2528 return;
2529
2530 if (snd_hdac_is_in_pm(&codec->core))
2531 return;
2532
2533 check_presence_and_report(codec, pin_nid, dev_id);
2534 }
2535
2536
2537 static void setup_drm_audio_ops(struct hda_codec *codec,
2538 const struct drm_audio_component_audio_ops *ops)
2539 {
2540 struct hdmi_spec *spec = codec->spec;
2541
2542 spec->drm_audio_ops.audio_ptr = codec;
2543
2544
2545
2546
2547 wmb();
2548 spec->drm_audio_ops.pin2port = ops->pin2port;
2549 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify;
2550 spec->drm_audio_ops.master_bind = ops->master_bind;
2551 spec->drm_audio_ops.master_unbind = ops->master_unbind;
2552 }
2553
2554
2555 static void generic_acomp_init(struct hda_codec *codec,
2556 const struct drm_audio_component_audio_ops *ops,
2557 int (*port2pin)(struct hda_codec *, int))
2558 {
2559 struct hdmi_spec *spec = codec->spec;
2560
2561 if (!enable_acomp) {
2562 codec_info(codec, "audio component disabled by module option\n");
2563 return;
2564 }
2565
2566 spec->port2pin = port2pin;
2567 setup_drm_audio_ops(codec, ops);
2568 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops,
2569 match_bound_vga, 0)) {
2570 spec->acomp_registered = true;
2571 codec->bus->keep_power = 0;
2572 }
2573 }
2574
2575
2576
2577
2578
2579 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2580 hda_nid_t nid)
2581 {
2582 struct hdmi_spec *spec = codec->spec;
2583 hda_nid_t conns[4];
2584 int nconns;
2585
2586 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2587 if (nconns == spec->num_cvts &&
2588 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2589 return;
2590
2591
2592 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2593 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2594 }
2595
2596 #define INTEL_GET_VENDOR_VERB 0xf81
2597 #define INTEL_SET_VENDOR_VERB 0x781
2598 #define INTEL_EN_DP12 0x02
2599 #define INTEL_EN_ALL_PIN_CVTS 0x01
2600
2601 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2602 bool update_tree)
2603 {
2604 unsigned int vendor_param;
2605 struct hdmi_spec *spec = codec->spec;
2606
2607 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2608 INTEL_GET_VENDOR_VERB, 0);
2609 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2610 return;
2611
2612 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2613 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2614 INTEL_SET_VENDOR_VERB, vendor_param);
2615 if (vendor_param == -1)
2616 return;
2617
2618 if (update_tree)
2619 snd_hda_codec_update_widgets(codec);
2620 }
2621
2622 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2623 {
2624 unsigned int vendor_param;
2625 struct hdmi_spec *spec = codec->spec;
2626
2627 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2628 INTEL_GET_VENDOR_VERB, 0);
2629 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2630 return;
2631
2632
2633 vendor_param |= INTEL_EN_DP12;
2634 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2635 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
2636 INTEL_SET_VENDOR_VERB, vendor_param);
2637 }
2638
2639
2640
2641
2642 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2643 unsigned int power_state)
2644 {
2645 if (power_state == AC_PWRST_D0) {
2646 intel_haswell_enable_all_pins(codec, false);
2647 intel_haswell_fixup_enable_dp12(codec);
2648 }
2649
2650 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2651 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2652 }
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665 static int intel_base_nid(struct hda_codec *codec)
2666 {
2667 switch (codec->core.vendor_id) {
2668 case 0x80860054:
2669 case 0x80862804:
2670 case 0x80862882:
2671 return 4;
2672 default:
2673 return 5;
2674 }
2675 }
2676
2677 static int intel_pin2port(void *audio_ptr, int pin_nid)
2678 {
2679 struct hda_codec *codec = audio_ptr;
2680 struct hdmi_spec *spec = codec->spec;
2681 int base_nid, i;
2682
2683 if (!spec->port_num) {
2684 base_nid = intel_base_nid(codec);
2685 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3))
2686 return -1;
2687 return pin_nid - base_nid + 1;
2688 }
2689
2690
2691
2692
2693
2694 for (i = 0; i < spec->port_num; i++) {
2695 if (pin_nid == spec->port_map[i])
2696 return i + 1;
2697 }
2698
2699
2700 codec_info(codec, "Can't find the HDMI/DP port for pin %d\n", pin_nid);
2701 return -1;
2702 }
2703
2704 static int intel_port2pin(struct hda_codec *codec, int port)
2705 {
2706 struct hdmi_spec *spec = codec->spec;
2707
2708 if (!spec->port_num) {
2709
2710 if (port < 1 || port > 3)
2711 return 0;
2712
2713 return port + intel_base_nid(codec) - 1;
2714 }
2715
2716 if (port < 1 || port > spec->port_num)
2717 return 0;
2718 return spec->port_map[port - 1];
2719 }
2720
2721 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
2722 {
2723 struct hda_codec *codec = audio_ptr;
2724 int pin_nid;
2725 int dev_id = pipe;
2726
2727 pin_nid = intel_port2pin(codec, port);
2728 if (!pin_nid)
2729 return;
2730
2731
2732
2733 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2734 return;
2735
2736 if (snd_hdac_is_in_pm(&codec->core))
2737 return;
2738
2739 snd_hdac_i915_set_bclk(&codec->bus->core);
2740 check_presence_and_report(codec, pin_nid, dev_id);
2741 }
2742
2743 static const struct drm_audio_component_audio_ops intel_audio_ops = {
2744 .pin2port = intel_pin2port,
2745 .pin_eld_notify = intel_pin_eld_notify,
2746 };
2747
2748
2749 static void register_i915_notifier(struct hda_codec *codec)
2750 {
2751 struct hdmi_spec *spec = codec->spec;
2752
2753 spec->use_acomp_notifier = true;
2754 spec->port2pin = intel_port2pin;
2755 setup_drm_audio_ops(codec, &intel_audio_ops);
2756 snd_hdac_acomp_register_notifier(&codec->bus->core,
2757 &spec->drm_audio_ops);
2758
2759 codec->relaxed_resume = 1;
2760 }
2761
2762
2763 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2764 hda_nid_t pin_nid, u32 stream_tag, int format)
2765 {
2766 haswell_verify_D0(codec, cvt_nid, pin_nid);
2767 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
2768 }
2769
2770
2771 static void i915_pin_cvt_fixup(struct hda_codec *codec,
2772 struct hdmi_spec_per_pin *per_pin,
2773 hda_nid_t cvt_nid)
2774 {
2775 if (per_pin) {
2776 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2777 per_pin->dev_id);
2778 intel_verify_pin_cvt_connect(codec, per_pin);
2779 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
2780 per_pin->dev_id, per_pin->mux_idx);
2781 } else {
2782 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
2783 }
2784 }
2785
2786
2787 static int alloc_intel_hdmi(struct hda_codec *codec)
2788 {
2789 int err;
2790
2791
2792 if (!codec->bus->core.audio_component) {
2793 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
2794
2795 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE;
2796 return -ENODEV;
2797 }
2798
2799 err = alloc_generic_hdmi(codec);
2800 if (err < 0)
2801 return err;
2802
2803 codec->patch_ops.unsol_event = NULL;
2804 return 0;
2805 }
2806
2807
2808 static int parse_intel_hdmi(struct hda_codec *codec)
2809 {
2810 int err, retries = 3;
2811
2812 do {
2813 err = hdmi_parse_codec(codec);
2814 } while (err < 0 && retries--);
2815
2816 if (err < 0) {
2817 generic_spec_free(codec);
2818 return err;
2819 }
2820
2821 generic_hdmi_init_per_pins(codec);
2822 register_i915_notifier(codec);
2823 return 0;
2824 }
2825
2826
2827 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid,
2828 const int *port_map, int port_num)
2829 {
2830 struct hdmi_spec *spec;
2831 int err;
2832
2833 err = alloc_intel_hdmi(codec);
2834 if (err < 0)
2835 return err;
2836 spec = codec->spec;
2837 codec->dp_mst = true;
2838 spec->dyn_pcm_assign = true;
2839 spec->vendor_nid = vendor_nid;
2840 spec->port_map = port_map;
2841 spec->port_num = port_num;
2842
2843 intel_haswell_enable_all_pins(codec, true);
2844 intel_haswell_fixup_enable_dp12(codec);
2845
2846 codec->display_power_control = 1;
2847
2848 codec->patch_ops.set_power_state = haswell_set_power_state;
2849 codec->depop_delay = 0;
2850 codec->auto_runtime_pm = 1;
2851
2852 spec->ops.setup_stream = i915_hsw_setup_stream;
2853 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2854
2855 return parse_intel_hdmi(codec);
2856 }
2857
2858 static int patch_i915_hsw_hdmi(struct hda_codec *codec)
2859 {
2860 return intel_hsw_common_init(codec, 0x08, NULL, 0);
2861 }
2862
2863 static int patch_i915_glk_hdmi(struct hda_codec *codec)
2864 {
2865 return intel_hsw_common_init(codec, 0x0b, NULL, 0);
2866 }
2867
2868 static int patch_i915_icl_hdmi(struct hda_codec *codec)
2869 {
2870
2871
2872
2873
2874 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb};
2875
2876 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map));
2877 }
2878
2879 static int patch_i915_tgl_hdmi(struct hda_codec *codec)
2880 {
2881
2882
2883
2884
2885 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf};
2886
2887 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map));
2888 }
2889
2890
2891
2892 static int patch_i915_byt_hdmi(struct hda_codec *codec)
2893 {
2894 struct hdmi_spec *spec;
2895 int err;
2896
2897 err = alloc_intel_hdmi(codec);
2898 if (err < 0)
2899 return err;
2900 spec = codec->spec;
2901
2902
2903
2904
2905 codec->display_power_control = 1;
2906
2907 codec->depop_delay = 0;
2908 codec->auto_runtime_pm = 1;
2909
2910 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2911
2912 return parse_intel_hdmi(codec);
2913 }
2914
2915
2916 static int patch_i915_cpt_hdmi(struct hda_codec *codec)
2917 {
2918 int err;
2919
2920 err = alloc_intel_hdmi(codec);
2921 if (err < 0)
2922 return err;
2923 return parse_intel_hdmi(codec);
2924 }
2925
2926
2927
2928
2929
2930 static int simple_playback_build_pcms(struct hda_codec *codec)
2931 {
2932 struct hdmi_spec *spec = codec->spec;
2933 struct hda_pcm *info;
2934 unsigned int chans;
2935 struct hda_pcm_stream *pstr;
2936 struct hdmi_spec_per_cvt *per_cvt;
2937
2938 per_cvt = get_cvt(spec, 0);
2939 chans = get_wcaps(codec, per_cvt->cvt_nid);
2940 chans = get_wcaps_channels(chans);
2941
2942 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2943 if (!info)
2944 return -ENOMEM;
2945 spec->pcm_rec[0].pcm = info;
2946 info->pcm_type = HDA_PCM_TYPE_HDMI;
2947 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2948 *pstr = spec->pcm_playback;
2949 pstr->nid = per_cvt->cvt_nid;
2950 if (pstr->channels_max <= 2 && chans && chans <= 16)
2951 pstr->channels_max = chans;
2952
2953 return 0;
2954 }
2955
2956
2957 static void simple_hdmi_unsol_event(struct hda_codec *codec,
2958 unsigned int res)
2959 {
2960 snd_hda_jack_set_dirty_all(codec);
2961 snd_hda_jack_report_sync(codec);
2962 }
2963
2964
2965
2966
2967 #define simple_hdmi_build_jack generic_hdmi_build_jack
2968
2969 static int simple_playback_build_controls(struct hda_codec *codec)
2970 {
2971 struct hdmi_spec *spec = codec->spec;
2972 struct hdmi_spec_per_cvt *per_cvt;
2973 int err;
2974
2975 per_cvt = get_cvt(spec, 0);
2976 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2977 per_cvt->cvt_nid,
2978 HDA_PCM_TYPE_HDMI);
2979 if (err < 0)
2980 return err;
2981 return simple_hdmi_build_jack(codec, 0);
2982 }
2983
2984 static int simple_playback_init(struct hda_codec *codec)
2985 {
2986 struct hdmi_spec *spec = codec->spec;
2987 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2988 hda_nid_t pin = per_pin->pin_nid;
2989
2990 snd_hda_codec_write(codec, pin, 0,
2991 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2992
2993 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2994 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2995 AMP_OUT_UNMUTE);
2996 snd_hda_jack_detect_enable(codec, pin);
2997 return 0;
2998 }
2999
3000 static void simple_playback_free(struct hda_codec *codec)
3001 {
3002 struct hdmi_spec *spec = codec->spec;
3003
3004 hdmi_array_free(spec);
3005 kfree(spec);
3006 }
3007
3008
3009
3010
3011
3012 #define Nv_VERB_SET_Channel_Allocation 0xF79
3013 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
3014 #define Nv_VERB_SET_Audio_Protection_On 0xF98
3015 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
3016
3017 #define nvhdmi_master_con_nid_7x 0x04
3018 #define nvhdmi_master_pin_nid_7x 0x05
3019
3020 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
3021
3022 0x6, 0x8, 0xa, 0xc,
3023 };
3024
3025 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
3026
3027 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3028
3029 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3030 {}
3031 };
3032
3033 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
3034
3035 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3036
3037 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3038 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3039 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3040 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3041 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3042 {}
3043 };
3044
3045 #ifdef LIMITED_RATE_FMT_SUPPORT
3046
3047 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
3048 #define SUPPORTED_MAXBPS 16
3049 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
3050 #else
3051
3052 #define SUPPORTED_RATES \
3053 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
3054 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
3055 SNDRV_PCM_RATE_192000)
3056 #define SUPPORTED_MAXBPS 24
3057 #define SUPPORTED_FORMATS \
3058 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
3059 #endif
3060
3061 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
3062 {
3063 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
3064 return 0;
3065 }
3066
3067 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
3068 {
3069 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
3070 return 0;
3071 }
3072
3073 static const unsigned int channels_2_6_8[] = {
3074 2, 6, 8
3075 };
3076
3077 static const unsigned int channels_2_8[] = {
3078 2, 8
3079 };
3080
3081 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
3082 .count = ARRAY_SIZE(channels_2_6_8),
3083 .list = channels_2_6_8,
3084 .mask = 0,
3085 };
3086
3087 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
3088 .count = ARRAY_SIZE(channels_2_8),
3089 .list = channels_2_8,
3090 .mask = 0,
3091 };
3092
3093 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
3094 struct hda_codec *codec,
3095 struct snd_pcm_substream *substream)
3096 {
3097 struct hdmi_spec *spec = codec->spec;
3098 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
3099
3100 switch (codec->preset->vendor_id) {
3101 case 0x10de0002:
3102 case 0x10de0003:
3103 case 0x10de0005:
3104 case 0x10de0006:
3105 hw_constraints_channels = &hw_constraints_2_8_channels;
3106 break;
3107 case 0x10de0007:
3108 hw_constraints_channels = &hw_constraints_2_6_8_channels;
3109 break;
3110 default:
3111 break;
3112 }
3113
3114 if (hw_constraints_channels != NULL) {
3115 snd_pcm_hw_constraint_list(substream->runtime, 0,
3116 SNDRV_PCM_HW_PARAM_CHANNELS,
3117 hw_constraints_channels);
3118 } else {
3119 snd_pcm_hw_constraint_step(substream->runtime, 0,
3120 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
3121 }
3122
3123 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3124 }
3125
3126 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
3127 struct hda_codec *codec,
3128 struct snd_pcm_substream *substream)
3129 {
3130 struct hdmi_spec *spec = codec->spec;
3131 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3132 }
3133
3134 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3135 struct hda_codec *codec,
3136 unsigned int stream_tag,
3137 unsigned int format,
3138 struct snd_pcm_substream *substream)
3139 {
3140 struct hdmi_spec *spec = codec->spec;
3141 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3142 stream_tag, format, substream);
3143 }
3144
3145 static const struct hda_pcm_stream simple_pcm_playback = {
3146 .substreams = 1,
3147 .channels_min = 2,
3148 .channels_max = 2,
3149 .ops = {
3150 .open = simple_playback_pcm_open,
3151 .close = simple_playback_pcm_close,
3152 .prepare = simple_playback_pcm_prepare
3153 },
3154 };
3155
3156 static const struct hda_codec_ops simple_hdmi_patch_ops = {
3157 .build_controls = simple_playback_build_controls,
3158 .build_pcms = simple_playback_build_pcms,
3159 .init = simple_playback_init,
3160 .free = simple_playback_free,
3161 .unsol_event = simple_hdmi_unsol_event,
3162 };
3163
3164 static int patch_simple_hdmi(struct hda_codec *codec,
3165 hda_nid_t cvt_nid, hda_nid_t pin_nid)
3166 {
3167 struct hdmi_spec *spec;
3168 struct hdmi_spec_per_cvt *per_cvt;
3169 struct hdmi_spec_per_pin *per_pin;
3170
3171 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
3172 if (!spec)
3173 return -ENOMEM;
3174
3175 spec->codec = codec;
3176 codec->spec = spec;
3177 hdmi_array_init(spec, 1);
3178
3179 spec->multiout.num_dacs = 0;
3180 spec->multiout.max_channels = 2;
3181 spec->multiout.dig_out_nid = cvt_nid;
3182 spec->num_cvts = 1;
3183 spec->num_pins = 1;
3184 per_pin = snd_array_new(&spec->pins);
3185 per_cvt = snd_array_new(&spec->cvts);
3186 if (!per_pin || !per_cvt) {
3187 simple_playback_free(codec);
3188 return -ENOMEM;
3189 }
3190 per_cvt->cvt_nid = cvt_nid;
3191 per_pin->pin_nid = pin_nid;
3192 spec->pcm_playback = simple_pcm_playback;
3193
3194 codec->patch_ops = simple_hdmi_patch_ops;
3195
3196 return 0;
3197 }
3198
3199 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
3200 int channels)
3201 {
3202 unsigned int chanmask;
3203 int chan = channels ? (channels - 1) : 1;
3204
3205 switch (channels) {
3206 default:
3207 case 0:
3208 case 2:
3209 chanmask = 0x00;
3210 break;
3211 case 4:
3212 chanmask = 0x08;
3213 break;
3214 case 6:
3215 chanmask = 0x0b;
3216 break;
3217 case 8:
3218 chanmask = 0x13;
3219 break;
3220 }
3221
3222
3223
3224 snd_hda_codec_write(codec, 0x1, 0,
3225 Nv_VERB_SET_Channel_Allocation, chanmask);
3226
3227 snd_hda_codec_write(codec, 0x1, 0,
3228 Nv_VERB_SET_Info_Frame_Checksum,
3229 (0x71 - chan - chanmask));
3230 }
3231
3232 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
3233 struct hda_codec *codec,
3234 struct snd_pcm_substream *substream)
3235 {
3236 struct hdmi_spec *spec = codec->spec;
3237 int i;
3238
3239 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
3240 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
3241 for (i = 0; i < 4; i++) {
3242
3243 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3244 AC_VERB_SET_CHANNEL_STREAMID, 0);
3245
3246 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3247 AC_VERB_SET_STREAM_FORMAT, 0);
3248 }
3249
3250
3251
3252 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3253
3254 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3255 }
3256
3257 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
3258 struct hda_codec *codec,
3259 unsigned int stream_tag,
3260 unsigned int format,
3261 struct snd_pcm_substream *substream)
3262 {
3263 int chs;
3264 unsigned int dataDCC2, channel_id;
3265 int i;
3266 struct hdmi_spec *spec = codec->spec;
3267 struct hda_spdif_out *spdif;
3268 struct hdmi_spec_per_cvt *per_cvt;
3269
3270 mutex_lock(&codec->spdif_mutex);
3271 per_cvt = get_cvt(spec, 0);
3272 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
3273
3274 chs = substream->runtime->channels;
3275
3276 dataDCC2 = 0x2;
3277
3278
3279 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
3280 snd_hda_codec_write(codec,
3281 nvhdmi_master_con_nid_7x,
3282 0,
3283 AC_VERB_SET_DIGI_CONVERT_1,
3284 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3285
3286
3287 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3288 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3289
3290
3291 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3292 AC_VERB_SET_STREAM_FORMAT, format);
3293
3294
3295
3296 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
3297 snd_hda_codec_write(codec,
3298 nvhdmi_master_con_nid_7x,
3299 0,
3300 AC_VERB_SET_DIGI_CONVERT_1,
3301 spdif->ctls & 0xff);
3302 snd_hda_codec_write(codec,
3303 nvhdmi_master_con_nid_7x,
3304 0,
3305 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3306 }
3307
3308 for (i = 0; i < 4; i++) {
3309 if (chs == 2)
3310 channel_id = 0;
3311 else
3312 channel_id = i * 2;
3313
3314
3315
3316
3317 if (codec->spdif_status_reset &&
3318 (spdif->ctls & AC_DIG1_ENABLE))
3319 snd_hda_codec_write(codec,
3320 nvhdmi_con_nids_7x[i],
3321 0,
3322 AC_VERB_SET_DIGI_CONVERT_1,
3323 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3324
3325 snd_hda_codec_write(codec,
3326 nvhdmi_con_nids_7x[i],
3327 0,
3328 AC_VERB_SET_CHANNEL_STREAMID,
3329 (stream_tag << 4) | channel_id);
3330
3331 snd_hda_codec_write(codec,
3332 nvhdmi_con_nids_7x[i],
3333 0,
3334 AC_VERB_SET_STREAM_FORMAT,
3335 format);
3336
3337
3338 if (codec->spdif_status_reset &&
3339 (spdif->ctls & AC_DIG1_ENABLE)) {
3340 snd_hda_codec_write(codec,
3341 nvhdmi_con_nids_7x[i],
3342 0,
3343 AC_VERB_SET_DIGI_CONVERT_1,
3344 spdif->ctls & 0xff);
3345 snd_hda_codec_write(codec,
3346 nvhdmi_con_nids_7x[i],
3347 0,
3348 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3349 }
3350 }
3351
3352 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
3353
3354 mutex_unlock(&codec->spdif_mutex);
3355 return 0;
3356 }
3357
3358 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
3359 .substreams = 1,
3360 .channels_min = 2,
3361 .channels_max = 8,
3362 .nid = nvhdmi_master_con_nid_7x,
3363 .rates = SUPPORTED_RATES,
3364 .maxbps = SUPPORTED_MAXBPS,
3365 .formats = SUPPORTED_FORMATS,
3366 .ops = {
3367 .open = simple_playback_pcm_open,
3368 .close = nvhdmi_8ch_7x_pcm_close,
3369 .prepare = nvhdmi_8ch_7x_pcm_prepare
3370 },
3371 };
3372
3373 static int patch_nvhdmi_2ch(struct hda_codec *codec)
3374 {
3375 struct hdmi_spec *spec;
3376 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3377 nvhdmi_master_pin_nid_7x);
3378 if (err < 0)
3379 return err;
3380
3381 codec->patch_ops.init = nvhdmi_7x_init_2ch;
3382
3383 spec = codec->spec;
3384 spec->pcm_playback.rates = SUPPORTED_RATES;
3385 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3386 spec->pcm_playback.formats = SUPPORTED_FORMATS;
3387 return 0;
3388 }
3389
3390 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3391 {
3392 struct hdmi_spec *spec = codec->spec;
3393 int err = simple_playback_build_pcms(codec);
3394 if (!err) {
3395 struct hda_pcm *info = get_pcm_rec(spec, 0);
3396 info->own_chmap = true;
3397 }
3398 return err;
3399 }
3400
3401 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3402 {
3403 struct hdmi_spec *spec = codec->spec;
3404 struct hda_pcm *info;
3405 struct snd_pcm_chmap *chmap;
3406 int err;
3407
3408 err = simple_playback_build_controls(codec);
3409 if (err < 0)
3410 return err;
3411
3412
3413 info = get_pcm_rec(spec, 0);
3414 err = snd_pcm_add_chmap_ctls(info->pcm,
3415 SNDRV_PCM_STREAM_PLAYBACK,
3416 snd_pcm_alt_chmaps, 8, 0, &chmap);
3417 if (err < 0)
3418 return err;
3419 switch (codec->preset->vendor_id) {
3420 case 0x10de0002:
3421 case 0x10de0003:
3422 case 0x10de0005:
3423 case 0x10de0006:
3424 chmap->channel_mask = (1U << 2) | (1U << 8);
3425 break;
3426 case 0x10de0007:
3427 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3428 }
3429 return 0;
3430 }
3431
3432 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3433 {
3434 struct hdmi_spec *spec;
3435 int err = patch_nvhdmi_2ch(codec);
3436 if (err < 0)
3437 return err;
3438 spec = codec->spec;
3439 spec->multiout.max_channels = 8;
3440 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
3441 codec->patch_ops.init = nvhdmi_7x_init_8ch;
3442 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3443 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
3444
3445
3446
3447 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3448
3449 return 0;
3450 }
3451
3452
3453
3454
3455
3456
3457 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
3458 struct hdac_cea_channel_speaker_allocation *cap, int channels)
3459 {
3460 if (cap->ca_index == 0x00 && channels == 2)
3461 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3462
3463
3464 if (cap->channels != channels)
3465 return -1;
3466
3467
3468 return SNDRV_CTL_TLVT_CHMAP_VAR;
3469 }
3470
3471 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3472 int ca, int chs, unsigned char *map)
3473 {
3474 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3475 return -EINVAL;
3476
3477 return 0;
3478 }
3479
3480 static int patch_nvhdmi(struct hda_codec *codec)
3481 {
3482 struct hdmi_spec *spec;
3483 int err;
3484
3485 err = patch_generic_hdmi(codec);
3486 if (err)
3487 return err;
3488
3489 spec = codec->spec;
3490 spec->dyn_pin_out = true;
3491
3492 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3493 nvhdmi_chmap_cea_alloc_validate_get_type;
3494 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3495
3496 codec->link_down_at_suspend = 1;
3497
3498 return 0;
3499 }
3500
3501
3502
3503
3504
3505
3506
3507
3508 #define NVIDIA_AFG_NID 0x01
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525 #define NVIDIA_GET_SCRATCH0 0xfa6
3526 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3527 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3528 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3529 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3530 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3531 #define NVIDIA_SCRATCH_VALID (1 << 6)
3532
3533 #define NVIDIA_GET_SCRATCH1 0xfab
3534 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3535 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3536 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3537 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3538
3539
3540
3541
3542
3543 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3544 {
3545 unsigned int value;
3546
3547
3548 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3549 NVIDIA_GET_SCRATCH0, 0);
3550 value = (value >> 24) & 0xff;
3551
3552
3553 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3554 NVIDIA_SET_SCRATCH0_BYTE0,
3555 (format >> 0) & 0xff);
3556 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3557 NVIDIA_SET_SCRATCH0_BYTE1,
3558 (format >> 8) & 0xff);
3559
3560
3561 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3562 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3563
3564
3565
3566
3567
3568 if (format == 0)
3569 value &= ~NVIDIA_SCRATCH_VALID;
3570 else
3571 value |= NVIDIA_SCRATCH_VALID;
3572
3573
3574
3575
3576
3577
3578 value ^= NVIDIA_SCRATCH_TRIGGER;
3579
3580 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3581 NVIDIA_SET_SCRATCH0_BYTE3, value);
3582 }
3583
3584 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3585 struct hda_codec *codec,
3586 unsigned int stream_tag,
3587 unsigned int format,
3588 struct snd_pcm_substream *substream)
3589 {
3590 int err;
3591
3592 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3593 format, substream);
3594 if (err < 0)
3595 return err;
3596
3597
3598 tegra_hdmi_set_format(codec, format);
3599
3600 return 0;
3601 }
3602
3603 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3604 struct hda_codec *codec,
3605 struct snd_pcm_substream *substream)
3606 {
3607
3608 tegra_hdmi_set_format(codec, 0);
3609
3610 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3611 }
3612
3613 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3614 {
3615 struct hdmi_spec *spec = codec->spec;
3616 unsigned int i;
3617
3618 for (i = 0; i < spec->num_pins; i++) {
3619 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3620
3621 if (pcm->pcm_type == type)
3622 return pcm;
3623 }
3624
3625 return NULL;
3626 }
3627
3628 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3629 {
3630 struct hda_pcm_stream *stream;
3631 struct hda_pcm *pcm;
3632 int err;
3633
3634 err = generic_hdmi_build_pcms(codec);
3635 if (err < 0)
3636 return err;
3637
3638 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3639 if (!pcm)
3640 return -ENODEV;
3641
3642
3643
3644
3645
3646 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3647 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3648 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3649
3650 return 0;
3651 }
3652
3653 static int patch_tegra_hdmi(struct hda_codec *codec)
3654 {
3655 int err;
3656
3657 err = patch_generic_hdmi(codec);
3658 if (err)
3659 return err;
3660
3661 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3662
3663 return 0;
3664 }
3665
3666
3667
3668
3669
3670 #define is_amdhdmi_rev3_or_later(codec) \
3671 ((codec)->core.vendor_id == 0x1002aa01 && \
3672 ((codec)->core.revision_id & 0xff00) >= 0x0300)
3673 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3674
3675
3676 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3677 #define ATI_VERB_SET_DOWNMIX_INFO 0x772
3678 #define ATI_VERB_SET_MULTICHANNEL_01 0x777
3679 #define ATI_VERB_SET_MULTICHANNEL_23 0x778
3680 #define ATI_VERB_SET_MULTICHANNEL_45 0x779
3681 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
3682 #define ATI_VERB_SET_HBR_CONTROL 0x77c
3683 #define ATI_VERB_SET_MULTICHANNEL_1 0x785
3684 #define ATI_VERB_SET_MULTICHANNEL_3 0x786
3685 #define ATI_VERB_SET_MULTICHANNEL_5 0x787
3686 #define ATI_VERB_SET_MULTICHANNEL_7 0x788
3687 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3688 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3689 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3690 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3691 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3692 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3693 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
3694 #define ATI_VERB_GET_HBR_CONTROL 0xf7c
3695 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3696 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3697 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3698 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3699 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3700
3701
3702 #define ATI_VERB_SET_RAMP_RATE 0x770
3703 #define ATI_VERB_GET_RAMP_RATE 0xf70
3704
3705 #define ATI_OUT_ENABLE 0x1
3706
3707 #define ATI_MULTICHANNEL_MODE_PAIRED 0
3708 #define ATI_MULTICHANNEL_MODE_SINGLE 1
3709
3710 #define ATI_HBR_CAPABLE 0x01
3711 #define ATI_HBR_ENABLE 0x10
3712
3713 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3714 unsigned char *buf, int *eld_size)
3715 {
3716
3717 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3718 is_amdhdmi_rev3_or_later(codec));
3719 }
3720
3721 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3722 int active_channels, int conn_type)
3723 {
3724 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3725 }
3726
3727 static int atihdmi_paired_swap_fc_lfe(int pos)
3728 {
3729
3730
3731
3732
3733
3734 switch (pos) {
3735
3736 case 2: return 3;
3737 case 3: return 2;
3738 default: break;
3739 }
3740
3741 return pos;
3742 }
3743
3744 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3745 int ca, int chs, unsigned char *map)
3746 {
3747 struct hdac_cea_channel_speaker_allocation *cap;
3748 int i, j;
3749
3750
3751
3752 cap = snd_hdac_get_ch_alloc_from_ca(ca);
3753 for (i = 0; i < chs; ++i) {
3754 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
3755 bool ok = false;
3756 bool companion_ok = false;
3757
3758 if (!mask)
3759 continue;
3760
3761 for (j = 0 + i % 2; j < 8; j += 2) {
3762 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3763 if (cap->speakers[chan_idx] == mask) {
3764
3765 ok = true;
3766
3767 if (i % 2 == 0 && i + 1 < chs) {
3768
3769 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3770 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
3771 int comp_mask_act = cap->speakers[comp_chan_idx];
3772
3773 if (comp_mask_req == comp_mask_act)
3774 companion_ok = true;
3775 else
3776 return -EINVAL;
3777 }
3778 break;
3779 }
3780 }
3781
3782 if (!ok)
3783 return -EINVAL;
3784
3785 if (companion_ok)
3786 i++;
3787 }
3788
3789 return 0;
3790 }
3791
3792 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
3793 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
3794 {
3795 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3796 int verb;
3797 int ati_channel_setup = 0;
3798
3799 if (hdmi_slot > 7)
3800 return -EINVAL;
3801
3802 if (!has_amd_full_remap_support(codec)) {
3803 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3804
3805
3806
3807
3808
3809 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3810 return 0;
3811
3812 hdmi_slot -= hdmi_slot % 2;
3813
3814 if (stream_channel != 0xf)
3815 stream_channel -= stream_channel % 2;
3816 }
3817
3818 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3819
3820
3821
3822 if (stream_channel != 0xf)
3823 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3824
3825 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3826 }
3827
3828 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
3829 hda_nid_t pin_nid, int asp_slot)
3830 {
3831 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3832 bool was_odd = false;
3833 int ati_asp_slot = asp_slot;
3834 int verb;
3835 int ati_channel_setup;
3836
3837 if (asp_slot > 7)
3838 return -EINVAL;
3839
3840 if (!has_amd_full_remap_support(codec)) {
3841 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3842 if (ati_asp_slot % 2 != 0) {
3843 ati_asp_slot -= 1;
3844 was_odd = true;
3845 }
3846 }
3847
3848 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3849
3850 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3851
3852 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3853 return 0xf;
3854
3855 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3856 }
3857
3858 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3859 struct hdac_chmap *chmap,
3860 struct hdac_cea_channel_speaker_allocation *cap,
3861 int channels)
3862 {
3863 int c;
3864
3865
3866
3867
3868
3869
3870
3871 int chanpairs = 0;
3872
3873
3874 if ((channels % 2) != 0)
3875 return -1;
3876
3877 for (c = 0; c < 7; c += 2) {
3878 if (cap->speakers[c] || cap->speakers[c+1])
3879 chanpairs++;
3880 }
3881
3882 if (chanpairs * 2 != channels)
3883 return -1;
3884
3885 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3886 }
3887
3888 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
3889 struct hdac_cea_channel_speaker_allocation *cap,
3890 unsigned int *chmap, int channels)
3891 {
3892
3893 int count = 0;
3894 int c;
3895
3896 for (c = 7; c >= 0; c--) {
3897 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3898 int spk = cap->speakers[chan];
3899 if (!spk) {
3900
3901 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3902 chmap[count++] = SNDRV_CHMAP_NA;
3903
3904 continue;
3905 }
3906
3907 chmap[count++] = snd_hdac_spk_to_chmap(spk);
3908 }
3909
3910 WARN_ON(count != channels);
3911 }
3912
3913 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3914 bool hbr)
3915 {
3916 int hbr_ctl, hbr_ctl_new;
3917
3918 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3919 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3920 if (hbr)
3921 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3922 else
3923 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3924
3925 codec_dbg(codec,
3926 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3927 pin_nid,
3928 hbr_ctl == hbr_ctl_new ? "" : "new-",
3929 hbr_ctl_new);
3930
3931 if (hbr_ctl != hbr_ctl_new)
3932 snd_hda_codec_write(codec, pin_nid, 0,
3933 ATI_VERB_SET_HBR_CONTROL,
3934 hbr_ctl_new);
3935
3936 } else if (hbr)
3937 return -EINVAL;
3938
3939 return 0;
3940 }
3941
3942 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3943 hda_nid_t pin_nid, u32 stream_tag, int format)
3944 {
3945
3946 if (is_amdhdmi_rev3_or_later(codec)) {
3947 int ramp_rate = 180;
3948
3949 if (format & AC_FMT_TYPE_NON_PCM)
3950 ramp_rate = 0;
3951
3952 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3953 }
3954
3955 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3956 }
3957
3958
3959 static int atihdmi_init(struct hda_codec *codec)
3960 {
3961 struct hdmi_spec *spec = codec->spec;
3962 int pin_idx, err;
3963
3964 err = generic_hdmi_init(codec);
3965
3966 if (err)
3967 return err;
3968
3969 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3970 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3971
3972
3973 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3974
3975
3976 if (has_amd_full_remap_support(codec))
3977 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3978 ATI_VERB_SET_MULTICHANNEL_MODE,
3979 ATI_MULTICHANNEL_MODE_SINGLE);
3980 }
3981
3982 return 0;
3983 }
3984
3985
3986
3987 static int atihdmi_pin2port(void *audio_ptr, int pin_nid)
3988 {
3989 return pin_nid / 2 - 1;
3990 }
3991
3992
3993 static int atihdmi_port2pin(struct hda_codec *codec, int port)
3994 {
3995 return port * 2 + 3;
3996 }
3997
3998 static const struct drm_audio_component_audio_ops atihdmi_audio_ops = {
3999 .pin2port = atihdmi_pin2port,
4000 .pin_eld_notify = generic_acomp_pin_eld_notify,
4001 .master_bind = generic_acomp_master_bind,
4002 .master_unbind = generic_acomp_master_unbind,
4003 };
4004
4005 static int patch_atihdmi(struct hda_codec *codec)
4006 {
4007 struct hdmi_spec *spec;
4008 struct hdmi_spec_per_cvt *per_cvt;
4009 int err, cvt_idx;
4010
4011 err = patch_generic_hdmi(codec);
4012
4013 if (err)
4014 return err;
4015
4016 codec->patch_ops.init = atihdmi_init;
4017
4018 spec = codec->spec;
4019
4020 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
4021 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
4022 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
4023 spec->ops.setup_stream = atihdmi_setup_stream;
4024
4025 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
4026 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
4027
4028 if (!has_amd_full_remap_support(codec)) {
4029
4030 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
4031 atihdmi_paired_chmap_cea_alloc_validate_get_type;
4032 spec->chmap.ops.cea_alloc_to_tlv_chmap =
4033 atihdmi_paired_cea_alloc_to_tlv_chmap;
4034 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
4035 }
4036
4037
4038 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
4039 per_cvt = get_cvt(spec, cvt_idx);
4040 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
4041 per_cvt->rates |= SUPPORTED_RATES;
4042 per_cvt->formats |= SUPPORTED_FORMATS;
4043 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
4044 }
4045
4046 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
4047
4048
4049
4050
4051 codec->link_down_at_suspend = 1;
4052
4053 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin);
4054
4055 return 0;
4056 }
4057
4058
4059 #define VIAHDMI_CVT_NID 0x02
4060 #define VIAHDMI_PIN_NID 0x03
4061
4062 static int patch_via_hdmi(struct hda_codec *codec)
4063 {
4064 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
4065 }
4066
4067
4068
4069
4070 static const struct hda_device_id snd_hda_id_hdmi[] = {
4071 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
4072 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
4073 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
4074 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
4075 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
4076 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
4077 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
4078 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch),
4079 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4080 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4081 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x),
4082 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4083 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4084 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
4085 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi),
4086 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi),
4087 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi),
4088 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi),
4089 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi),
4090 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi),
4091 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi),
4092 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi),
4093 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi),
4094 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi),
4095 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi),
4096 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi),
4097 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi),
4098
4099 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi),
4100 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi),
4101 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi),
4102 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi),
4103 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi),
4104 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
4105 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
4106 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
4107 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
4108 HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi),
4109 HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi),
4110 HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi),
4111 HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi),
4112 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
4113 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
4114 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
4115 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
4116 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
4117 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi),
4118 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi),
4119 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
4120 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi),
4121 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
4122 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi),
4123 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi),
4124 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
4125 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
4126 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
4127 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
4128 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi),
4129 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi),
4130 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi),
4131 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi),
4132 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi),
4133 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
4134 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi),
4135 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi),
4136 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi),
4137 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
4138 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
4139 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi),
4140 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi),
4141 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi),
4142 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi),
4143 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi),
4144 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi),
4145 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi),
4146 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi),
4147 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi),
4148 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi),
4149 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
4150 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch),
4151 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
4152 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
4153 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
4154 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
4155 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi),
4156 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi),
4157 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
4158 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
4159 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
4160 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi),
4161 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
4162 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
4163 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi),
4164 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi),
4165 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi),
4166 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi),
4167 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi),
4168 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi),
4169 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi),
4170 HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi),
4171 HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi),
4172 HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI", patch_i915_icl_hdmi),
4173 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
4174 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
4175 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
4176 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
4177
4178 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
4179 {}
4180 };
4181 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
4182
4183 MODULE_LICENSE("GPL");
4184 MODULE_DESCRIPTION("HDMI HD-audio codec");
4185 MODULE_ALIAS("snd-hda-codec-intelhdmi");
4186 MODULE_ALIAS("snd-hda-codec-nvhdmi");
4187 MODULE_ALIAS("snd-hda-codec-atihdmi");
4188
4189 static struct hda_codec_driver hdmi_driver = {
4190 .id = snd_hda_id_hdmi,
4191 };
4192
4193 module_hda_codec_driver(hdmi_driver);