1
2 #ifndef __SOUND_VT1724_H
3 #define __SOUND_VT1724_H
4
5
6
7
8
9
10
11 #include <sound/control.h>
12 #include <sound/ac97_codec.h>
13 #include <sound/rawmidi.h>
14 #include <sound/i2c.h>
15 #include <sound/pcm.h>
16
17 #include "ice1712.h"
18
19 enum {
20 ICE_EEP2_SYSCONF = 0,
21 ICE_EEP2_ACLINK,
22 ICE_EEP2_I2S,
23 ICE_EEP2_SPDIF,
24 ICE_EEP2_GPIO_DIR,
25 ICE_EEP2_GPIO_DIR1,
26 ICE_EEP2_GPIO_DIR2,
27 ICE_EEP2_GPIO_MASK,
28 ICE_EEP2_GPIO_MASK1,
29 ICE_EEP2_GPIO_MASK2,
30 ICE_EEP2_GPIO_STATE,
31 ICE_EEP2_GPIO_STATE1,
32 ICE_EEP2_GPIO_STATE2
33 };
34
35
36
37
38
39 #define ICEREG1724(ice, x) ((ice)->port + VT1724_REG_##x)
40
41 #define VT1724_REG_CONTROL 0x00
42 #define VT1724_RESET 0x80
43 #define VT1724_REG_IRQMASK 0x01
44 #define VT1724_IRQ_MPU_RX 0x80
45 #define VT1724_IRQ_MPU_TX 0x20
46 #define VT1724_IRQ_MTPCM 0x10
47 #define VT1724_REG_IRQSTAT 0x02
48
49 #define VT1724_REG_SYS_CFG 0x04
50 #define VT1724_CFG_CLOCK 0xc0
51 #define VT1724_CFG_CLOCK512 0x00
52 #define VT1724_CFG_CLOCK384 0x40
53 #define VT1724_CFG_MPU401 0x20
54 #define VT1724_CFG_ADC_MASK 0x0c
55 #define VT1724_CFG_ADC_NONE 0x0c
56 #define VT1724_CFG_DAC_MASK 0x03
57
58 #define VT1724_REG_AC97_CFG 0x05
59 #define VT1724_CFG_PRO_I2S 0x80
60 #define VT1724_CFG_AC97_PACKED 0x01
61
62 #define VT1724_REG_I2S_FEATURES 0x06
63 #define VT1724_CFG_I2S_VOLUME 0x80
64 #define VT1724_CFG_I2S_96KHZ 0x40
65 #define VT1724_CFG_I2S_RESMASK 0x30
66 #define VT1724_CFG_I2S_192KHZ 0x08
67 #define VT1724_CFG_I2S_OTHER 0x07
68
69 #define VT1724_REG_SPDIF_CFG 0x07
70 #define VT1724_CFG_SPDIF_OUT_EN 0x80
71 #define VT1724_CFG_SPDIF_OUT_INT 0x40
72 #define VT1724_CFG_I2S_CHIPID 0x3c
73 #define VT1724_CFG_SPDIF_IN 0x02
74 #define VT1724_CFG_SPDIF_OUT 0x01
75
76
77
78
79
80 #define VT1724_REG_MPU_TXFIFO 0x0a
81 #define VT1724_REG_MPU_RXFIFO 0x0b
82
83 #define VT1724_REG_MPU_DATA 0x0c
84 #define VT1724_REG_MPU_CTRL 0x0d
85 #define VT1724_MPU_UART 0x01
86 #define VT1724_MPU_TX_EMPTY 0x02
87 #define VT1724_MPU_TX_FULL 0x04
88 #define VT1724_MPU_RX_EMPTY 0x08
89 #define VT1724_MPU_RX_FULL 0x10
90
91 #define VT1724_REG_MPU_FIFO_WM 0x0e
92 #define VT1724_MPU_RX_FIFO 0x20
93 #define VT1724_MPU_FIFO_MASK 0x1f
94
95 #define VT1724_REG_I2C_DEV_ADDR 0x10
96 #define VT1724_I2C_WRITE 0x01
97 #define VT1724_REG_I2C_BYTE_ADDR 0x11
98 #define VT1724_REG_I2C_DATA 0x12
99 #define VT1724_REG_I2C_CTRL 0x13
100 #define VT1724_I2C_EEPROM 0x80
101 #define VT1724_I2C_BUSY 0x01
102
103 #define VT1724_REG_GPIO_DATA 0x14
104 #define VT1724_REG_GPIO_WRITE_MASK 0x16
105 #define VT1724_REG_GPIO_DIRECTION 0x18
106
107
108 #define VT1724_REG_POWERDOWN 0x1c
109 #define VT1724_REG_GPIO_DATA_22 0x1e
110 #define VT1724_REG_GPIO_WRITE_MASK_22 0x1f
111
112
113
114
115
116
117 #define ICEMT1724(ice, x) ((ice)->profi_port + VT1724_MT_##x)
118
119 #define VT1724_MT_IRQ 0x00
120 #define VT1724_MULTI_PDMA4 0x80
121 #define VT1724_MULTI_PDMA3 0x40
122 #define VT1724_MULTI_PDMA2 0x20
123 #define VT1724_MULTI_PDMA1 0x10
124 #define VT1724_MULTI_FIFO_ERR 0x08
125 #define VT1724_MULTI_RDMA1 0x04
126 #define VT1724_MULTI_RDMA0 0x02
127 #define VT1724_MULTI_PDMA0 0x01
128
129 #define VT1724_MT_RATE 0x01
130 #define VT1724_SPDIF_MASTER 0x10
131 #define VT1724_MT_I2S_FORMAT 0x02
132 #define VT1724_MT_I2S_MCLK_128X 0x08
133 #define VT1724_MT_I2S_FORMAT_MASK 0x03
134 #define VT1724_MT_I2S_FORMAT_I2S 0x00
135 #define VT1724_MT_DMA_INT_MASK 0x03
136
137 #define VT1724_MT_AC97_INDEX 0x04
138 #define VT1724_MT_AC97_CMD 0x05
139 #define VT1724_AC97_COLD 0x80
140 #define VT1724_AC97_WARM 0x40
141 #define VT1724_AC97_WRITE 0x20
142 #define VT1724_AC97_READ 0x10
143 #define VT1724_AC97_READY 0x08
144 #define VT1724_AC97_ID_MASK 0x03
145 #define VT1724_MT_AC97_DATA 0x06
146 #define VT1724_MT_PLAYBACK_ADDR 0x10
147 #define VT1724_MT_PLAYBACK_SIZE 0x14
148 #define VT1724_MT_DMA_CONTROL 0x18
149 #define VT1724_PDMA4_START 0x80
150 #define VT1724_PDMA3_START 0x40
151 #define VT1724_PDMA2_START 0x20
152 #define VT1724_PDMA1_START 0x10
153 #define VT1724_RDMA1_START 0x04
154 #define VT1724_RDMA0_START 0x02
155 #define VT1724_PDMA0_START 0x01
156 #define VT1724_MT_BURST 0x19
157 #define VT1724_MT_DMA_FIFO_ERR 0x1a
158 #define VT1724_PDMA4_UNDERRUN 0x80
159 #define VT1724_PDMA2_UNDERRUN 0x40
160 #define VT1724_PDMA3_UNDERRUN 0x20
161 #define VT1724_PDMA1_UNDERRUN 0x10
162 #define VT1724_RDMA1_UNDERRUN 0x04
163 #define VT1724_RDMA0_UNDERRUN 0x02
164 #define VT1724_PDMA0_UNDERRUN 0x01
165 #define VT1724_MT_DMA_PAUSE 0x1b
166 #define VT1724_PDMA4_PAUSE 0x80
167 #define VT1724_PDMA3_PAUSE 0x40
168 #define VT1724_PDMA2_PAUSE 0x20
169 #define VT1724_PDMA1_PAUSE 0x10
170 #define VT1724_RDMA1_PAUSE 0x04
171 #define VT1724_RDMA0_PAUSE 0x02
172 #define VT1724_PDMA0_PAUSE 0x01
173 #define VT1724_MT_PLAYBACK_COUNT 0x1c
174 #define VT1724_MT_CAPTURE_ADDR 0x20
175 #define VT1724_MT_CAPTURE_SIZE 0x24
176 #define VT1724_MT_CAPTURE_COUNT 0x26
177
178 #define VT1724_MT_ROUTE_PLAYBACK 0x2c
179
180 #define VT1724_MT_RDMA1_ADDR 0x30
181 #define VT1724_MT_RDMA1_SIZE 0x34
182 #define VT1724_MT_RDMA1_COUNT 0x36
183
184 #define VT1724_MT_SPDIF_CTRL 0x3c
185 #define VT1724_MT_MONITOR_PEAKINDEX 0x3e
186 #define VT1724_MT_MONITOR_PEAKDATA 0x3f
187
188
189 #define VT1724_MT_PDMA4_ADDR 0x40
190 #define VT1724_MT_PDMA4_SIZE 0x44
191 #define VT1724_MT_PDMA4_COUNT 0x46
192 #define VT1724_MT_PDMA3_ADDR 0x50
193 #define VT1724_MT_PDMA3_SIZE 0x54
194 #define VT1724_MT_PDMA3_COUNT 0x56
195 #define VT1724_MT_PDMA2_ADDR 0x60
196 #define VT1724_MT_PDMA2_SIZE 0x64
197 #define VT1724_MT_PDMA2_COUNT 0x66
198 #define VT1724_MT_PDMA1_ADDR 0x70
199 #define VT1724_MT_PDMA1_SIZE 0x74
200 #define VT1724_MT_PDMA1_COUNT 0x76
201
202
203 unsigned char snd_vt1724_read_i2c(struct snd_ice1712 *ice, unsigned char dev, unsigned char addr);
204 void snd_vt1724_write_i2c(struct snd_ice1712 *ice, unsigned char dev, unsigned char addr, unsigned char data);
205
206 #endif