root/sound/pci/echoaudio/darla20_dsp.c

DEFINITIONS

1. init_hw
2. set_mixer_defaults
3. detect_input_clocks
4. load_asic
5. set_sample_rate

   1 /***************************************************************************
   2 
   3    Copyright Echo Digital Audio Corporation (c) 1998 - 2004
   4    All rights reserved
   5    www.echoaudio.com
   6 
   7    This file is part of Echo Digital Audio's generic driver library.
   8 
   9    Echo Digital Audio's generic driver library is free software;
  10    you can redistribute it and/or modify it under the terms of
  11    the GNU General Public License as published by the Free Software
  12    Foundation.
  13 
  14    This program is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18 
  19    You should have received a copy of the GNU General Public License
  20    along with this program; if not, write to the Free Software
  21    Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  22    MA  02111-1307, USA.
  23 
  24    *************************************************************************
  25 
  26  Translation from C++ and adaptation for use in ALSA-Driver
  27  were made by Giuliano Pochini <pochini@shiny.it>
  28 
  29 ****************************************************************************/
  30 
  31 
  32 static int init_hw(struct echoaudio *chip, u16 device_id, u16 subdevice_id)
  33 {
  34         int err;
  35 
  36         if (snd_BUG_ON((subdevice_id & 0xfff0) != DARLA20))
  37                 return -ENODEV;
  38 
  39         if ((err = init_dsp_comm_page(chip))) {
  40                 dev_err(chip->card->dev,
  41                         "init_hw: could not initialize DSP comm page\n");
  42                 return err;
  43         }
  44 
  45         chip->device_id = device_id;
  46         chip->subdevice_id = subdevice_id;
  47         chip->bad_board = true;
  48         chip->dsp_code_to_load = FW_DARLA20_DSP;
  49         chip->spdif_status = GD_SPDIF_STATUS_UNDEF;
  50         chip->clock_state = GD_CLOCK_UNDEF;
  51         /* Since this card has no ASIC, mark it as loaded so everything
  52            works OK */
  53         chip->asic_loaded = true;
  54         chip->input_clock_types = ECHO_CLOCK_BIT_INTERNAL;
  55 
  56         if ((err = load_firmware(chip)) < 0)
  57                 return err;
  58         chip->bad_board = false;
  59 
  60         return err;
  61 }
  62 
  63 
  64 
  65 static int set_mixer_defaults(struct echoaudio *chip)
  66 {
  67         return init_line_levels(chip);
  68 }
  69 
  70 
  71 
  72 /* The Darla20 has no external clock sources */
  73 static u32 detect_input_clocks(const struct echoaudio *chip)
  74 {
  75         return ECHO_CLOCK_BIT_INTERNAL;
  76 }
  77 
  78 
  79 
  80 /* The Darla20 has no ASIC. Just do nothing */
  81 static int load_asic(struct echoaudio *chip)
  82 {
  83         return 0;
  84 }
  85 
  86 
  87 
  88 static int set_sample_rate(struct echoaudio *chip, u32 rate)
  89 {
  90         u8 clock_state, spdif_status;
  91 
  92         if (wait_handshake(chip))
  93                 return -EIO;
  94 
  95         switch (rate) {
  96         case 44100:
  97                 clock_state = GD_CLOCK_44;
  98                 spdif_status = GD_SPDIF_STATUS_44;
  99                 break;
 100         case 48000:
 101                 clock_state = GD_CLOCK_48;
 102                 spdif_status = GD_SPDIF_STATUS_48;
 103                 break;
 104         default:
 105                 clock_state = GD_CLOCK_NOCHANGE;
 106                 spdif_status = GD_SPDIF_STATUS_NOCHANGE;
 107                 break;
 108         }
 109 
 110         if (chip->clock_state == clock_state)
 111                 clock_state = GD_CLOCK_NOCHANGE;
 112         if (spdif_status == chip->spdif_status)
 113                 spdif_status = GD_SPDIF_STATUS_NOCHANGE;
 114 
 115         chip->comm_page->sample_rate = cpu_to_le32(rate);
 116         chip->comm_page->gd_clock_state = clock_state;
 117         chip->comm_page->gd_spdif_status = spdif_status;
 118         chip->comm_page->gd_resampler_state = 3;        /* magic number - should always be 3 */
 119 
 120         /* Save the new audio state if it changed */
 121         if (clock_state != GD_CLOCK_NOCHANGE)
 122                 chip->clock_state = clock_state;
 123         if (spdif_status != GD_SPDIF_STATUS_NOCHANGE)
 124                 chip->spdif_status = spdif_status;
 125         chip->sample_rate = rate;
 126 
 127         clear_handshake(chip);
 128         return send_vector(chip, DSP_VC_SET_GD_AUDIO_STATE);
 129 }