This source file includes following definitions.
- snd_cs46xx_codec_read
- snd_cs46xx_ac97_read
- snd_cs46xx_codec_write
- snd_cs46xx_ac97_write
- snd_cs46xx_download
- memcpy_le32
- free_module_desc
- load_firmware
- snd_cs46xx_clear_BA1
- load_firmware
- snd_cs46xx_download_image
- snd_cs46xx_reset
- cs46xx_wait_for_fifo
- snd_cs46xx_clear_serial_FIFOs
- snd_cs46xx_proc_start
- snd_cs46xx_proc_stop
- snd_cs46xx_set_play_sample_rate
- snd_cs46xx_set_capture_sample_rate
- snd_cs46xx_pb_trans_copy
- snd_cs46xx_playback_transfer
- snd_cs46xx_cp_trans_copy
- snd_cs46xx_capture_transfer
- snd_cs46xx_playback_direct_pointer
- snd_cs46xx_playback_indirect_pointer
- snd_cs46xx_capture_direct_pointer
- snd_cs46xx_capture_indirect_pointer
- snd_cs46xx_playback_trigger
- snd_cs46xx_capture_trigger
- _cs46xx_adjust_sample_rate
- snd_cs46xx_playback_hw_params
- snd_cs46xx_playback_hw_free
- snd_cs46xx_playback_prepare
- snd_cs46xx_capture_hw_params
- snd_cs46xx_capture_hw_free
- snd_cs46xx_capture_prepare
- snd_cs46xx_interrupt
- snd_cs46xx_pcm_free_substream
- _cs46xx_playback_open_channel
- snd_cs46xx_playback_open
- snd_cs46xx_playback_open_rear
- snd_cs46xx_playback_open_clfe
- snd_cs46xx_playback_open_iec958
- snd_cs46xx_playback_close_iec958
- snd_cs46xx_capture_open
- snd_cs46xx_playback_close
- snd_cs46xx_capture_close
- snd_cs46xx_pcm
- snd_cs46xx_pcm_rear
- snd_cs46xx_pcm_center_lfe
- snd_cs46xx_pcm_iec958
- snd_cs46xx_mixer_free_ac97_bus
- snd_cs46xx_mixer_free_ac97
- snd_cs46xx_vol_info
- snd_cs46xx_vol_get
- snd_cs46xx_vol_put
- snd_cs46xx_vol_dac_get
- snd_cs46xx_vol_dac_put
- snd_cs46xx_vol_iec958_get
- snd_cs46xx_vol_iec958_put
- snd_cs46xx_iec958_get
- snd_cs46xx_iec958_put
- snd_cs46xx_adc_capture_get
- snd_cs46xx_adc_capture_put
- snd_cs46xx_pcm_capture_get
- snd_cs46xx_pcm_capture_put
- snd_herc_spdif_select_get
- snd_herc_spdif_select_put
- snd_cs46xx_spdif_info
- snd_cs46xx_spdif_default_get
- snd_cs46xx_spdif_default_put
- snd_cs46xx_spdif_mask_get
- snd_cs46xx_spdif_stream_get
- snd_cs46xx_spdif_stream_put
- snd_cs46xx_front_dup_get
- snd_cs46xx_front_dup_put
- snd_cs46xx_codec_reset
- cs46xx_detect_codec
- snd_cs46xx_mixer
- snd_cs46xx_midi_reset
- snd_cs46xx_midi_input_open
- snd_cs46xx_midi_input_close
- snd_cs46xx_midi_output_open
- snd_cs46xx_midi_output_close
- snd_cs46xx_midi_input_trigger
- snd_cs46xx_midi_output_trigger
- snd_cs46xx_midi
- snd_cs46xx_gameport_trigger
- snd_cs46xx_gameport_read
- snd_cs46xx_gameport_cooked_read
- snd_cs46xx_gameport_open
- snd_cs46xx_gameport
- snd_cs46xx_remove_gameport
- snd_cs46xx_gameport
- snd_cs46xx_remove_gameport
- snd_cs46xx_io_read
- snd_cs46xx_proc_init
- snd_cs46xx_proc_done
- snd_cs46xx_hw_stop
- snd_cs46xx_free
- snd_cs46xx_dev_free
- snd_cs46xx_chip_init
- cs46xx_enable_stream_irqs
- snd_cs46xx_start_dsp
- amp_none
- voyetra_setup_eapd_slot
- amp_voyetra
- hercules_init
- amp_hercules
- voyetra_mixer_init
- hercules_mixer_init
- amp_voyetra_4294
- clkrun_hack
- clkrun_init
- snd_cs46xx_suspend
- snd_cs46xx_resume
- snd_cs46xx_create
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34 #include <linux/delay.h>
35 #include <linux/pci.h>
36 #include <linux/pm.h>
37 #include <linux/init.h>
38 #include <linux/interrupt.h>
39 #include <linux/slab.h>
40 #include <linux/gameport.h>
41 #include <linux/mutex.h>
42 #include <linux/export.h>
43 #include <linux/module.h>
44 #include <linux/firmware.h>
45 #include <linux/vmalloc.h>
46 #include <linux/io.h>
47
48 #include <sound/core.h>
49 #include <sound/control.h>
50 #include <sound/info.h>
51 #include <sound/pcm.h>
52 #include <sound/pcm_params.h>
53 #include "cs46xx.h"
54
55 #include "cs46xx_lib.h"
56 #include "dsp_spos.h"
57
58 static void amp_voyetra(struct snd_cs46xx *chip, int change);
59
60 #ifdef CONFIG_SND_CS46XX_NEW_DSP
61 static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops;
62 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops;
63 static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops;
64 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops;
65 static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops;
66 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops;
67 #endif
68
69 static const struct snd_pcm_ops snd_cs46xx_playback_ops;
70 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops;
71 static const struct snd_pcm_ops snd_cs46xx_capture_ops;
72 static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops;
73
74 static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx *chip,
75 unsigned short reg,
76 int codec_index)
77 {
78 int count;
79 unsigned short result,tmp;
80 u32 offset = 0;
81
82 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
83 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
84 return 0xffff;
85
86 chip->active_ctrl(chip, 1);
87
88 if (codec_index == CS46XX_SECONDARY_CODEC_INDEX)
89 offset = CS46XX_SECONDARY_CODEC_OFFSET;
90
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97
98
99
100 snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
101
102 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL);
103 if ((tmp & ACCTL_VFRM) == 0) {
104 dev_warn(chip->card->dev, "ACCTL_VFRM not set 0x%x\n", tmp);
105 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM );
106 msleep(50);
107 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset);
108 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM );
109
110 }
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123
124
125 snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg);
126 snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0);
127 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
128 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_CRW |
129 ACCTL_VFRM | ACCTL_ESYN |
130 ACCTL_RSTN);
131 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW |
132 ACCTL_VFRM | ACCTL_ESYN |
133 ACCTL_RSTN);
134 } else {
135 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
136 ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN |
137 ACCTL_RSTN);
138 }
139
140
141
142
143 for (count = 0; count < 1000; count++) {
144
145
146
147 udelay(10);
148
149
150
151
152 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV))
153 goto ok1;
154 }
155
156 dev_err(chip->card->dev,
157 "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
158 result = 0xffff;
159 goto end;
160
161 ok1:
162
163
164
165 for (count = 0; count < 100; count++) {
166
167
168
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170
171 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS)
172 goto ok2;
173 udelay(10);
174 }
175
176 dev_err(chip->card->dev,
177 "AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n",
178 codec_index, reg);
179 result = 0xffff;
180 goto end;
181
182 ok2:
183
184
185
186
187 #if 0
188 dev_dbg(chip->card->dev,
189 "e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg,
190 snd_cs46xx_peekBA0(chip, BA0_ACSDA),
191 snd_cs46xx_peekBA0(chip, BA0_ACCAD));
192 #endif
193
194
195 result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
196 end:
197 chip->active_ctrl(chip, -1);
198 return result;
199 }
200
201 static unsigned short snd_cs46xx_ac97_read(struct snd_ac97 * ac97,
202 unsigned short reg)
203 {
204 struct snd_cs46xx *chip = ac97->private_data;
205 unsigned short val;
206 int codec_index = ac97->num;
207
208 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
209 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
210 return 0xffff;
211
212 val = snd_cs46xx_codec_read(chip, reg, codec_index);
213
214 return val;
215 }
216
217
218 static void snd_cs46xx_codec_write(struct snd_cs46xx *chip,
219 unsigned short reg,
220 unsigned short val,
221 int codec_index)
222 {
223 int count;
224
225 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
226 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
227 return;
228
229 chip->active_ctrl(chip, 1);
230
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251 snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg);
252 snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val);
253 snd_cs46xx_peekBA0(chip, BA0_ACCTL);
254
255 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
256 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM |
257 ACCTL_ESYN | ACCTL_RSTN);
258 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM |
259 ACCTL_ESYN | ACCTL_RSTN);
260 } else {
261 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
262 ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
263 }
264
265 for (count = 0; count < 4000; count++) {
266
267
268
269 udelay(10);
270
271
272
273
274 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) {
275 goto end;
276 }
277 }
278 dev_err(chip->card->dev,
279 "AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n",
280 codec_index, reg, val);
281 end:
282 chip->active_ctrl(chip, -1);
283 }
284
285 static void snd_cs46xx_ac97_write(struct snd_ac97 *ac97,
286 unsigned short reg,
287 unsigned short val)
288 {
289 struct snd_cs46xx *chip = ac97->private_data;
290 int codec_index = ac97->num;
291
292 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
293 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
294 return;
295
296 snd_cs46xx_codec_write(chip, reg, val, codec_index);
297 }
298
299
300
301
302
303
304 int snd_cs46xx_download(struct snd_cs46xx *chip,
305 u32 *src,
306 unsigned long offset,
307 unsigned long len)
308 {
309 void __iomem *dst;
310 unsigned int bank = offset >> 16;
311 offset = offset & 0xffff;
312
313 if (snd_BUG_ON((offset & 3) || (len & 3)))
314 return -EINVAL;
315 dst = chip->region.idx[bank+1].remap_addr + offset;
316 len /= sizeof(u32);
317
318
319 while (len-- > 0) {
320 writel(*src++, dst);
321 dst += sizeof(u32);
322 }
323 return 0;
324 }
325
326 static inline void memcpy_le32(void *dst, const void *src, unsigned int len)
327 {
328 #ifdef __LITTLE_ENDIAN
329 memcpy(dst, src, len);
330 #else
331 u32 *_dst = dst;
332 const __le32 *_src = src;
333 len /= 4;
334 while (len-- > 0)
335 *_dst++ = le32_to_cpu(*_src++);
336 #endif
337 }
338
339 #ifdef CONFIG_SND_CS46XX_NEW_DSP
340
341 static const char *module_names[CS46XX_DSP_MODULES] = {
342 "cwc4630", "cwcasync", "cwcsnoop", "cwcbinhack", "cwcdma"
343 };
344
345 MODULE_FIRMWARE("cs46xx/cwc4630");
346 MODULE_FIRMWARE("cs46xx/cwcasync");
347 MODULE_FIRMWARE("cs46xx/cwcsnoop");
348 MODULE_FIRMWARE("cs46xx/cwcbinhack");
349 MODULE_FIRMWARE("cs46xx/cwcdma");
350
351 static void free_module_desc(struct dsp_module_desc *module)
352 {
353 if (!module)
354 return;
355 kfree(module->module_name);
356 kfree(module->symbol_table.symbols);
357 if (module->segments) {
358 int i;
359 for (i = 0; i < module->nsegments; i++)
360 kfree(module->segments[i].data);
361 kfree(module->segments);
362 }
363 kfree(module);
364 }
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382 static int load_firmware(struct snd_cs46xx *chip,
383 struct dsp_module_desc **module_ret,
384 const char *fw_name)
385 {
386 int i, err;
387 unsigned int nums, fwlen, fwsize;
388 const __le32 *fwdat;
389 struct dsp_module_desc *module = NULL;
390 const struct firmware *fw;
391 char fw_path[32];
392
393 sprintf(fw_path, "cs46xx/%s", fw_name);
394 err = request_firmware(&fw, fw_path, &chip->pci->dev);
395 if (err < 0)
396 return err;
397 fwsize = fw->size / 4;
398 if (fwsize < 2) {
399 err = -EINVAL;
400 goto error;
401 }
402
403 err = -ENOMEM;
404 module = kzalloc(sizeof(*module), GFP_KERNEL);
405 if (!module)
406 goto error;
407 module->module_name = kstrdup(fw_name, GFP_KERNEL);
408 if (!module->module_name)
409 goto error;
410
411 fwlen = 0;
412 fwdat = (const __le32 *)fw->data;
413 nums = module->symbol_table.nsymbols = le32_to_cpu(fwdat[fwlen++]);
414 if (nums >= 40)
415 goto error_inval;
416 module->symbol_table.symbols =
417 kcalloc(nums, sizeof(struct dsp_symbol_entry), GFP_KERNEL);
418 if (!module->symbol_table.symbols)
419 goto error;
420 for (i = 0; i < nums; i++) {
421 struct dsp_symbol_entry *entry =
422 &module->symbol_table.symbols[i];
423 if (fwlen + 2 + DSP_MAX_SYMBOL_NAME / 4 > fwsize)
424 goto error_inval;
425 entry->address = le32_to_cpu(fwdat[fwlen++]);
426 memcpy(entry->symbol_name, &fwdat[fwlen], DSP_MAX_SYMBOL_NAME - 1);
427 fwlen += DSP_MAX_SYMBOL_NAME / 4;
428 entry->symbol_type = le32_to_cpu(fwdat[fwlen++]);
429 }
430
431 if (fwlen >= fwsize)
432 goto error_inval;
433 nums = module->nsegments = le32_to_cpu(fwdat[fwlen++]);
434 if (nums > 10)
435 goto error_inval;
436 module->segments =
437 kcalloc(nums, sizeof(struct dsp_segment_desc), GFP_KERNEL);
438 if (!module->segments)
439 goto error;
440 for (i = 0; i < nums; i++) {
441 struct dsp_segment_desc *entry = &module->segments[i];
442 if (fwlen + 3 > fwsize)
443 goto error_inval;
444 entry->segment_type = le32_to_cpu(fwdat[fwlen++]);
445 entry->offset = le32_to_cpu(fwdat[fwlen++]);
446 entry->size = le32_to_cpu(fwdat[fwlen++]);
447 if (fwlen + entry->size > fwsize)
448 goto error_inval;
449 entry->data = kmalloc_array(entry->size, 4, GFP_KERNEL);
450 if (!entry->data)
451 goto error;
452 memcpy_le32(entry->data, &fwdat[fwlen], entry->size * 4);
453 fwlen += entry->size;
454 }
455
456 *module_ret = module;
457 release_firmware(fw);
458 return 0;
459
460 error_inval:
461 err = -EINVAL;
462 error:
463 free_module_desc(module);
464 release_firmware(fw);
465 return err;
466 }
467
468 int snd_cs46xx_clear_BA1(struct snd_cs46xx *chip,
469 unsigned long offset,
470 unsigned long len)
471 {
472 void __iomem *dst;
473 unsigned int bank = offset >> 16;
474 offset = offset & 0xffff;
475
476 if (snd_BUG_ON((offset & 3) || (len & 3)))
477 return -EINVAL;
478 dst = chip->region.idx[bank+1].remap_addr + offset;
479 len /= sizeof(u32);
480
481
482 while (len-- > 0) {
483 writel(0, dst);
484 dst += sizeof(u32);
485 }
486 return 0;
487 }
488
489 #else
490
491 struct ba1_struct {
492 struct {
493 u32 offset;
494 u32 size;
495 } memory[BA1_MEMORY_COUNT];
496 u32 map[BA1_DWORD_SIZE];
497 };
498
499 MODULE_FIRMWARE("cs46xx/ba1");
500
501 static int load_firmware(struct snd_cs46xx *chip)
502 {
503 const struct firmware *fw;
504 int i, size, err;
505
506 err = request_firmware(&fw, "cs46xx/ba1", &chip->pci->dev);
507 if (err < 0)
508 return err;
509 if (fw->size != sizeof(*chip->ba1)) {
510 err = -EINVAL;
511 goto error;
512 }
513
514 chip->ba1 = vmalloc(sizeof(*chip->ba1));
515 if (!chip->ba1) {
516 err = -ENOMEM;
517 goto error;
518 }
519
520 memcpy_le32(chip->ba1, fw->data, sizeof(*chip->ba1));
521
522
523 size = 0;
524 for (i = 0; i < BA1_MEMORY_COUNT; i++)
525 size += chip->ba1->memory[i].size;
526 if (size > BA1_DWORD_SIZE * 4)
527 err = -EINVAL;
528
529 error:
530 release_firmware(fw);
531 return err;
532 }
533
534 int snd_cs46xx_download_image(struct snd_cs46xx *chip)
535 {
536 int idx, err;
537 unsigned int offset = 0;
538 struct ba1_struct *ba1 = chip->ba1;
539
540 for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) {
541 err = snd_cs46xx_download(chip,
542 &ba1->map[offset],
543 ba1->memory[idx].offset,
544 ba1->memory[idx].size);
545 if (err < 0)
546 return err;
547 offset += ba1->memory[idx].size >> 2;
548 }
549 return 0;
550 }
551 #endif
552
553
554
555
556
557 static void snd_cs46xx_reset(struct snd_cs46xx *chip)
558 {
559 int idx;
560
561
562
563
564 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP);
565
566
567
568
569 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN);
570
571
572
573
574 for (idx = 0; idx < 8; idx++) {
575 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx);
576 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF);
577 }
578 snd_cs46xx_poke(chip, BA1_DREG, 0);
579
580
581
582
583 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
584 }
585
586 static int cs46xx_wait_for_fifo(struct snd_cs46xx * chip,int retry_timeout)
587 {
588 u32 i, status = 0;
589
590
591
592 for(i = 0; i < 50; i++){
593 status = snd_cs46xx_peekBA0(chip, BA0_SERBST);
594
595 if( !(status & SERBST_WBSY) )
596 break;
597
598 mdelay(retry_timeout);
599 }
600
601 if(status & SERBST_WBSY) {
602 dev_err(chip->card->dev,
603 "failure waiting for FIFO command to complete\n");
604 return -EINVAL;
605 }
606
607 return 0;
608 }
609
610 static void snd_cs46xx_clear_serial_FIFOs(struct snd_cs46xx *chip)
611 {
612 int idx, powerdown = 0;
613 unsigned int tmp;
614
615
616
617
618
619 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
620 if (!(tmp & CLKCR1_SWCE)) {
621 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
622 powerdown = 1;
623 }
624
625
626
627
628
629
630 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0);
631
632
633
634
635 for (idx = 0; idx < 0xFF; idx++) {
636
637
638
639 if (cs46xx_wait_for_fifo(chip,1)) {
640 dev_dbg(chip->card->dev,
641 "failed waiting for FIFO at addr (%02X)\n",
642 idx);
643
644 if (powerdown)
645 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
646
647 break;
648 }
649
650
651
652 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
653
654
655
656 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
657 }
658
659
660
661
662 if (powerdown)
663 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
664 }
665
666 static void snd_cs46xx_proc_start(struct snd_cs46xx *chip)
667 {
668 int cnt;
669
670
671
672
673 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
674
675
676
677
678 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
679
680
681
682
683 for (cnt = 0; cnt < 25; cnt++) {
684 udelay(50);
685 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR))
686 break;
687 }
688
689 if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)
690 dev_err(chip->card->dev, "SPCR_RUNFR never reset\n");
691 }
692
693 static void snd_cs46xx_proc_stop(struct snd_cs46xx *chip)
694 {
695
696
697
698
699 snd_cs46xx_poke(chip, BA1_SPCR, 0);
700 }
701
702
703
704
705
706 #define GOF_PER_SEC 200
707
708 static void snd_cs46xx_set_play_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
709 {
710 unsigned long flags;
711 unsigned int tmp1, tmp2;
712 unsigned int phiIncr;
713 unsigned int correctionPerGOF, correctionPerSec;
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732 tmp1 = rate << 16;
733 phiIncr = tmp1 / 48000;
734 tmp1 -= phiIncr * 48000;
735 tmp1 <<= 10;
736 phiIncr <<= 10;
737 tmp2 = tmp1 / 48000;
738 phiIncr += tmp2;
739 tmp1 -= tmp2 * 48000;
740 correctionPerGOF = tmp1 / GOF_PER_SEC;
741 tmp1 -= correctionPerGOF * GOF_PER_SEC;
742 correctionPerSec = tmp1;
743
744
745
746
747 spin_lock_irqsave(&chip->reg_lock, flags);
748 snd_cs46xx_poke(chip, BA1_PSRC,
749 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
750 snd_cs46xx_poke(chip, BA1_PPI, phiIncr);
751 spin_unlock_irqrestore(&chip->reg_lock, flags);
752 }
753
754 static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
755 {
756 unsigned long flags;
757 unsigned int phiIncr, coeffIncr, tmp1, tmp2;
758 unsigned int correctionPerGOF, correctionPerSec, initialDelay;
759 unsigned int frameGroupLength, cnt;
760
761
762
763
764
765 if ((rate * 9) < 48000)
766 rate = 48000 / 9;
767
768
769
770
771
772 if (rate > 48000)
773 rate = 48000;
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797 tmp1 = rate << 16;
798 coeffIncr = tmp1 / 48000;
799 tmp1 -= coeffIncr * 48000;
800 tmp1 <<= 7;
801 coeffIncr <<= 7;
802 coeffIncr += tmp1 / 48000;
803 coeffIncr ^= 0xFFFFFFFF;
804 coeffIncr++;
805 tmp1 = 48000 << 16;
806 phiIncr = tmp1 / rate;
807 tmp1 -= phiIncr * rate;
808 tmp1 <<= 10;
809 phiIncr <<= 10;
810 tmp2 = tmp1 / rate;
811 phiIncr += tmp2;
812 tmp1 -= tmp2 * rate;
813 correctionPerGOF = tmp1 / GOF_PER_SEC;
814 tmp1 -= correctionPerGOF * GOF_PER_SEC;
815 correctionPerSec = tmp1;
816 initialDelay = ((48000 * 24) + rate - 1) / rate;
817
818
819
820
821 spin_lock_irqsave(&chip->reg_lock, flags);
822 snd_cs46xx_poke(chip, BA1_CSRC,
823 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
824 snd_cs46xx_poke(chip, BA1_CCI, coeffIncr);
825 snd_cs46xx_poke(chip, BA1_CD,
826 (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80);
827 snd_cs46xx_poke(chip, BA1_CPI, phiIncr);
828 spin_unlock_irqrestore(&chip->reg_lock, flags);
829
830
831
832
833
834
835 frameGroupLength = 1;
836 for (cnt = 2; cnt <= 64; cnt *= 2) {
837 if (((rate / cnt) * cnt) != rate)
838 frameGroupLength *= 2;
839 }
840 if (((rate / 3) * 3) != rate) {
841 frameGroupLength *= 3;
842 }
843 for (cnt = 5; cnt <= 125; cnt *= 5) {
844 if (((rate / cnt) * cnt) != rate)
845 frameGroupLength *= 5;
846 }
847
848
849
850
851 spin_lock_irqsave(&chip->reg_lock, flags);
852 snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength);
853 snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength));
854 snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF);
855 snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000));
856 snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF);
857 spin_unlock_irqrestore(&chip->reg_lock, flags);
858 }
859
860
861
862
863
864 static void snd_cs46xx_pb_trans_copy(struct snd_pcm_substream *substream,
865 struct snd_pcm_indirect *rec, size_t bytes)
866 {
867 struct snd_pcm_runtime *runtime = substream->runtime;
868 struct snd_cs46xx_pcm * cpcm = runtime->private_data;
869 memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes);
870 }
871
872 static int snd_cs46xx_playback_transfer(struct snd_pcm_substream *substream)
873 {
874 struct snd_pcm_runtime *runtime = substream->runtime;
875 struct snd_cs46xx_pcm * cpcm = runtime->private_data;
876 return snd_pcm_indirect_playback_transfer(substream, &cpcm->pcm_rec,
877 snd_cs46xx_pb_trans_copy);
878 }
879
880 static void snd_cs46xx_cp_trans_copy(struct snd_pcm_substream *substream,
881 struct snd_pcm_indirect *rec, size_t bytes)
882 {
883 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
884 struct snd_pcm_runtime *runtime = substream->runtime;
885 memcpy(runtime->dma_area + rec->sw_data,
886 chip->capt.hw_buf.area + rec->hw_data, bytes);
887 }
888
889 static int snd_cs46xx_capture_transfer(struct snd_pcm_substream *substream)
890 {
891 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
892 return snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec,
893 snd_cs46xx_cp_trans_copy);
894 }
895
896 static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(struct snd_pcm_substream *substream)
897 {
898 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
899 size_t ptr;
900 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
901
902 if (snd_BUG_ON(!cpcm->pcm_channel))
903 return -ENXIO;
904
905 #ifdef CONFIG_SND_CS46XX_NEW_DSP
906 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
907 #else
908 ptr = snd_cs46xx_peek(chip, BA1_PBA);
909 #endif
910 ptr -= cpcm->hw_buf.addr;
911 return ptr >> cpcm->shift;
912 }
913
914 static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(struct snd_pcm_substream *substream)
915 {
916 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
917 size_t ptr;
918 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
919
920 #ifdef CONFIG_SND_CS46XX_NEW_DSP
921 if (snd_BUG_ON(!cpcm->pcm_channel))
922 return -ENXIO;
923 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
924 #else
925 ptr = snd_cs46xx_peek(chip, BA1_PBA);
926 #endif
927 ptr -= cpcm->hw_buf.addr;
928 return snd_pcm_indirect_playback_pointer(substream, &cpcm->pcm_rec, ptr);
929 }
930
931 static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(struct snd_pcm_substream *substream)
932 {
933 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
934 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
935 return ptr >> chip->capt.shift;
936 }
937
938 static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(struct snd_pcm_substream *substream)
939 {
940 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
941 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
942 return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr);
943 }
944
945 static int snd_cs46xx_playback_trigger(struct snd_pcm_substream *substream,
946 int cmd)
947 {
948 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
949
950 int result = 0;
951
952 #ifdef CONFIG_SND_CS46XX_NEW_DSP
953 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
954 if (! cpcm->pcm_channel) {
955 return -ENXIO;
956 }
957 #endif
958 switch (cmd) {
959 case SNDRV_PCM_TRIGGER_START:
960 case SNDRV_PCM_TRIGGER_RESUME:
961 #ifdef CONFIG_SND_CS46XX_NEW_DSP
962
963 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
964 SCBVolumeCtrl) << 2, 0x80008000);
965
966 if (cpcm->pcm_channel->unlinked)
967 cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel);
968
969 if (substream->runtime->periods != CS46XX_FRAGS)
970 snd_cs46xx_playback_transfer(substream);
971 #else
972 spin_lock(&chip->reg_lock);
973 if (substream->runtime->periods != CS46XX_FRAGS)
974 snd_cs46xx_playback_transfer(substream);
975 { unsigned int tmp;
976 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
977 tmp &= 0x0000ffff;
978 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp);
979 }
980 spin_unlock(&chip->reg_lock);
981 #endif
982 break;
983 case SNDRV_PCM_TRIGGER_STOP:
984 case SNDRV_PCM_TRIGGER_SUSPEND:
985 #ifdef CONFIG_SND_CS46XX_NEW_DSP
986
987 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
988 SCBVolumeCtrl) << 2, 0xffffffff);
989
990 if (!cpcm->pcm_channel->unlinked)
991 cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel);
992 #else
993 spin_lock(&chip->reg_lock);
994 { unsigned int tmp;
995 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
996 tmp &= 0x0000ffff;
997 snd_cs46xx_poke(chip, BA1_PCTL, tmp);
998 }
999 spin_unlock(&chip->reg_lock);
1000 #endif
1001 break;
1002 default:
1003 result = -EINVAL;
1004 break;
1005 }
1006
1007 return result;
1008 }
1009
1010 static int snd_cs46xx_capture_trigger(struct snd_pcm_substream *substream,
1011 int cmd)
1012 {
1013 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1014 unsigned int tmp;
1015 int result = 0;
1016
1017 spin_lock(&chip->reg_lock);
1018 switch (cmd) {
1019 case SNDRV_PCM_TRIGGER_START:
1020 case SNDRV_PCM_TRIGGER_RESUME:
1021 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1022 tmp &= 0xffff0000;
1023 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp);
1024 break;
1025 case SNDRV_PCM_TRIGGER_STOP:
1026 case SNDRV_PCM_TRIGGER_SUSPEND:
1027 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1028 tmp &= 0xffff0000;
1029 snd_cs46xx_poke(chip, BA1_CCTL, tmp);
1030 break;
1031 default:
1032 result = -EINVAL;
1033 break;
1034 }
1035 spin_unlock(&chip->reg_lock);
1036
1037 return result;
1038 }
1039
1040 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1041 static int _cs46xx_adjust_sample_rate (struct snd_cs46xx *chip, struct snd_cs46xx_pcm *cpcm,
1042 int sample_rate)
1043 {
1044
1045
1046 if ( cpcm->pcm_channel == NULL) {
1047 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate,
1048 cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id);
1049 if (cpcm->pcm_channel == NULL) {
1050 dev_err(chip->card->dev,
1051 "failed to create virtual PCM channel\n");
1052 return -ENOMEM;
1053 }
1054 cpcm->pcm_channel->sample_rate = sample_rate;
1055 } else
1056
1057 if ((int)cpcm->pcm_channel->sample_rate != sample_rate) {
1058 int unlinked = cpcm->pcm_channel->unlinked;
1059 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel);
1060
1061 if ( (cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, cpcm,
1062 cpcm->hw_buf.addr,
1063 cpcm->pcm_channel_id)) == NULL) {
1064 dev_err(chip->card->dev,
1065 "failed to re-create virtual PCM channel\n");
1066 return -ENOMEM;
1067 }
1068
1069 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel);
1070 cpcm->pcm_channel->sample_rate = sample_rate;
1071 }
1072
1073 return 0;
1074 }
1075 #endif
1076
1077
1078 static int snd_cs46xx_playback_hw_params(struct snd_pcm_substream *substream,
1079 struct snd_pcm_hw_params *hw_params)
1080 {
1081 struct snd_pcm_runtime *runtime = substream->runtime;
1082 struct snd_cs46xx_pcm *cpcm;
1083 int err;
1084 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1085 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1086 int sample_rate = params_rate(hw_params);
1087 int period_size = params_period_bytes(hw_params);
1088 #endif
1089 cpcm = runtime->private_data;
1090
1091 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1092 if (snd_BUG_ON(!sample_rate))
1093 return -ENXIO;
1094
1095 mutex_lock(&chip->spos_mutex);
1096
1097 if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) {
1098 mutex_unlock(&chip->spos_mutex);
1099 return -ENXIO;
1100 }
1101
1102 snd_BUG_ON(!cpcm->pcm_channel);
1103 if (!cpcm->pcm_channel) {
1104 mutex_unlock(&chip->spos_mutex);
1105 return -ENXIO;
1106 }
1107
1108
1109 if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) {
1110 mutex_unlock(&chip->spos_mutex);
1111 return -EINVAL;
1112 }
1113
1114 dev_dbg(chip->card->dev,
1115 "period_size (%d), periods (%d) buffer_size(%d)\n",
1116 period_size, params_periods(hw_params),
1117 params_buffer_bytes(hw_params));
1118 #endif
1119
1120 if (params_periods(hw_params) == CS46XX_FRAGS) {
1121 if (runtime->dma_area != cpcm->hw_buf.area)
1122 snd_pcm_lib_free_pages(substream);
1123 runtime->dma_area = cpcm->hw_buf.area;
1124 runtime->dma_addr = cpcm->hw_buf.addr;
1125 runtime->dma_bytes = cpcm->hw_buf.bytes;
1126
1127
1128 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1129 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1130 substream->ops = &snd_cs46xx_playback_ops;
1131 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1132 substream->ops = &snd_cs46xx_playback_rear_ops;
1133 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1134 substream->ops = &snd_cs46xx_playback_clfe_ops;
1135 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1136 substream->ops = &snd_cs46xx_playback_iec958_ops;
1137 } else {
1138 snd_BUG();
1139 }
1140 #else
1141 substream->ops = &snd_cs46xx_playback_ops;
1142 #endif
1143
1144 } else {
1145 if (runtime->dma_area == cpcm->hw_buf.area) {
1146 runtime->dma_area = NULL;
1147 runtime->dma_addr = 0;
1148 runtime->dma_bytes = 0;
1149 }
1150 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) {
1151 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1152 mutex_unlock(&chip->spos_mutex);
1153 #endif
1154 return err;
1155 }
1156
1157 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1158 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1159 substream->ops = &snd_cs46xx_playback_indirect_ops;
1160 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1161 substream->ops = &snd_cs46xx_playback_indirect_rear_ops;
1162 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1163 substream->ops = &snd_cs46xx_playback_indirect_clfe_ops;
1164 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1165 substream->ops = &snd_cs46xx_playback_indirect_iec958_ops;
1166 } else {
1167 snd_BUG();
1168 }
1169 #else
1170 substream->ops = &snd_cs46xx_playback_indirect_ops;
1171 #endif
1172
1173 }
1174
1175 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1176 mutex_unlock(&chip->spos_mutex);
1177 #endif
1178
1179 return 0;
1180 }
1181
1182 static int snd_cs46xx_playback_hw_free(struct snd_pcm_substream *substream)
1183 {
1184
1185 struct snd_pcm_runtime *runtime = substream->runtime;
1186 struct snd_cs46xx_pcm *cpcm;
1187
1188 cpcm = runtime->private_data;
1189
1190
1191
1192 if (!cpcm) return -ENXIO;
1193
1194 if (runtime->dma_area != cpcm->hw_buf.area)
1195 snd_pcm_lib_free_pages(substream);
1196
1197 runtime->dma_area = NULL;
1198 runtime->dma_addr = 0;
1199 runtime->dma_bytes = 0;
1200
1201 return 0;
1202 }
1203
1204 static int snd_cs46xx_playback_prepare(struct snd_pcm_substream *substream)
1205 {
1206 unsigned int tmp;
1207 unsigned int pfie;
1208 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1209 struct snd_pcm_runtime *runtime = substream->runtime;
1210 struct snd_cs46xx_pcm *cpcm;
1211
1212 cpcm = runtime->private_data;
1213
1214 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1215 if (snd_BUG_ON(!cpcm->pcm_channel))
1216 return -ENXIO;
1217
1218 pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 );
1219 pfie &= ~0x0000f03f;
1220 #else
1221
1222 pfie = snd_cs46xx_peek(chip, BA1_PFIE);
1223 pfie &= ~0x0000f03f;
1224 #endif
1225
1226 cpcm->shift = 2;
1227
1228 if (runtime->channels == 1) {
1229 cpcm->shift--;
1230 pfie |= 0x00002000;
1231 }
1232
1233 if (snd_pcm_format_width(runtime->format) == 8) {
1234 cpcm->shift--;
1235 pfie |= 0x00001000;
1236 }
1237
1238 if (snd_pcm_format_unsigned(runtime->format))
1239 pfie |= 0x00008000;
1240
1241
1242 if (snd_pcm_format_width(runtime->format) != 8) {
1243
1244 if (snd_pcm_format_big_endian(runtime->format))
1245 pfie |= 0x00004000;
1246 }
1247
1248 memset(&cpcm->pcm_rec, 0, sizeof(cpcm->pcm_rec));
1249 cpcm->pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1250 cpcm->pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift;
1251
1252 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1253
1254 tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2);
1255 tmp &= ~0x000003ff;
1256 tmp |= (4 << cpcm->shift) - 1;
1257
1258 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp);
1259
1260
1261 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot);
1262 #else
1263 snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr);
1264 tmp = snd_cs46xx_peek(chip, BA1_PDTC);
1265 tmp &= ~0x000003ff;
1266 tmp |= (4 << cpcm->shift) - 1;
1267 snd_cs46xx_poke(chip, BA1_PDTC, tmp);
1268 snd_cs46xx_poke(chip, BA1_PFIE, pfie);
1269 snd_cs46xx_set_play_sample_rate(chip, runtime->rate);
1270 #endif
1271
1272 return 0;
1273 }
1274
1275 static int snd_cs46xx_capture_hw_params(struct snd_pcm_substream *substream,
1276 struct snd_pcm_hw_params *hw_params)
1277 {
1278 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1279 struct snd_pcm_runtime *runtime = substream->runtime;
1280 int err;
1281
1282 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1283 cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params));
1284 #endif
1285 if (runtime->periods == CS46XX_FRAGS) {
1286 if (runtime->dma_area != chip->capt.hw_buf.area)
1287 snd_pcm_lib_free_pages(substream);
1288 runtime->dma_area = chip->capt.hw_buf.area;
1289 runtime->dma_addr = chip->capt.hw_buf.addr;
1290 runtime->dma_bytes = chip->capt.hw_buf.bytes;
1291 substream->ops = &snd_cs46xx_capture_ops;
1292 } else {
1293 if (runtime->dma_area == chip->capt.hw_buf.area) {
1294 runtime->dma_area = NULL;
1295 runtime->dma_addr = 0;
1296 runtime->dma_bytes = 0;
1297 }
1298 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1299 return err;
1300 substream->ops = &snd_cs46xx_capture_indirect_ops;
1301 }
1302
1303 return 0;
1304 }
1305
1306 static int snd_cs46xx_capture_hw_free(struct snd_pcm_substream *substream)
1307 {
1308 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1309 struct snd_pcm_runtime *runtime = substream->runtime;
1310
1311 if (runtime->dma_area != chip->capt.hw_buf.area)
1312 snd_pcm_lib_free_pages(substream);
1313 runtime->dma_area = NULL;
1314 runtime->dma_addr = 0;
1315 runtime->dma_bytes = 0;
1316
1317 return 0;
1318 }
1319
1320 static int snd_cs46xx_capture_prepare(struct snd_pcm_substream *substream)
1321 {
1322 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1323 struct snd_pcm_runtime *runtime = substream->runtime;
1324
1325 snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr);
1326 chip->capt.shift = 2;
1327 memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec));
1328 chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1329 chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2;
1330 snd_cs46xx_set_capture_sample_rate(chip, runtime->rate);
1331
1332 return 0;
1333 }
1334
1335 static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id)
1336 {
1337 struct snd_cs46xx *chip = dev_id;
1338 u32 status1;
1339 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1340 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1341 u32 status2;
1342 int i;
1343 struct snd_cs46xx_pcm *cpcm = NULL;
1344 #endif
1345
1346
1347
1348
1349 status1 = snd_cs46xx_peekBA0(chip, BA0_HISR);
1350 if ((status1 & 0x7fffffff) == 0) {
1351 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1352 return IRQ_NONE;
1353 }
1354
1355 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1356 status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0);
1357
1358 for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) {
1359 if (i <= 15) {
1360 if ( status1 & (1 << i) ) {
1361 if (i == CS46XX_DSP_CAPTURE_CHANNEL) {
1362 if (chip->capt.substream)
1363 snd_pcm_period_elapsed(chip->capt.substream);
1364 } else {
1365 if (ins->pcm_channels[i].active &&
1366 ins->pcm_channels[i].private_data &&
1367 !ins->pcm_channels[i].unlinked) {
1368 cpcm = ins->pcm_channels[i].private_data;
1369 snd_pcm_period_elapsed(cpcm->substream);
1370 }
1371 }
1372 }
1373 } else {
1374 if ( status2 & (1 << (i - 16))) {
1375 if (ins->pcm_channels[i].active &&
1376 ins->pcm_channels[i].private_data &&
1377 !ins->pcm_channels[i].unlinked) {
1378 cpcm = ins->pcm_channels[i].private_data;
1379 snd_pcm_period_elapsed(cpcm->substream);
1380 }
1381 }
1382 }
1383 }
1384
1385 #else
1386
1387 if ((status1 & HISR_VC0) && chip->playback_pcm) {
1388 if (chip->playback_pcm->substream)
1389 snd_pcm_period_elapsed(chip->playback_pcm->substream);
1390 }
1391 if ((status1 & HISR_VC1) && chip->pcm) {
1392 if (chip->capt.substream)
1393 snd_pcm_period_elapsed(chip->capt.substream);
1394 }
1395 #endif
1396
1397 if ((status1 & HISR_MIDI) && chip->rmidi) {
1398 unsigned char c;
1399
1400 spin_lock(&chip->reg_lock);
1401 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) {
1402 c = snd_cs46xx_peekBA0(chip, BA0_MIDRP);
1403 if ((chip->midcr & MIDCR_RIE) == 0)
1404 continue;
1405 snd_rawmidi_receive(chip->midi_input, &c, 1);
1406 }
1407 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
1408 if ((chip->midcr & MIDCR_TIE) == 0)
1409 break;
1410 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1411 chip->midcr &= ~MIDCR_TIE;
1412 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1413 break;
1414 }
1415 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c);
1416 }
1417 spin_unlock(&chip->reg_lock);
1418 }
1419
1420
1421
1422 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1423
1424 return IRQ_HANDLED;
1425 }
1426
1427 static const struct snd_pcm_hardware snd_cs46xx_playback =
1428 {
1429 .info = (SNDRV_PCM_INFO_MMAP |
1430 SNDRV_PCM_INFO_INTERLEAVED |
1431 SNDRV_PCM_INFO_BLOCK_TRANSFER
1432 |
1433 SNDRV_PCM_INFO_SYNC_APPLPTR),
1434 .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
1435 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
1436 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE),
1437 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1438 .rate_min = 5500,
1439 .rate_max = 48000,
1440 .channels_min = 1,
1441 .channels_max = 2,
1442 .buffer_bytes_max = (256 * 1024),
1443 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1444 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1445 .periods_min = CS46XX_FRAGS,
1446 .periods_max = 1024,
1447 .fifo_size = 0,
1448 };
1449
1450 static const struct snd_pcm_hardware snd_cs46xx_capture =
1451 {
1452 .info = (SNDRV_PCM_INFO_MMAP |
1453 SNDRV_PCM_INFO_INTERLEAVED |
1454 SNDRV_PCM_INFO_BLOCK_TRANSFER
1455 |
1456 SNDRV_PCM_INFO_SYNC_APPLPTR),
1457 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1458 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1459 .rate_min = 5500,
1460 .rate_max = 48000,
1461 .channels_min = 2,
1462 .channels_max = 2,
1463 .buffer_bytes_max = (256 * 1024),
1464 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1465 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1466 .periods_min = CS46XX_FRAGS,
1467 .periods_max = 1024,
1468 .fifo_size = 0,
1469 };
1470
1471 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1472
1473 static const unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 };
1474
1475 static const struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = {
1476 .count = ARRAY_SIZE(period_sizes),
1477 .list = period_sizes,
1478 .mask = 0
1479 };
1480
1481 #endif
1482
1483 static void snd_cs46xx_pcm_free_substream(struct snd_pcm_runtime *runtime)
1484 {
1485 kfree(runtime->private_data);
1486 }
1487
1488 static int _cs46xx_playback_open_channel (struct snd_pcm_substream *substream,int pcm_channel_id)
1489 {
1490 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1491 struct snd_cs46xx_pcm * cpcm;
1492 struct snd_pcm_runtime *runtime = substream->runtime;
1493
1494 cpcm = kzalloc(sizeof(*cpcm), GFP_KERNEL);
1495 if (cpcm == NULL)
1496 return -ENOMEM;
1497 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1498 PAGE_SIZE, &cpcm->hw_buf) < 0) {
1499 kfree(cpcm);
1500 return -ENOMEM;
1501 }
1502
1503 runtime->hw = snd_cs46xx_playback;
1504 runtime->private_data = cpcm;
1505 runtime->private_free = snd_cs46xx_pcm_free_substream;
1506
1507 cpcm->substream = substream;
1508 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1509 mutex_lock(&chip->spos_mutex);
1510 cpcm->pcm_channel = NULL;
1511 cpcm->pcm_channel_id = pcm_channel_id;
1512
1513
1514 snd_pcm_hw_constraint_list(runtime, 0,
1515 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1516 &hw_constraints_period_sizes);
1517
1518 mutex_unlock(&chip->spos_mutex);
1519 #else
1520 chip->playback_pcm = cpcm;
1521 #endif
1522
1523 if (chip->accept_valid)
1524 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1525 chip->active_ctrl(chip, 1);
1526
1527 return 0;
1528 }
1529
1530 static int snd_cs46xx_playback_open(struct snd_pcm_substream *substream)
1531 {
1532 dev_dbg(substream->pcm->card->dev, "open front channel\n");
1533 return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL);
1534 }
1535
1536 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1537 static int snd_cs46xx_playback_open_rear(struct snd_pcm_substream *substream)
1538 {
1539 dev_dbg(substream->pcm->card->dev, "open rear channel\n");
1540 return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL);
1541 }
1542
1543 static int snd_cs46xx_playback_open_clfe(struct snd_pcm_substream *substream)
1544 {
1545 dev_dbg(substream->pcm->card->dev, "open center - LFE channel\n");
1546 return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL);
1547 }
1548
1549 static int snd_cs46xx_playback_open_iec958(struct snd_pcm_substream *substream)
1550 {
1551 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1552
1553 dev_dbg(chip->card->dev, "open raw iec958 channel\n");
1554
1555 mutex_lock(&chip->spos_mutex);
1556 cs46xx_iec958_pre_open (chip);
1557 mutex_unlock(&chip->spos_mutex);
1558
1559 return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL);
1560 }
1561
1562 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream);
1563
1564 static int snd_cs46xx_playback_close_iec958(struct snd_pcm_substream *substream)
1565 {
1566 int err;
1567 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1568
1569 dev_dbg(chip->card->dev, "close raw iec958 channel\n");
1570
1571 err = snd_cs46xx_playback_close(substream);
1572
1573 mutex_lock(&chip->spos_mutex);
1574 cs46xx_iec958_post_close (chip);
1575 mutex_unlock(&chip->spos_mutex);
1576
1577 return err;
1578 }
1579 #endif
1580
1581 static int snd_cs46xx_capture_open(struct snd_pcm_substream *substream)
1582 {
1583 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1584
1585 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1586 PAGE_SIZE, &chip->capt.hw_buf) < 0)
1587 return -ENOMEM;
1588 chip->capt.substream = substream;
1589 substream->runtime->hw = snd_cs46xx_capture;
1590
1591 if (chip->accept_valid)
1592 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1593
1594 chip->active_ctrl(chip, 1);
1595
1596 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1597 snd_pcm_hw_constraint_list(substream->runtime, 0,
1598 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1599 &hw_constraints_period_sizes);
1600 #endif
1601 return 0;
1602 }
1603
1604 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream)
1605 {
1606 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1607 struct snd_pcm_runtime *runtime = substream->runtime;
1608 struct snd_cs46xx_pcm * cpcm;
1609
1610 cpcm = runtime->private_data;
1611
1612
1613 if (!cpcm) return -ENXIO;
1614
1615 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1616 mutex_lock(&chip->spos_mutex);
1617 if (cpcm->pcm_channel) {
1618 cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel);
1619 cpcm->pcm_channel = NULL;
1620 }
1621 mutex_unlock(&chip->spos_mutex);
1622 #else
1623 chip->playback_pcm = NULL;
1624 #endif
1625
1626 cpcm->substream = NULL;
1627 snd_dma_free_pages(&cpcm->hw_buf);
1628 chip->active_ctrl(chip, -1);
1629
1630 return 0;
1631 }
1632
1633 static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream)
1634 {
1635 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1636
1637 chip->capt.substream = NULL;
1638 snd_dma_free_pages(&chip->capt.hw_buf);
1639 chip->active_ctrl(chip, -1);
1640
1641 return 0;
1642 }
1643
1644 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1645 static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops = {
1646 .open = snd_cs46xx_playback_open_rear,
1647 .close = snd_cs46xx_playback_close,
1648 .ioctl = snd_pcm_lib_ioctl,
1649 .hw_params = snd_cs46xx_playback_hw_params,
1650 .hw_free = snd_cs46xx_playback_hw_free,
1651 .prepare = snd_cs46xx_playback_prepare,
1652 .trigger = snd_cs46xx_playback_trigger,
1653 .pointer = snd_cs46xx_playback_direct_pointer,
1654 };
1655
1656 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = {
1657 .open = snd_cs46xx_playback_open_rear,
1658 .close = snd_cs46xx_playback_close,
1659 .ioctl = snd_pcm_lib_ioctl,
1660 .hw_params = snd_cs46xx_playback_hw_params,
1661 .hw_free = snd_cs46xx_playback_hw_free,
1662 .prepare = snd_cs46xx_playback_prepare,
1663 .trigger = snd_cs46xx_playback_trigger,
1664 .pointer = snd_cs46xx_playback_indirect_pointer,
1665 .ack = snd_cs46xx_playback_transfer,
1666 };
1667
1668 static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = {
1669 .open = snd_cs46xx_playback_open_clfe,
1670 .close = snd_cs46xx_playback_close,
1671 .ioctl = snd_pcm_lib_ioctl,
1672 .hw_params = snd_cs46xx_playback_hw_params,
1673 .hw_free = snd_cs46xx_playback_hw_free,
1674 .prepare = snd_cs46xx_playback_prepare,
1675 .trigger = snd_cs46xx_playback_trigger,
1676 .pointer = snd_cs46xx_playback_direct_pointer,
1677 };
1678
1679 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = {
1680 .open = snd_cs46xx_playback_open_clfe,
1681 .close = snd_cs46xx_playback_close,
1682 .ioctl = snd_pcm_lib_ioctl,
1683 .hw_params = snd_cs46xx_playback_hw_params,
1684 .hw_free = snd_cs46xx_playback_hw_free,
1685 .prepare = snd_cs46xx_playback_prepare,
1686 .trigger = snd_cs46xx_playback_trigger,
1687 .pointer = snd_cs46xx_playback_indirect_pointer,
1688 .ack = snd_cs46xx_playback_transfer,
1689 };
1690
1691 static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = {
1692 .open = snd_cs46xx_playback_open_iec958,
1693 .close = snd_cs46xx_playback_close_iec958,
1694 .ioctl = snd_pcm_lib_ioctl,
1695 .hw_params = snd_cs46xx_playback_hw_params,
1696 .hw_free = snd_cs46xx_playback_hw_free,
1697 .prepare = snd_cs46xx_playback_prepare,
1698 .trigger = snd_cs46xx_playback_trigger,
1699 .pointer = snd_cs46xx_playback_direct_pointer,
1700 };
1701
1702 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = {
1703 .open = snd_cs46xx_playback_open_iec958,
1704 .close = snd_cs46xx_playback_close_iec958,
1705 .ioctl = snd_pcm_lib_ioctl,
1706 .hw_params = snd_cs46xx_playback_hw_params,
1707 .hw_free = snd_cs46xx_playback_hw_free,
1708 .prepare = snd_cs46xx_playback_prepare,
1709 .trigger = snd_cs46xx_playback_trigger,
1710 .pointer = snd_cs46xx_playback_indirect_pointer,
1711 .ack = snd_cs46xx_playback_transfer,
1712 };
1713
1714 #endif
1715
1716 static const struct snd_pcm_ops snd_cs46xx_playback_ops = {
1717 .open = snd_cs46xx_playback_open,
1718 .close = snd_cs46xx_playback_close,
1719 .ioctl = snd_pcm_lib_ioctl,
1720 .hw_params = snd_cs46xx_playback_hw_params,
1721 .hw_free = snd_cs46xx_playback_hw_free,
1722 .prepare = snd_cs46xx_playback_prepare,
1723 .trigger = snd_cs46xx_playback_trigger,
1724 .pointer = snd_cs46xx_playback_direct_pointer,
1725 };
1726
1727 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = {
1728 .open = snd_cs46xx_playback_open,
1729 .close = snd_cs46xx_playback_close,
1730 .ioctl = snd_pcm_lib_ioctl,
1731 .hw_params = snd_cs46xx_playback_hw_params,
1732 .hw_free = snd_cs46xx_playback_hw_free,
1733 .prepare = snd_cs46xx_playback_prepare,
1734 .trigger = snd_cs46xx_playback_trigger,
1735 .pointer = snd_cs46xx_playback_indirect_pointer,
1736 .ack = snd_cs46xx_playback_transfer,
1737 };
1738
1739 static const struct snd_pcm_ops snd_cs46xx_capture_ops = {
1740 .open = snd_cs46xx_capture_open,
1741 .close = snd_cs46xx_capture_close,
1742 .ioctl = snd_pcm_lib_ioctl,
1743 .hw_params = snd_cs46xx_capture_hw_params,
1744 .hw_free = snd_cs46xx_capture_hw_free,
1745 .prepare = snd_cs46xx_capture_prepare,
1746 .trigger = snd_cs46xx_capture_trigger,
1747 .pointer = snd_cs46xx_capture_direct_pointer,
1748 };
1749
1750 static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops = {
1751 .open = snd_cs46xx_capture_open,
1752 .close = snd_cs46xx_capture_close,
1753 .ioctl = snd_pcm_lib_ioctl,
1754 .hw_params = snd_cs46xx_capture_hw_params,
1755 .hw_free = snd_cs46xx_capture_hw_free,
1756 .prepare = snd_cs46xx_capture_prepare,
1757 .trigger = snd_cs46xx_capture_trigger,
1758 .pointer = snd_cs46xx_capture_indirect_pointer,
1759 .ack = snd_cs46xx_capture_transfer,
1760 };
1761
1762 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1763 #define MAX_PLAYBACK_CHANNELS (DSP_MAX_PCM_CHANNELS - 1)
1764 #else
1765 #define MAX_PLAYBACK_CHANNELS 1
1766 #endif
1767
1768 int snd_cs46xx_pcm(struct snd_cs46xx *chip, int device)
1769 {
1770 struct snd_pcm *pcm;
1771 int err;
1772
1773 if ((err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm)) < 0)
1774 return err;
1775
1776 pcm->private_data = chip;
1777
1778 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops);
1779 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops);
1780
1781
1782 pcm->info_flags = 0;
1783 strcpy(pcm->name, "CS46xx");
1784 chip->pcm = pcm;
1785
1786 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1787 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1788
1789 return 0;
1790 }
1791
1792
1793 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1794 int snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device)
1795 {
1796 struct snd_pcm *pcm;
1797 int err;
1798
1799 if ((err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1800 return err;
1801
1802 pcm->private_data = chip;
1803
1804 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops);
1805
1806
1807 pcm->info_flags = 0;
1808 strcpy(pcm->name, "CS46xx - Rear");
1809 chip->pcm_rear = pcm;
1810
1811 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1812 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1813
1814 return 0;
1815 }
1816
1817 int snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device)
1818 {
1819 struct snd_pcm *pcm;
1820 int err;
1821
1822 if ((err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1823 return err;
1824
1825 pcm->private_data = chip;
1826
1827 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops);
1828
1829
1830 pcm->info_flags = 0;
1831 strcpy(pcm->name, "CS46xx - Center LFE");
1832 chip->pcm_center_lfe = pcm;
1833
1834 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1835 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1836
1837 return 0;
1838 }
1839
1840 int snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device)
1841 {
1842 struct snd_pcm *pcm;
1843 int err;
1844
1845 if ((err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm)) < 0)
1846 return err;
1847
1848 pcm->private_data = chip;
1849
1850 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops);
1851
1852
1853 pcm->info_flags = 0;
1854 strcpy(pcm->name, "CS46xx - IEC958");
1855 chip->pcm_iec958 = pcm;
1856
1857 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1858 snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1859
1860 return 0;
1861 }
1862 #endif
1863
1864
1865
1866
1867 static void snd_cs46xx_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1868 {
1869 struct snd_cs46xx *chip = bus->private_data;
1870
1871 chip->ac97_bus = NULL;
1872 }
1873
1874 static void snd_cs46xx_mixer_free_ac97(struct snd_ac97 *ac97)
1875 {
1876 struct snd_cs46xx *chip = ac97->private_data;
1877
1878 if (snd_BUG_ON(ac97 != chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] &&
1879 ac97 != chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]))
1880 return;
1881
1882 if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) {
1883 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL;
1884 chip->eapd_switch = NULL;
1885 }
1886 else
1887 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL;
1888 }
1889
1890 static int snd_cs46xx_vol_info(struct snd_kcontrol *kcontrol,
1891 struct snd_ctl_elem_info *uinfo)
1892 {
1893 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1894 uinfo->count = 2;
1895 uinfo->value.integer.min = 0;
1896 uinfo->value.integer.max = 0x7fff;
1897 return 0;
1898 }
1899
1900 static int snd_cs46xx_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1901 {
1902 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1903 int reg = kcontrol->private_value;
1904 unsigned int val = snd_cs46xx_peek(chip, reg);
1905 ucontrol->value.integer.value[0] = 0xffff - (val >> 16);
1906 ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff);
1907 return 0;
1908 }
1909
1910 static int snd_cs46xx_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1911 {
1912 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1913 int reg = kcontrol->private_value;
1914 unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 |
1915 (0xffff - ucontrol->value.integer.value[1]));
1916 unsigned int old = snd_cs46xx_peek(chip, reg);
1917 int change = (old != val);
1918
1919 if (change) {
1920 snd_cs46xx_poke(chip, reg, val);
1921 }
1922
1923 return change;
1924 }
1925
1926 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1927
1928 static int snd_cs46xx_vol_dac_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1929 {
1930 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1931
1932 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left;
1933 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right;
1934
1935 return 0;
1936 }
1937
1938 static int snd_cs46xx_vol_dac_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1939 {
1940 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1941 int change = 0;
1942
1943 if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] ||
1944 chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) {
1945 cs46xx_dsp_set_dac_volume(chip,
1946 ucontrol->value.integer.value[0],
1947 ucontrol->value.integer.value[1]);
1948 change = 1;
1949 }
1950
1951 return change;
1952 }
1953
1954 #if 0
1955 static int snd_cs46xx_vol_iec958_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1956 {
1957 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1958
1959 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left;
1960 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right;
1961 return 0;
1962 }
1963
1964 static int snd_cs46xx_vol_iec958_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1965 {
1966 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1967 int change = 0;
1968
1969 if (chip->dsp_spos_instance->spdif_input_volume_left != ucontrol->value.integer.value[0] ||
1970 chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) {
1971 cs46xx_dsp_set_iec958_volume (chip,
1972 ucontrol->value.integer.value[0],
1973 ucontrol->value.integer.value[1]);
1974 change = 1;
1975 }
1976
1977 return change;
1978 }
1979 #endif
1980
1981 #define snd_mixer_boolean_info snd_ctl_boolean_mono_info
1982
1983 static int snd_cs46xx_iec958_get(struct snd_kcontrol *kcontrol,
1984 struct snd_ctl_elem_value *ucontrol)
1985 {
1986 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1987 int reg = kcontrol->private_value;
1988
1989 if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT)
1990 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1991 else
1992 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in;
1993
1994 return 0;
1995 }
1996
1997 static int snd_cs46xx_iec958_put(struct snd_kcontrol *kcontrol,
1998 struct snd_ctl_elem_value *ucontrol)
1999 {
2000 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2001 int change, res;
2002
2003 switch (kcontrol->private_value) {
2004 case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT:
2005 mutex_lock(&chip->spos_mutex);
2006 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
2007 if (ucontrol->value.integer.value[0] && !change)
2008 cs46xx_dsp_enable_spdif_out(chip);
2009 else if (change && !ucontrol->value.integer.value[0])
2010 cs46xx_dsp_disable_spdif_out(chip);
2011
2012 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED));
2013 mutex_unlock(&chip->spos_mutex);
2014 break;
2015 case CS46XX_MIXER_SPDIF_INPUT_ELEMENT:
2016 change = chip->dsp_spos_instance->spdif_status_in;
2017 if (ucontrol->value.integer.value[0] && !change) {
2018 cs46xx_dsp_enable_spdif_in(chip);
2019
2020 }
2021 else if (change && !ucontrol->value.integer.value[0])
2022 cs46xx_dsp_disable_spdif_in(chip);
2023
2024 res = (change != chip->dsp_spos_instance->spdif_status_in);
2025 break;
2026 default:
2027 res = -EINVAL;
2028 snd_BUG();
2029 }
2030
2031 return res;
2032 }
2033
2034 static int snd_cs46xx_adc_capture_get(struct snd_kcontrol *kcontrol,
2035 struct snd_ctl_elem_value *ucontrol)
2036 {
2037 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2038 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2039
2040 if (ins->adc_input != NULL)
2041 ucontrol->value.integer.value[0] = 1;
2042 else
2043 ucontrol->value.integer.value[0] = 0;
2044
2045 return 0;
2046 }
2047
2048 static int snd_cs46xx_adc_capture_put(struct snd_kcontrol *kcontrol,
2049 struct snd_ctl_elem_value *ucontrol)
2050 {
2051 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2052 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2053 int change = 0;
2054
2055 if (ucontrol->value.integer.value[0] && !ins->adc_input) {
2056 cs46xx_dsp_enable_adc_capture(chip);
2057 change = 1;
2058 } else if (!ucontrol->value.integer.value[0] && ins->adc_input) {
2059 cs46xx_dsp_disable_adc_capture(chip);
2060 change = 1;
2061 }
2062 return change;
2063 }
2064
2065 static int snd_cs46xx_pcm_capture_get(struct snd_kcontrol *kcontrol,
2066 struct snd_ctl_elem_value *ucontrol)
2067 {
2068 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2069 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2070
2071 if (ins->pcm_input != NULL)
2072 ucontrol->value.integer.value[0] = 1;
2073 else
2074 ucontrol->value.integer.value[0] = 0;
2075
2076 return 0;
2077 }
2078
2079
2080 static int snd_cs46xx_pcm_capture_put(struct snd_kcontrol *kcontrol,
2081 struct snd_ctl_elem_value *ucontrol)
2082 {
2083 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2084 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2085 int change = 0;
2086
2087 if (ucontrol->value.integer.value[0] && !ins->pcm_input) {
2088 cs46xx_dsp_enable_pcm_capture(chip);
2089 change = 1;
2090 } else if (!ucontrol->value.integer.value[0] && ins->pcm_input) {
2091 cs46xx_dsp_disable_pcm_capture(chip);
2092 change = 1;
2093 }
2094
2095 return change;
2096 }
2097
2098 static int snd_herc_spdif_select_get(struct snd_kcontrol *kcontrol,
2099 struct snd_ctl_elem_value *ucontrol)
2100 {
2101 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2102
2103 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2104
2105 if (val1 & EGPIODR_GPOE0)
2106 ucontrol->value.integer.value[0] = 1;
2107 else
2108 ucontrol->value.integer.value[0] = 0;
2109
2110 return 0;
2111 }
2112
2113
2114
2115
2116 static int snd_herc_spdif_select_put(struct snd_kcontrol *kcontrol,
2117 struct snd_ctl_elem_value *ucontrol)
2118 {
2119 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2120 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2121 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
2122
2123 if (ucontrol->value.integer.value[0]) {
2124
2125 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
2126 EGPIODR_GPOE0 | val1);
2127 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
2128 EGPIOPTR_GPPT0 | val2);
2129 } else {
2130
2131 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE0);
2132 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0);
2133 }
2134
2135
2136
2137 return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR));
2138 }
2139
2140
2141 static int snd_cs46xx_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2142 {
2143 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2144 uinfo->count = 1;
2145 return 0;
2146 }
2147
2148 static int snd_cs46xx_spdif_default_get(struct snd_kcontrol *kcontrol,
2149 struct snd_ctl_elem_value *ucontrol)
2150 {
2151 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2152 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2153
2154 mutex_lock(&chip->spos_mutex);
2155 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff);
2156 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff);
2157 ucontrol->value.iec958.status[2] = 0;
2158 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff);
2159 mutex_unlock(&chip->spos_mutex);
2160
2161 return 0;
2162 }
2163
2164 static int snd_cs46xx_spdif_default_put(struct snd_kcontrol *kcontrol,
2165 struct snd_ctl_elem_value *ucontrol)
2166 {
2167 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2168 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2169 unsigned int val;
2170 int change;
2171
2172 mutex_lock(&chip->spos_mutex);
2173 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2174 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) |
2175 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2176
2177 (1 << 13) | (1 << 12);
2178
2179
2180 change = (unsigned int)ins->spdif_csuv_default != val;
2181 ins->spdif_csuv_default = val;
2182
2183 if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) )
2184 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2185
2186 mutex_unlock(&chip->spos_mutex);
2187
2188 return change;
2189 }
2190
2191 static int snd_cs46xx_spdif_mask_get(struct snd_kcontrol *kcontrol,
2192 struct snd_ctl_elem_value *ucontrol)
2193 {
2194 ucontrol->value.iec958.status[0] = 0xff;
2195 ucontrol->value.iec958.status[1] = 0xff;
2196 ucontrol->value.iec958.status[2] = 0x00;
2197 ucontrol->value.iec958.status[3] = 0xff;
2198 return 0;
2199 }
2200
2201 static int snd_cs46xx_spdif_stream_get(struct snd_kcontrol *kcontrol,
2202 struct snd_ctl_elem_value *ucontrol)
2203 {
2204 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2205 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2206
2207 mutex_lock(&chip->spos_mutex);
2208 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff);
2209 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff);
2210 ucontrol->value.iec958.status[2] = 0;
2211 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff);
2212 mutex_unlock(&chip->spos_mutex);
2213
2214 return 0;
2215 }
2216
2217 static int snd_cs46xx_spdif_stream_put(struct snd_kcontrol *kcontrol,
2218 struct snd_ctl_elem_value *ucontrol)
2219 {
2220 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2221 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2222 unsigned int val;
2223 int change;
2224
2225 mutex_lock(&chip->spos_mutex);
2226 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2227 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) |
2228 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2229
2230 (1 << 13) | (1 << 12);
2231
2232
2233 change = ins->spdif_csuv_stream != val;
2234 ins->spdif_csuv_stream = val;
2235
2236 if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN )
2237 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2238
2239 mutex_unlock(&chip->spos_mutex);
2240
2241 return change;
2242 }
2243
2244 #endif
2245
2246
2247 static struct snd_kcontrol_new snd_cs46xx_controls[] = {
2248 {
2249 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2250 .name = "DAC Volume",
2251 .info = snd_cs46xx_vol_info,
2252 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2253 .get = snd_cs46xx_vol_get,
2254 .put = snd_cs46xx_vol_put,
2255 .private_value = BA1_PVOL,
2256 #else
2257 .get = snd_cs46xx_vol_dac_get,
2258 .put = snd_cs46xx_vol_dac_put,
2259 #endif
2260 },
2261
2262 {
2263 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2264 .name = "ADC Volume",
2265 .info = snd_cs46xx_vol_info,
2266 .get = snd_cs46xx_vol_get,
2267 .put = snd_cs46xx_vol_put,
2268 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2269 .private_value = BA1_CVOL,
2270 #else
2271 .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2,
2272 #endif
2273 },
2274 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2275 {
2276 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2277 .name = "ADC Capture Switch",
2278 .info = snd_mixer_boolean_info,
2279 .get = snd_cs46xx_adc_capture_get,
2280 .put = snd_cs46xx_adc_capture_put
2281 },
2282 {
2283 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2284 .name = "DAC Capture Switch",
2285 .info = snd_mixer_boolean_info,
2286 .get = snd_cs46xx_pcm_capture_get,
2287 .put = snd_cs46xx_pcm_capture_put
2288 },
2289 {
2290 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2291 .name = SNDRV_CTL_NAME_IEC958("Output ",NONE,SWITCH),
2292 .info = snd_mixer_boolean_info,
2293 .get = snd_cs46xx_iec958_get,
2294 .put = snd_cs46xx_iec958_put,
2295 .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT,
2296 },
2297 {
2298 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2299 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,SWITCH),
2300 .info = snd_mixer_boolean_info,
2301 .get = snd_cs46xx_iec958_get,
2302 .put = snd_cs46xx_iec958_put,
2303 .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT,
2304 },
2305 #if 0
2306
2307 {
2308 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2309 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,VOLUME),
2310 .info = snd_cs46xx_vol_info,
2311 .get = snd_cs46xx_vol_iec958_get,
2312 .put = snd_cs46xx_vol_iec958_put,
2313 .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2,
2314 },
2315 #endif
2316 {
2317 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2318 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2319 .info = snd_cs46xx_spdif_info,
2320 .get = snd_cs46xx_spdif_default_get,
2321 .put = snd_cs46xx_spdif_default_put,
2322 },
2323 {
2324 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2325 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
2326 .info = snd_cs46xx_spdif_info,
2327 .get = snd_cs46xx_spdif_mask_get,
2328 .access = SNDRV_CTL_ELEM_ACCESS_READ
2329 },
2330 {
2331 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2332 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2333 .info = snd_cs46xx_spdif_info,
2334 .get = snd_cs46xx_spdif_stream_get,
2335 .put = snd_cs46xx_spdif_stream_put
2336 },
2337
2338 #endif
2339 };
2340
2341 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2342
2343 static int snd_cs46xx_front_dup_get(struct snd_kcontrol *kcontrol,
2344 struct snd_ctl_elem_value *ucontrol)
2345 {
2346 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2347 unsigned short val;
2348 val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE);
2349 ucontrol->value.integer.value[0] = (val & 0x200) ? 0 : 1;
2350 return 0;
2351 }
2352
2353 static int snd_cs46xx_front_dup_put(struct snd_kcontrol *kcontrol,
2354 struct snd_ctl_elem_value *ucontrol)
2355 {
2356 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2357 return snd_ac97_update_bits(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2358 AC97_CSR_ACMODE, 0x200,
2359 ucontrol->value.integer.value[0] ? 0 : 0x200);
2360 }
2361
2362 static const struct snd_kcontrol_new snd_cs46xx_front_dup_ctl = {
2363 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2364 .name = "Duplicate Front",
2365 .info = snd_mixer_boolean_info,
2366 .get = snd_cs46xx_front_dup_get,
2367 .put = snd_cs46xx_front_dup_put,
2368 };
2369 #endif
2370
2371 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2372
2373 static struct snd_kcontrol_new snd_hercules_controls[] = {
2374 {
2375 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2376 .name = "Optical/Coaxial SPDIF Input Switch",
2377 .info = snd_mixer_boolean_info,
2378 .get = snd_herc_spdif_select_get,
2379 .put = snd_herc_spdif_select_put,
2380 },
2381 };
2382
2383
2384 static void snd_cs46xx_codec_reset (struct snd_ac97 * ac97)
2385 {
2386 unsigned long end_time;
2387 int err;
2388
2389
2390 snd_ac97_write(ac97, AC97_RESET, 0);
2391
2392
2393 if (ac97->num == CS46XX_PRIMARY_CODEC_INDEX) {
2394 dev_dbg(ac97->bus->card->dev, "CODEC1 mode %04x\n", 0x0);
2395 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x0);
2396 } else if (ac97->num == CS46XX_SECONDARY_CODEC_INDEX) {
2397 dev_dbg(ac97->bus->card->dev, "CODEC2 mode %04x\n", 0x3);
2398 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x3);
2399 } else {
2400 snd_BUG();
2401 }
2402
2403 udelay(50);
2404
2405
2406
2407
2408 end_time = jiffies + HZ;
2409 do {
2410 unsigned short ext_mid;
2411
2412
2413 snd_ac97_read(ac97, AC97_RESET);
2414 snd_ac97_read(ac97, AC97_VENDOR_ID1);
2415 snd_ac97_read(ac97, AC97_VENDOR_ID2);
2416
2417 ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID);
2418 if (ext_mid != 0xffff && (ext_mid & 1) != 0)
2419 return;
2420
2421
2422 snd_ac97_write(ac97, AC97_REC_GAIN, 0x8a05);
2423 if ((err = snd_ac97_read(ac97, AC97_REC_GAIN)) == 0x8a05)
2424 return;
2425
2426 msleep(10);
2427 } while (time_after_eq(end_time, jiffies));
2428
2429 dev_err(ac97->bus->card->dev,
2430 "CS46xx secondary codec doesn't respond!\n");
2431 }
2432 #endif
2433
2434 static int cs46xx_detect_codec(struct snd_cs46xx *chip, int codec)
2435 {
2436 int idx, err;
2437 struct snd_ac97_template ac97;
2438
2439 memset(&ac97, 0, sizeof(ac97));
2440 ac97.private_data = chip;
2441 ac97.private_free = snd_cs46xx_mixer_free_ac97;
2442 ac97.num = codec;
2443 if (chip->amplifier_ctrl == amp_voyetra)
2444 ac97.scaps = AC97_SCAP_INV_EAPD;
2445
2446 if (codec == CS46XX_SECONDARY_CODEC_INDEX) {
2447 snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec);
2448 udelay(10);
2449 if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) {
2450 dev_dbg(chip->card->dev,
2451 "secondary codec not present\n");
2452 return -ENXIO;
2453 }
2454 }
2455
2456 snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec);
2457 for (idx = 0; idx < 100; ++idx) {
2458 if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) {
2459 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]);
2460 return err;
2461 }
2462 msleep(10);
2463 }
2464 dev_dbg(chip->card->dev, "codec %d detection timeout\n", codec);
2465 return -ENXIO;
2466 }
2467
2468 int snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device)
2469 {
2470 struct snd_card *card = chip->card;
2471 struct snd_ctl_elem_id id;
2472 int err;
2473 unsigned int idx;
2474 static struct snd_ac97_bus_ops ops = {
2475 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2476 .reset = snd_cs46xx_codec_reset,
2477 #endif
2478 .write = snd_cs46xx_ac97_write,
2479 .read = snd_cs46xx_ac97_read,
2480 };
2481
2482
2483 chip->nr_ac97_codecs = 0;
2484 dev_dbg(chip->card->dev, "detecting primary codec\n");
2485 if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
2486 return err;
2487 chip->ac97_bus->private_free = snd_cs46xx_mixer_free_ac97_bus;
2488
2489 if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0)
2490 return -ENXIO;
2491 chip->nr_ac97_codecs = 1;
2492
2493 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2494 dev_dbg(chip->card->dev, "detecting secondary codec\n");
2495
2496 if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX))
2497 chip->nr_ac97_codecs = 2;
2498 #endif
2499
2500
2501 for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) {
2502 struct snd_kcontrol *kctl;
2503 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip);
2504 if (kctl && kctl->id.iface == SNDRV_CTL_ELEM_IFACE_PCM)
2505 kctl->id.device = spdif_device;
2506 if ((err = snd_ctl_add(card, kctl)) < 0)
2507 return err;
2508 }
2509
2510
2511 memset(&id, 0, sizeof(id));
2512 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2513 strcpy(id.name, "External Amplifier");
2514 chip->eapd_switch = snd_ctl_find_id(chip->card, &id);
2515
2516 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2517 if (chip->nr_ac97_codecs == 1) {
2518 unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff;
2519 if ((id2 & 0xfff0) == 0x5920) {
2520 err = snd_ctl_add(card, snd_ctl_new1(&snd_cs46xx_front_dup_ctl, chip));
2521 if (err < 0)
2522 return err;
2523 snd_ac97_write_cache(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2524 AC97_CSR_ACMODE, 0x200);
2525 }
2526 }
2527
2528 if (chip->mixer_init) {
2529 dev_dbg(chip->card->dev, "calling chip->mixer_init(chip);\n");
2530 chip->mixer_init(chip);
2531 }
2532 #endif
2533
2534
2535 chip->amplifier_ctrl(chip, 1);
2536
2537 return 0;
2538 }
2539
2540
2541
2542
2543
2544 static void snd_cs46xx_midi_reset(struct snd_cs46xx *chip)
2545 {
2546 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST);
2547 udelay(100);
2548 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2549 }
2550
2551 static int snd_cs46xx_midi_input_open(struct snd_rawmidi_substream *substream)
2552 {
2553 struct snd_cs46xx *chip = substream->rmidi->private_data;
2554
2555 chip->active_ctrl(chip, 1);
2556 spin_lock_irq(&chip->reg_lock);
2557 chip->uartm |= CS46XX_MODE_INPUT;
2558 chip->midcr |= MIDCR_RXE;
2559 chip->midi_input = substream;
2560 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2561 snd_cs46xx_midi_reset(chip);
2562 } else {
2563 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2564 }
2565 spin_unlock_irq(&chip->reg_lock);
2566 return 0;
2567 }
2568
2569 static int snd_cs46xx_midi_input_close(struct snd_rawmidi_substream *substream)
2570 {
2571 struct snd_cs46xx *chip = substream->rmidi->private_data;
2572
2573 spin_lock_irq(&chip->reg_lock);
2574 chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE);
2575 chip->midi_input = NULL;
2576 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2577 snd_cs46xx_midi_reset(chip);
2578 } else {
2579 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2580 }
2581 chip->uartm &= ~CS46XX_MODE_INPUT;
2582 spin_unlock_irq(&chip->reg_lock);
2583 chip->active_ctrl(chip, -1);
2584 return 0;
2585 }
2586
2587 static int snd_cs46xx_midi_output_open(struct snd_rawmidi_substream *substream)
2588 {
2589 struct snd_cs46xx *chip = substream->rmidi->private_data;
2590
2591 chip->active_ctrl(chip, 1);
2592
2593 spin_lock_irq(&chip->reg_lock);
2594 chip->uartm |= CS46XX_MODE_OUTPUT;
2595 chip->midcr |= MIDCR_TXE;
2596 chip->midi_output = substream;
2597 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2598 snd_cs46xx_midi_reset(chip);
2599 } else {
2600 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2601 }
2602 spin_unlock_irq(&chip->reg_lock);
2603 return 0;
2604 }
2605
2606 static int snd_cs46xx_midi_output_close(struct snd_rawmidi_substream *substream)
2607 {
2608 struct snd_cs46xx *chip = substream->rmidi->private_data;
2609
2610 spin_lock_irq(&chip->reg_lock);
2611 chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE);
2612 chip->midi_output = NULL;
2613 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2614 snd_cs46xx_midi_reset(chip);
2615 } else {
2616 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2617 }
2618 chip->uartm &= ~CS46XX_MODE_OUTPUT;
2619 spin_unlock_irq(&chip->reg_lock);
2620 chip->active_ctrl(chip, -1);
2621 return 0;
2622 }
2623
2624 static void snd_cs46xx_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2625 {
2626 unsigned long flags;
2627 struct snd_cs46xx *chip = substream->rmidi->private_data;
2628
2629 spin_lock_irqsave(&chip->reg_lock, flags);
2630 if (up) {
2631 if ((chip->midcr & MIDCR_RIE) == 0) {
2632 chip->midcr |= MIDCR_RIE;
2633 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2634 }
2635 } else {
2636 if (chip->midcr & MIDCR_RIE) {
2637 chip->midcr &= ~MIDCR_RIE;
2638 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2639 }
2640 }
2641 spin_unlock_irqrestore(&chip->reg_lock, flags);
2642 }
2643
2644 static void snd_cs46xx_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2645 {
2646 unsigned long flags;
2647 struct snd_cs46xx *chip = substream->rmidi->private_data;
2648 unsigned char byte;
2649
2650 spin_lock_irqsave(&chip->reg_lock, flags);
2651 if (up) {
2652 if ((chip->midcr & MIDCR_TIE) == 0) {
2653 chip->midcr |= MIDCR_TIE;
2654
2655 while ((chip->midcr & MIDCR_TIE) &&
2656 (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
2657 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2658 chip->midcr &= ~MIDCR_TIE;
2659 } else {
2660 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte);
2661 }
2662 }
2663 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2664 }
2665 } else {
2666 if (chip->midcr & MIDCR_TIE) {
2667 chip->midcr &= ~MIDCR_TIE;
2668 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2669 }
2670 }
2671 spin_unlock_irqrestore(&chip->reg_lock, flags);
2672 }
2673
2674 static const struct snd_rawmidi_ops snd_cs46xx_midi_output =
2675 {
2676 .open = snd_cs46xx_midi_output_open,
2677 .close = snd_cs46xx_midi_output_close,
2678 .trigger = snd_cs46xx_midi_output_trigger,
2679 };
2680
2681 static const struct snd_rawmidi_ops snd_cs46xx_midi_input =
2682 {
2683 .open = snd_cs46xx_midi_input_open,
2684 .close = snd_cs46xx_midi_input_close,
2685 .trigger = snd_cs46xx_midi_input_trigger,
2686 };
2687
2688 int snd_cs46xx_midi(struct snd_cs46xx *chip, int device)
2689 {
2690 struct snd_rawmidi *rmidi;
2691 int err;
2692
2693 if ((err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi)) < 0)
2694 return err;
2695 strcpy(rmidi->name, "CS46XX");
2696 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output);
2697 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input);
2698 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2699 rmidi->private_data = chip;
2700 chip->rmidi = rmidi;
2701 return 0;
2702 }
2703
2704
2705
2706
2707
2708
2709 #if IS_REACHABLE(CONFIG_GAMEPORT)
2710
2711 static void snd_cs46xx_gameport_trigger(struct gameport *gameport)
2712 {
2713 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2714
2715 if (snd_BUG_ON(!chip))
2716 return;
2717 snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF);
2718 }
2719
2720 static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport)
2721 {
2722 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2723
2724 if (snd_BUG_ON(!chip))
2725 return 0;
2726 return snd_cs46xx_peekBA0(chip, BA0_JSPT);
2727 }
2728
2729 static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
2730 {
2731 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2732 unsigned js1, js2, jst;
2733
2734 if (snd_BUG_ON(!chip))
2735 return 0;
2736
2737 js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1);
2738 js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2);
2739 jst = snd_cs46xx_peekBA0(chip, BA0_JSPT);
2740
2741 *buttons = (~jst >> 4) & 0x0F;
2742
2743 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
2744 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
2745 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
2746 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
2747
2748 for(jst=0;jst<4;++jst)
2749 if(axes[jst]==0xFFFF) axes[jst] = -1;
2750 return 0;
2751 }
2752
2753 static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode)
2754 {
2755 switch (mode) {
2756 case GAMEPORT_MODE_COOKED:
2757 return 0;
2758 case GAMEPORT_MODE_RAW:
2759 return 0;
2760 default:
2761 return -1;
2762 }
2763 return 0;
2764 }
2765
2766 int snd_cs46xx_gameport(struct snd_cs46xx *chip)
2767 {
2768 struct gameport *gp;
2769
2770 chip->gameport = gp = gameport_allocate_port();
2771 if (!gp) {
2772 dev_err(chip->card->dev,
2773 "cannot allocate memory for gameport\n");
2774 return -ENOMEM;
2775 }
2776
2777 gameport_set_name(gp, "CS46xx Gameport");
2778 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2779 gameport_set_dev_parent(gp, &chip->pci->dev);
2780 gameport_set_port_data(gp, chip);
2781
2782 gp->open = snd_cs46xx_gameport_open;
2783 gp->read = snd_cs46xx_gameport_read;
2784 gp->trigger = snd_cs46xx_gameport_trigger;
2785 gp->cooked_read = snd_cs46xx_gameport_cooked_read;
2786
2787 snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF);
2788 snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
2789
2790 gameport_register_port(gp);
2791
2792 return 0;
2793 }
2794
2795 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip)
2796 {
2797 if (chip->gameport) {
2798 gameport_unregister_port(chip->gameport);
2799 chip->gameport = NULL;
2800 }
2801 }
2802 #else
2803 int snd_cs46xx_gameport(struct snd_cs46xx *chip) { return -ENOSYS; }
2804 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) { }
2805 #endif
2806
2807 #ifdef CONFIG_SND_PROC_FS
2808
2809
2810
2811
2812 static ssize_t snd_cs46xx_io_read(struct snd_info_entry *entry,
2813 void *file_private_data,
2814 struct file *file, char __user *buf,
2815 size_t count, loff_t pos)
2816 {
2817 struct snd_cs46xx_region *region = entry->private_data;
2818
2819 if (copy_to_user_fromio(buf, region->remap_addr + pos, count))
2820 return -EFAULT;
2821 return count;
2822 }
2823
2824 static struct snd_info_entry_ops snd_cs46xx_proc_io_ops = {
2825 .read = snd_cs46xx_io_read,
2826 };
2827
2828 static int snd_cs46xx_proc_init(struct snd_card *card, struct snd_cs46xx *chip)
2829 {
2830 struct snd_info_entry *entry;
2831 int idx;
2832
2833 for (idx = 0; idx < 5; idx++) {
2834 struct snd_cs46xx_region *region = &chip->region.idx[idx];
2835 if (! snd_card_proc_new(card, region->name, &entry)) {
2836 entry->content = SNDRV_INFO_CONTENT_DATA;
2837 entry->private_data = chip;
2838 entry->c.ops = &snd_cs46xx_proc_io_ops;
2839 entry->size = region->size;
2840 entry->mode = S_IFREG | 0400;
2841 }
2842 }
2843 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2844 cs46xx_dsp_proc_init(card, chip);
2845 #endif
2846 return 0;
2847 }
2848
2849 static int snd_cs46xx_proc_done(struct snd_cs46xx *chip)
2850 {
2851 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2852 cs46xx_dsp_proc_done(chip);
2853 #endif
2854 return 0;
2855 }
2856 #else
2857 #define snd_cs46xx_proc_init(card, chip)
2858 #define snd_cs46xx_proc_done(chip)
2859 #endif
2860
2861
2862
2863
2864 static void snd_cs46xx_hw_stop(struct snd_cs46xx *chip)
2865 {
2866 unsigned int tmp;
2867
2868 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
2869 tmp &= ~0x0000f03f;
2870 tmp |= 0x00000010;
2871 snd_cs46xx_poke(chip, BA1_PFIE, tmp);
2872
2873 tmp = snd_cs46xx_peek(chip, BA1_CIE);
2874 tmp &= ~0x0000003f;
2875 tmp |= 0x00000011;
2876 snd_cs46xx_poke(chip, BA1_CIE, tmp);
2877
2878
2879
2880
2881 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
2882 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
2883
2884
2885
2886
2887 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
2888 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
2889
2890
2891
2892
2893 snd_cs46xx_reset(chip);
2894
2895 snd_cs46xx_proc_stop(chip);
2896
2897
2898
2899
2900 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2901
2902
2903
2904
2905
2906 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE;
2907 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
2908 }
2909
2910
2911 static int snd_cs46xx_free(struct snd_cs46xx *chip)
2912 {
2913 int idx;
2914
2915 if (snd_BUG_ON(!chip))
2916 return -EINVAL;
2917
2918 if (chip->active_ctrl)
2919 chip->active_ctrl(chip, 1);
2920
2921 snd_cs46xx_remove_gameport(chip);
2922
2923 if (chip->amplifier_ctrl)
2924 chip->amplifier_ctrl(chip, -chip->amplifier);
2925
2926 snd_cs46xx_proc_done(chip);
2927
2928 if (chip->region.idx[0].resource)
2929 snd_cs46xx_hw_stop(chip);
2930
2931 if (chip->irq >= 0)
2932 free_irq(chip->irq, chip);
2933
2934 if (chip->active_ctrl)
2935 chip->active_ctrl(chip, -chip->amplifier);
2936
2937 for (idx = 0; idx < 5; idx++) {
2938 struct snd_cs46xx_region *region = &chip->region.idx[idx];
2939
2940 iounmap(region->remap_addr);
2941 release_and_free_resource(region->resource);
2942 }
2943
2944 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2945 if (chip->dsp_spos_instance) {
2946 cs46xx_dsp_spos_destroy(chip);
2947 chip->dsp_spos_instance = NULL;
2948 }
2949 for (idx = 0; idx < CS46XX_DSP_MODULES; idx++)
2950 free_module_desc(chip->modules[idx]);
2951 #else
2952 vfree(chip->ba1);
2953 #endif
2954
2955 #ifdef CONFIG_PM_SLEEP
2956 kfree(chip->saved_regs);
2957 #endif
2958
2959 pci_disable_device(chip->pci);
2960 kfree(chip);
2961 return 0;
2962 }
2963
2964 static int snd_cs46xx_dev_free(struct snd_device *device)
2965 {
2966 struct snd_cs46xx *chip = device->device_data;
2967 return snd_cs46xx_free(chip);
2968 }
2969
2970
2971
2972
2973 static int snd_cs46xx_chip_init(struct snd_cs46xx *chip)
2974 {
2975 int timeout;
2976
2977
2978
2979
2980
2981
2982 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2983 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0);
2984
2985
2986
2987
2988
2989 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2990 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 |
2991 SERACC_TWO_CODECS);
2992
2993 #else
2994 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03);
2995 #endif
2996
2997
2998
2999
3000
3001
3002
3003 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0);
3004 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3005 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0);
3006 #endif
3007 udelay(50);
3008 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN);
3009 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3010 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN);
3011 #endif
3012
3013
3014
3015
3016
3017
3018 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
3019 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3020 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN);
3021 #endif
3022
3023
3024
3025
3026
3027
3028 mdelay(10);
3029
3030
3031
3032
3033
3034 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97);
3035
3036
3037
3038
3039
3040
3041 snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
3042 snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a);
3043 snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8);
3044
3045
3046
3047
3048 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP);
3049
3050
3051
3052
3053 msleep(100);
3054
3055
3056
3057
3058 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE);
3059
3060
3061
3062
3063 snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP);
3064
3065
3066
3067
3068 snd_cs46xx_clear_serial_FIFOs(chip);
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079 snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
3080 snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
3081 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
3082
3083
3084 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3085 snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN);
3086 snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0);
3087 snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0);
3088 snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0);
3089 snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1);
3090 #endif
3091
3092 mdelay(5);
3093
3094
3095
3096
3097
3098 timeout = 150;
3099 while (timeout-- > 0) {
3100
3101
3102
3103
3104 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY)
3105 goto ok1;
3106 msleep(10);
3107 }
3108
3109
3110 dev_err(chip->card->dev,
3111 "create - never read codec ready from AC'97\n");
3112 dev_err(chip->card->dev,
3113 "it is not probably bug, try to use CS4236 driver\n");
3114 return -EIO;
3115 ok1:
3116 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3117 {
3118 int count;
3119 for (count = 0; count < 150; count++) {
3120
3121 udelay(25);
3122
3123 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)
3124 break;
3125 }
3126
3127
3128
3129
3130 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY))
3131 dev_dbg(chip->card->dev,
3132 "never read card ready from secondary AC'97\n");
3133 }
3134 #endif
3135
3136
3137
3138
3139
3140 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3141 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3142 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3143 #endif
3144
3145
3146
3147
3148
3149
3150 timeout = 150;
3151 while (timeout-- > 0) {
3152
3153
3154
3155
3156 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
3157 goto ok2;
3158 msleep(10);
3159 }
3160
3161 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3162 dev_err(chip->card->dev,
3163 "create - never read ISV3 & ISV4 from AC'97\n");
3164 return -EIO;
3165 #else
3166
3167
3168
3169
3170 dev_err(chip->card->dev, "never read ISV3 & ISV4 from AC'97\n");
3171 dev_err(chip->card->dev,
3172 "Try reloading the ALSA driver, if you find something\n");
3173 dev_err(chip->card->dev,
3174 "broken or not working on your soundcard upon\n");
3175 dev_err(chip->card->dev,
3176 "this message please report to alsa-devel@alsa-project.org\n");
3177
3178 return -EIO;
3179 #endif
3180 ok2:
3181
3182
3183
3184
3185
3186
3187 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203 return 0;
3204 }
3205
3206
3207
3208
3209
3210 static void cs46xx_enable_stream_irqs(struct snd_cs46xx *chip)
3211 {
3212 unsigned int tmp;
3213
3214 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM);
3215
3216 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
3217 tmp &= ~0x0000f03f;
3218 snd_cs46xx_poke(chip, BA1_PFIE, tmp);
3219
3220 tmp = snd_cs46xx_peek(chip, BA1_CIE);
3221 tmp &= ~0x0000003f;
3222 tmp |= 0x00000001;
3223 snd_cs46xx_poke(chip, BA1_CIE, tmp);
3224 }
3225
3226 int snd_cs46xx_start_dsp(struct snd_cs46xx *chip)
3227 {
3228 unsigned int tmp;
3229 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3230 int i;
3231 #endif
3232 int err;
3233
3234
3235
3236
3237 snd_cs46xx_reset(chip);
3238
3239
3240
3241 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3242 for (i = 0; i < CS46XX_DSP_MODULES; i++) {
3243 err = load_firmware(chip, &chip->modules[i], module_names[i]);
3244 if (err < 0) {
3245 dev_err(chip->card->dev, "firmware load error [%s]\n",
3246 module_names[i]);
3247 return err;
3248 }
3249 err = cs46xx_dsp_load_module(chip, chip->modules[i]);
3250 if (err < 0) {
3251 dev_err(chip->card->dev, "image download error [%s]\n",
3252 module_names[i]);
3253 return err;
3254 }
3255 }
3256
3257 if (cs46xx_dsp_scb_and_task_init(chip) < 0)
3258 return -EIO;
3259 #else
3260 err = load_firmware(chip);
3261 if (err < 0)
3262 return err;
3263
3264
3265 err = snd_cs46xx_download_image(chip);
3266 if (err < 0) {
3267 dev_err(chip->card->dev, "image download error\n");
3268 return err;
3269 }
3270
3271
3272
3273
3274 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
3275 chip->play_ctl = tmp & 0xffff0000;
3276 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
3277 #endif
3278
3279
3280
3281
3282 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3283 chip->capt.ctl = tmp & 0x0000ffff;
3284 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3285
3286 mdelay(5);
3287
3288 snd_cs46xx_set_play_sample_rate(chip, 8000);
3289 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3290
3291 snd_cs46xx_proc_start(chip);
3292
3293 cs46xx_enable_stream_irqs(chip);
3294
3295 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3296
3297 snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000);
3298 snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000);
3299 #endif
3300
3301 return 0;
3302 }
3303
3304
3305
3306
3307
3308
3309 static void amp_none(struct snd_cs46xx *chip, int change)
3310 {
3311 }
3312
3313 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3314 static int voyetra_setup_eapd_slot(struct snd_cs46xx *chip)
3315 {
3316
3317 u32 idx, valid_slots,tmp,powerdown = 0;
3318 u16 modem_power,pin_config,logic_type;
3319
3320 dev_dbg(chip->card->dev, "cs46xx_setup_eapd_slot()+\n");
3321
3322
3323
3324
3325
3326 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
3327
3328 if (!(tmp & CLKCR1_SWCE)) {
3329 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
3330 powerdown = 1;
3331 }
3332
3333
3334
3335
3336
3337 if(chip->nr_ac97_codecs != 2) {
3338 dev_err(chip->card->dev,
3339 "cs46xx_setup_eapd_slot() - no secondary codec configured\n");
3340 return -EINVAL;
3341 }
3342
3343 modem_power = snd_cs46xx_codec_read (chip,
3344 AC97_EXTENDED_MSTATUS,
3345 CS46XX_SECONDARY_CODEC_INDEX);
3346 modem_power &=0xFEFF;
3347
3348 snd_cs46xx_codec_write(chip,
3349 AC97_EXTENDED_MSTATUS, modem_power,
3350 CS46XX_SECONDARY_CODEC_INDEX);
3351
3352
3353
3354
3355 pin_config = snd_cs46xx_codec_read (chip,
3356 AC97_GPIO_CFG,
3357 CS46XX_SECONDARY_CODEC_INDEX);
3358 pin_config &=0x27F;
3359
3360 snd_cs46xx_codec_write(chip,
3361 AC97_GPIO_CFG, pin_config,
3362 CS46XX_SECONDARY_CODEC_INDEX);
3363
3364
3365
3366
3367
3368 logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY,
3369 CS46XX_SECONDARY_CODEC_INDEX);
3370 logic_type &=0x27F;
3371
3372 snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type,
3373 CS46XX_SECONDARY_CODEC_INDEX);
3374
3375 valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
3376 valid_slots |= 0x200;
3377 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
3378
3379 if ( cs46xx_wait_for_fifo(chip,1) ) {
3380 dev_dbg(chip->card->dev, "FIFO is busy\n");
3381
3382 return -EINVAL;
3383 }
3384
3385
3386
3387
3388 for(idx = 0x90; idx <= 0x9F; idx++) {
3389
3390
3391
3392
3393
3394
3395 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800);
3396
3397
3398
3399
3400 if ( cs46xx_wait_for_fifo(chip,200) ) {
3401 dev_dbg(chip->card->dev,
3402 "failed waiting for FIFO at addr (%02X)\n",
3403 idx);
3404
3405 return -EINVAL;
3406 }
3407
3408
3409
3410
3411 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
3412
3413
3414
3415
3416 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
3417 }
3418
3419
3420 cs46xx_wait_for_fifo(chip,200);
3421
3422
3423
3424
3425
3426 if (powerdown)
3427 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
3428
3429 return 0;
3430 }
3431 #endif
3432
3433
3434
3435
3436
3437 static void amp_voyetra(struct snd_cs46xx *chip, int change)
3438 {
3439
3440
3441
3442 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3443 int old = chip->amplifier;
3444 #endif
3445 int oval, val;
3446
3447 chip->amplifier += change;
3448 oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN,
3449 CS46XX_PRIMARY_CODEC_INDEX);
3450 val = oval;
3451 if (chip->amplifier) {
3452
3453 val |= 0x8000;
3454 } else {
3455
3456 val &= ~0x8000;
3457 }
3458 if (val != oval) {
3459 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val,
3460 CS46XX_PRIMARY_CODEC_INDEX);
3461 if (chip->eapd_switch)
3462 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
3463 &chip->eapd_switch->id);
3464 }
3465
3466 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3467 if (chip->amplifier && !old) {
3468 voyetra_setup_eapd_slot(chip);
3469 }
3470 #endif
3471 }
3472
3473 static void hercules_init(struct snd_cs46xx *chip)
3474 {
3475
3476 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3477 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3478 }
3479
3480
3481
3482
3483
3484 static void amp_hercules(struct snd_cs46xx *chip, int change)
3485 {
3486 int old = chip->amplifier;
3487 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
3488 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
3489
3490 chip->amplifier += change;
3491 if (chip->amplifier && !old) {
3492 dev_dbg(chip->card->dev, "Hercules amplifier ON\n");
3493
3494 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
3495 EGPIODR_GPOE2 | val1);
3496 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
3497 EGPIOPTR_GPPT2 | val2);
3498 } else if (old && !chip->amplifier) {
3499 dev_dbg(chip->card->dev, "Hercules amplifier OFF\n");
3500 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE2);
3501 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2);
3502 }
3503 }
3504
3505 static void voyetra_mixer_init (struct snd_cs46xx *chip)
3506 {
3507 dev_dbg(chip->card->dev, "initializing Voyetra mixer\n");
3508
3509
3510 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3511 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3512 }
3513
3514 static void hercules_mixer_init (struct snd_cs46xx *chip)
3515 {
3516 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3517 unsigned int idx;
3518 int err;
3519 struct snd_card *card = chip->card;
3520 #endif
3521
3522
3523 hercules_init(chip);
3524
3525 dev_dbg(chip->card->dev, "initializing Hercules mixer\n");
3526
3527 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3528 if (chip->in_suspend)
3529 return;
3530
3531 for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) {
3532 struct snd_kcontrol *kctl;
3533
3534 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip);
3535 if ((err = snd_ctl_add(card, kctl)) < 0) {
3536 dev_err(card->dev,
3537 "failed to initialize Hercules mixer (%d)\n",
3538 err);
3539 break;
3540 }
3541 }
3542 #endif
3543 }
3544
3545
3546 #if 0
3547
3548
3549
3550
3551 static void amp_voyetra_4294(struct snd_cs46xx *chip, int change)
3552 {
3553 chip->amplifier += change;
3554
3555 if (chip->amplifier) {
3556
3557 snd_cs46xx_codec_write(chip, 0x4C,
3558 snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F);
3559 snd_cs46xx_codec_write(chip, 0x4E,
3560 snd_cs46xx_codec_read(chip, 0x4E) | 0x0180);
3561
3562 snd_cs46xx_codec_write(chip, 0x54,
3563 snd_cs46xx_codec_read(chip, 0x54) & ~0x0180);
3564 } else {
3565 snd_cs46xx_codec_write(chip, 0x54,
3566 snd_cs46xx_codec_read(chip, 0x54) | 0x0180);
3567 }
3568 }
3569 #endif
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581 static void clkrun_hack(struct snd_cs46xx *chip, int change)
3582 {
3583 u16 control, nval;
3584
3585 if (!chip->acpi_port)
3586 return;
3587
3588 chip->amplifier += change;
3589
3590
3591 nval = control = inw(chip->acpi_port + 0x10);
3592
3593
3594 if (! chip->amplifier)
3595 nval |= 0x2000;
3596 else
3597 nval &= ~0x2000;
3598 if (nval != control)
3599 outw(nval, chip->acpi_port + 0x10);
3600 }
3601
3602
3603
3604
3605
3606 static void clkrun_init(struct snd_cs46xx *chip)
3607 {
3608 struct pci_dev *pdev;
3609 u8 pp;
3610
3611 chip->acpi_port = 0;
3612
3613 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
3614 PCI_DEVICE_ID_INTEL_82371AB_3, NULL);
3615 if (pdev == NULL)
3616 return;
3617
3618
3619 pci_read_config_byte(pdev, 0x41, &pp);
3620 chip->acpi_port = pp << 8;
3621 pci_dev_put(pdev);
3622 }
3623
3624
3625
3626
3627
3628
3629 struct cs_card_type
3630 {
3631 u16 vendor;
3632 u16 id;
3633 char *name;
3634 void (*init)(struct snd_cs46xx *);
3635 void (*amp)(struct snd_cs46xx *, int);
3636 void (*active)(struct snd_cs46xx *, int);
3637 void (*mixer_init)(struct snd_cs46xx *);
3638 };
3639
3640 static struct cs_card_type cards[] = {
3641 {
3642 .vendor = 0x1489,
3643 .id = 0x7001,
3644 .name = "Genius Soundmaker 128 value",
3645
3646 },
3647 {
3648 .vendor = 0x5053,
3649 .id = 0x3357,
3650 .name = "Voyetra",
3651 .amp = amp_voyetra,
3652 .mixer_init = voyetra_mixer_init,
3653 },
3654 {
3655 .vendor = 0x1071,
3656 .id = 0x6003,
3657 .name = "Mitac MI6020/21",
3658 .amp = amp_voyetra,
3659 },
3660
3661 {
3662 .vendor = 0x14af,
3663 .id = 0x0050,
3664 .name = "Hercules Game Theatre XP",
3665 .amp = amp_hercules,
3666 .mixer_init = hercules_mixer_init,
3667 },
3668 {
3669 .vendor = 0x1681,
3670 .id = 0x0050,
3671 .name = "Hercules Game Theatre XP",
3672 .amp = amp_hercules,
3673 .mixer_init = hercules_mixer_init,
3674 },
3675 {
3676 .vendor = 0x1681,
3677 .id = 0x0051,
3678 .name = "Hercules Game Theatre XP",
3679 .amp = amp_hercules,
3680 .mixer_init = hercules_mixer_init,
3681
3682 },
3683 {
3684 .vendor = 0x1681,
3685 .id = 0x0052,
3686 .name = "Hercules Game Theatre XP",
3687 .amp = amp_hercules,
3688 .mixer_init = hercules_mixer_init,
3689 },
3690 {
3691 .vendor = 0x1681,
3692 .id = 0x0053,
3693 .name = "Hercules Game Theatre XP",
3694 .amp = amp_hercules,
3695 .mixer_init = hercules_mixer_init,
3696 },
3697 {
3698 .vendor = 0x1681,
3699 .id = 0x0054,
3700 .name = "Hercules Game Theatre XP",
3701 .amp = amp_hercules,
3702 .mixer_init = hercules_mixer_init,
3703 },
3704
3705 {
3706 .vendor = 0x1681,
3707 .id = 0xa010,
3708 .name = "Hercules Gamesurround Fortissimo II",
3709 },
3710 {
3711 .vendor = 0x1681,
3712 .id = 0xa011,
3713 .name = "Hercules Gamesurround Fortissimo III 7.1",
3714 },
3715
3716 {
3717 .vendor = 0x153b,
3718 .id = 0x112e,
3719 .name = "Terratec DMX XFire 1024",
3720 },
3721 {
3722 .vendor = 0x153b,
3723 .id = 0x1136,
3724 .name = "Terratec SiXPack 5.1",
3725 },
3726
3727 {
3728 .vendor = PCI_VENDOR_ID_IBM,
3729 .id = 0x0132,
3730 .name = "Thinkpad 570",
3731 .init = clkrun_init,
3732 .active = clkrun_hack,
3733 },
3734 {
3735 .vendor = PCI_VENDOR_ID_IBM,
3736 .id = 0x0153,
3737 .name = "Thinkpad 600X/A20/T20",
3738 .init = clkrun_init,
3739 .active = clkrun_hack,
3740 },
3741 {
3742 .vendor = PCI_VENDOR_ID_IBM,
3743 .id = 0x1010,
3744 .name = "Thinkpad 600E (unsupported)",
3745 },
3746 {}
3747 };
3748
3749
3750
3751
3752
3753 #ifdef CONFIG_PM_SLEEP
3754 static unsigned int saved_regs[] = {
3755 BA0_ACOSV,
3756
3757 BA0_ASER_MASTER,
3758 BA1_PVOL,
3759 BA1_CVOL,
3760 };
3761
3762 static int snd_cs46xx_suspend(struct device *dev)
3763 {
3764 struct snd_card *card = dev_get_drvdata(dev);
3765 struct snd_cs46xx *chip = card->private_data;
3766 int i, amp_saved;
3767
3768 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3769 chip->in_suspend = 1;
3770
3771
3772
3773 snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3774 snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3775
3776
3777 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3778 chip->saved_regs[i] = snd_cs46xx_peekBA0(chip, saved_regs[i]);
3779
3780 amp_saved = chip->amplifier;
3781
3782 chip->amplifier_ctrl(chip, -chip->amplifier);
3783 snd_cs46xx_hw_stop(chip);
3784
3785 chip->active_ctrl(chip, -chip->amplifier);
3786 chip->amplifier = amp_saved;
3787 return 0;
3788 }
3789
3790 static int snd_cs46xx_resume(struct device *dev)
3791 {
3792 struct snd_card *card = dev_get_drvdata(dev);
3793 struct snd_cs46xx *chip = card->private_data;
3794 int amp_saved;
3795 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3796 int i;
3797 #endif
3798 unsigned int tmp;
3799
3800 amp_saved = chip->amplifier;
3801 chip->amplifier = 0;
3802 chip->active_ctrl(chip, 1);
3803
3804 snd_cs46xx_chip_init(chip);
3805
3806 snd_cs46xx_reset(chip);
3807 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3808 cs46xx_dsp_resume(chip);
3809
3810 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3811 snd_cs46xx_pokeBA0(chip, saved_regs[i], chip->saved_regs[i]);
3812 #else
3813 snd_cs46xx_download_image(chip);
3814 #endif
3815
3816 #if 0
3817 snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE,
3818 chip->ac97_general_purpose);
3819 snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL,
3820 chip->ac97_powerdown);
3821 mdelay(10);
3822 snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN,
3823 chip->ac97_powerdown);
3824 mdelay(5);
3825 #endif
3826
3827 snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3828 snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3829
3830
3831
3832
3833 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3834 chip->capt.ctl = tmp & 0x0000ffff;
3835 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3836
3837 mdelay(5);
3838
3839
3840 snd_cs46xx_set_play_sample_rate(chip, 8000);
3841 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3842 snd_cs46xx_proc_start(chip);
3843
3844 cs46xx_enable_stream_irqs(chip);
3845
3846 if (amp_saved)
3847 chip->amplifier_ctrl(chip, 1);
3848 else
3849 chip->active_ctrl(chip, -1);
3850 chip->amplifier = amp_saved;
3851 chip->in_suspend = 0;
3852 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3853 return 0;
3854 }
3855
3856 SIMPLE_DEV_PM_OPS(snd_cs46xx_pm, snd_cs46xx_suspend, snd_cs46xx_resume);
3857 #endif
3858
3859
3860
3861
3862
3863 int snd_cs46xx_create(struct snd_card *card,
3864 struct pci_dev *pci,
3865 int external_amp, int thinkpad,
3866 struct snd_cs46xx **rchip)
3867 {
3868 struct snd_cs46xx *chip;
3869 int err, idx;
3870 struct snd_cs46xx_region *region;
3871 struct cs_card_type *cp;
3872 u16 ss_card, ss_vendor;
3873 static struct snd_device_ops ops = {
3874 .dev_free = snd_cs46xx_dev_free,
3875 };
3876
3877 *rchip = NULL;
3878
3879
3880 if ((err = pci_enable_device(pci)) < 0)
3881 return err;
3882
3883 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3884 if (chip == NULL) {
3885 pci_disable_device(pci);
3886 return -ENOMEM;
3887 }
3888 spin_lock_init(&chip->reg_lock);
3889 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3890 mutex_init(&chip->spos_mutex);
3891 #endif
3892 chip->card = card;
3893 chip->pci = pci;
3894 chip->irq = -1;
3895 chip->ba0_addr = pci_resource_start(pci, 0);
3896 chip->ba1_addr = pci_resource_start(pci, 1);
3897 if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 ||
3898 chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) {
3899 dev_err(chip->card->dev,
3900 "wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n",
3901 chip->ba0_addr, chip->ba1_addr);
3902 snd_cs46xx_free(chip);
3903 return -ENOMEM;
3904 }
3905
3906 region = &chip->region.name.ba0;
3907 strcpy(region->name, "CS46xx_BA0");
3908 region->base = chip->ba0_addr;
3909 region->size = CS46XX_BA0_SIZE;
3910
3911 region = &chip->region.name.data0;
3912 strcpy(region->name, "CS46xx_BA1_data0");
3913 region->base = chip->ba1_addr + BA1_SP_DMEM0;
3914 region->size = CS46XX_BA1_DATA0_SIZE;
3915
3916 region = &chip->region.name.data1;
3917 strcpy(region->name, "CS46xx_BA1_data1");
3918 region->base = chip->ba1_addr + BA1_SP_DMEM1;
3919 region->size = CS46XX_BA1_DATA1_SIZE;
3920
3921 region = &chip->region.name.pmem;
3922 strcpy(region->name, "CS46xx_BA1_pmem");
3923 region->base = chip->ba1_addr + BA1_SP_PMEM;
3924 region->size = CS46XX_BA1_PRG_SIZE;
3925
3926 region = &chip->region.name.reg;
3927 strcpy(region->name, "CS46xx_BA1_reg");
3928 region->base = chip->ba1_addr + BA1_SP_REG;
3929 region->size = CS46XX_BA1_REG_SIZE;
3930
3931
3932 pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor);
3933 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card);
3934
3935 for (cp = &cards[0]; cp->name; cp++) {
3936 if (cp->vendor == ss_vendor && cp->id == ss_card) {
3937 dev_dbg(chip->card->dev, "hack for %s enabled\n",
3938 cp->name);
3939
3940 chip->amplifier_ctrl = cp->amp;
3941 chip->active_ctrl = cp->active;
3942 chip->mixer_init = cp->mixer_init;
3943
3944 if (cp->init)
3945 cp->init(chip);
3946 break;
3947 }
3948 }
3949
3950 if (external_amp) {
3951 dev_info(chip->card->dev,
3952 "Crystal EAPD support forced on.\n");
3953 chip->amplifier_ctrl = amp_voyetra;
3954 }
3955
3956 if (thinkpad) {
3957 dev_info(chip->card->dev,
3958 "Activating CLKRUN hack for Thinkpad.\n");
3959 chip->active_ctrl = clkrun_hack;
3960 clkrun_init(chip);
3961 }
3962
3963 if (chip->amplifier_ctrl == NULL)
3964 chip->amplifier_ctrl = amp_none;
3965 if (chip->active_ctrl == NULL)
3966 chip->active_ctrl = amp_none;
3967
3968 chip->active_ctrl(chip, 1);
3969
3970 pci_set_master(pci);
3971
3972 for (idx = 0; idx < 5; idx++) {
3973 region = &chip->region.idx[idx];
3974 if ((region->resource = request_mem_region(region->base, region->size,
3975 region->name)) == NULL) {
3976 dev_err(chip->card->dev,
3977 "unable to request memory region 0x%lx-0x%lx\n",
3978 region->base, region->base + region->size - 1);
3979 snd_cs46xx_free(chip);
3980 return -EBUSY;
3981 }
3982 region->remap_addr = ioremap_nocache(region->base, region->size);
3983 if (region->remap_addr == NULL) {
3984 dev_err(chip->card->dev,
3985 "%s ioremap problem\n", region->name);
3986 snd_cs46xx_free(chip);
3987 return -ENOMEM;
3988 }
3989 }
3990
3991 if (request_irq(pci->irq, snd_cs46xx_interrupt, IRQF_SHARED,
3992 KBUILD_MODNAME, chip)) {
3993 dev_err(chip->card->dev, "unable to grab IRQ %d\n", pci->irq);
3994 snd_cs46xx_free(chip);
3995 return -EBUSY;
3996 }
3997 chip->irq = pci->irq;
3998
3999 #ifdef CONFIG_SND_CS46XX_NEW_DSP
4000 chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip);
4001 if (chip->dsp_spos_instance == NULL) {
4002 snd_cs46xx_free(chip);
4003 return -ENOMEM;
4004 }
4005 #endif
4006
4007 err = snd_cs46xx_chip_init(chip);
4008 if (err < 0) {
4009 snd_cs46xx_free(chip);
4010 return err;
4011 }
4012
4013 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
4014 snd_cs46xx_free(chip);
4015 return err;
4016 }
4017
4018 snd_cs46xx_proc_init(card, chip);
4019
4020 #ifdef CONFIG_PM_SLEEP
4021 chip->saved_regs = kmalloc_array(ARRAY_SIZE(saved_regs),
4022 sizeof(*chip->saved_regs),
4023 GFP_KERNEL);
4024 if (!chip->saved_regs) {
4025 snd_cs46xx_free(chip);
4026 return -ENOMEM;
4027 }
4028 #endif
4029
4030 chip->active_ctrl(chip, -1);
4031
4032 *rchip = chip;
4033 return 0;
4034 }