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11 #define G2_FIFO 0xa05f688c
12 #define SPU_MEMORY_BASE 0xA0800000
13 #define ARM_RESET_REGISTER 0xA0702C00
14 #define SPU_REGISTER_BASE 0xA0700000
15
16
17 #define AICA_CONTROL_POINT 0xA0810000
18 #define AICA_CONTROL_CHANNEL_SAMPLE_NUMBER 0xA0810008
19 #define AICA_CHANNEL0_CONTROL_OFFSET 0x10004
20
21
22 #define AICA_CMD_KICK 0x80000000
23 #define AICA_CMD_NONE 0
24 #define AICA_CMD_START 1
25 #define AICA_CMD_STOP 2
26 #define AICA_CMD_VOL 3
27
28
29 #define SM_8BIT 1
30 #define SM_16BIT 0
31 #define SM_ADPCM 2
32
33
34 #define AICA_BUFFER_SIZE 0x8000
35 #define AICA_PERIOD_SIZE 0x800
36 #define AICA_PERIOD_NUMBER 16
37
38 #define AICA_CHANNEL0_OFFSET 0x11000
39 #define AICA_CHANNEL1_OFFSET 0x21000
40 #define CHANNEL_OFFSET 0x10000
41
42 #define AICA_DMA_CHANNEL 5
43 #define AICA_DMA_MODE 5
44
45 #define SND_AICA_DRIVER "AICA"
46
47 struct aica_channel {
48 uint32_t cmd;
49 uint32_t pos;
50 uint32_t length;
51 uint32_t freq;
52 uint32_t vol;
53 uint32_t pan;
54 uint32_t sfmt;
55 uint32_t flags;
56 };
57
58 struct snd_card_aica {
59 struct work_struct spu_dma_work;
60 struct snd_card *card;
61 struct aica_channel *channel;
62 struct snd_pcm_substream *substream;
63 int clicks;
64 int current_period;
65 struct timer_list timer;
66 int master_volume;
67 int dma_check;
68 };