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9 #ifndef __AWACS_H
10 #define __AWACS_H
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15
16 struct awacs_regs {
17 unsigned control;
18 unsigned pad0[3];
19 unsigned codec_ctrl;
20 unsigned pad1[3];
21 unsigned codec_stat;
22 unsigned pad2[3];
23 unsigned clip_count;
24 unsigned pad3[3];
25 unsigned byteswap;
26 };
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33
34 #define MASK_ISFSEL (0xf)
35 #define MASK_OSFSEL (0xf << 4)
36 #define MASK_RATE (0x7 << 8)
37 #define MASK_CNTLERR (0x1 << 11)
38 #define MASK_PORTCHG (0x1 << 12)
39 #define MASK_IEE (0x1 << 13)
40 #define MASK_IEPC (0x1 << 14)
41 #define MASK_SSFSEL (0x3 << 15)
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43
44
45 #define MASK_NEWECMD (0x1 << 24)
46 #define MASK_EMODESEL (0x3 << 22)
47 #define MASK_EXMODEADDR (0x3ff << 12)
48 #define MASK_EXMODEDATA (0xfff)
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50
51
52 #define MASK_ADDR0 (0x0 << 12)
53 #define MASK_ADDR_MUX MASK_ADDR0
54 #define MASK_ADDR_GAIN MASK_ADDR0
55
56 #define MASK_ADDR1 (0x1 << 12)
57 #define MASK_ADDR_MUTE MASK_ADDR1
58 #define MASK_ADDR_RATE MASK_ADDR1
59
60 #define MASK_ADDR2 (0x2 << 12)
61 #define MASK_ADDR_VOLA MASK_ADDR2
62 #define MASK_ADDR_VOLHD MASK_ADDR2
63
64 #define MASK_ADDR4 (0x4 << 12)
65 #define MASK_ADDR_VOLC MASK_ADDR4
66 #define MASK_ADDR_VOLSPK MASK_ADDR4
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68
69 #define MASK_ADDR5 (0x5 << 12)
70 #define MASK_ADDR6 (0x6 << 12)
71 #define MASK_ADDR7 (0x7 << 12)
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74
75 #define MASK_GAINRIGHT (0xf)
76 #define MASK_GAINLEFT (0xf << 4)
77 #define MASK_GAINLINE (0x1 << 8)
78 #define MASK_GAINMIC (0x0 << 8)
79 #define MASK_MUX_CD (0x1 << 9)
80 #define MASK_MUX_MIC (0x1 << 10)
81 #define MASK_MUX_AUDIN (0x1 << 11)
82 #define MASK_MUX_LINE MASK_MUX_AUDIN
83 #define SHIFT_GAINLINE 8
84 #define SHIFT_MUX_CD 9
85 #define SHIFT_MUX_MIC 10
86 #define SHIFT_MUX_LINE 11
87
88 #define GAINRIGHT(x) ((x) & MASK_GAINRIGHT)
89 #define GAINLEFT(x) (((x) << 4) & MASK_GAINLEFT)
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92
93 #define MASK_ADDR1RES1 (0x3)
94 #define MASK_RECALIBRATE (0x1 << 2)
95 #define MASK_SAMPLERATE (0x7 << 3)
96 #define MASK_LOOPTHRU (0x1 << 6)
97 #define SHIFT_LOOPTHRU 6
98 #define MASK_CMUTE (0x1 << 7)
99 #define MASK_SPKMUTE MASK_CMUTE
100 #define SHIFT_SPKMUTE 7
101 #define MASK_ADDR1RES2 (0x1 << 8)
102 #define MASK_AMUTE (0x1 << 9)
103 #define MASK_HDMUTE MASK_AMUTE
104 #define SHIFT_HDMUTE 9
105 #define MASK_PAROUT (0x3 << 10)
106 #define MASK_PAROUT0 (0x1 << 10)
107 #define MASK_PAROUT1 (0x1 << 11)
108 #define SHIFT_PAROUT 10
109 #define SHIFT_PAROUT0 10
110 #define SHIFT_PAROUT1 11
111
112 #define SAMPLERATE_48000 (0x0 << 3)
113 #define SAMPLERATE_32000 (0x1 << 3)
114 #define SAMPLERATE_24000 (0x2 << 3)
115 #define SAMPLERATE_19200 (0x3 << 3)
116 #define SAMPLERATE_16000 (0x4 << 3)
117 #define SAMPLERATE_12000 (0x5 << 3)
118 #define SAMPLERATE_9600 (0x6 << 3)
119 #define SAMPLERATE_8000 (0x7 << 3)
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122
123 #define MASK_OUTVOLRIGHT (0xf)
124 #define MASK_ADDR2RES1 (0x2 << 4)
125 #define MASK_ADDR4RES1 MASK_ADDR2RES1
126 #define MASK_OUTVOLLEFT (0xf << 6)
127 #define MASK_ADDR2RES2 (0x2 << 10)
128 #define MASK_ADDR4RES2 MASK_ADDR2RES2
129
130 #define VOLRIGHT(x) (((~(x)) & MASK_OUTVOLRIGHT))
131 #define VOLLEFT(x) (((~(x)) << 6) & MASK_OUTVOLLEFT)
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133
134 #define MASK_MIC_BOOST (0x4)
135 #define SHIFT_MIC_BOOST 2
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138
139 #define MASK_EXTEND (0x1 << 23)
140 #define MASK_VALID (0x1 << 22)
141 #define MASK_OFLEFT (0x1 << 21)
142 #define MASK_OFRIGHT (0x1 << 20)
143 #define MASK_ERRCODE (0xf << 16)
144 #define MASK_REVISION (0xf << 12)
145 #define MASK_MFGID (0xf << 8)
146 #define MASK_CODSTATRES (0xf << 4)
147 #define MASK_INSENSE (0xf)
148 #define MASK_HDPCONN 8
149 #define MASK_LOCONN 4
150 #define MASK_LICONN 2
151 #define MASK_MICCONN 1
152 #define MASK_LICONN_IMAC 8
153 #define MASK_HDPRCONN_IMAC 4
154 #define MASK_HDPLCONN_IMAC 2
155 #define MASK_LOCONN_IMAC 1
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158
159 #define MASK_CLIPLEFT (0xff << 7)
160 #define MASK_CLIPRIGHT (0xff)
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163
164 #define MASK_CSERR (0x1 << 7)
165 #define MASK_EOI (0x1 << 6)
166
167 #define MASK_CSUNUSED (0x1f << 1)
168 #define MASK_WAIT (0x1)
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171
172 #define RATE_48000 (0x0 << 8)
173 #define RATE_44100 (0x0 << 8)
174 #define RATE_32000 (0x1 << 8)
175 #define RATE_29400 (0x1 << 8)
176 #define RATE_24000 (0x2 << 8)
177 #define RATE_22050 (0x2 << 8)
178 #define RATE_19200 (0x3 << 8)
179 #define RATE_17640 (0x3 << 8)
180 #define RATE_16000 (0x4 << 8)
181 #define RATE_14700 (0x4 << 8)
182 #define RATE_12000 (0x5 << 8)
183 #define RATE_11025 (0x5 << 8)
184 #define RATE_9600 (0x6 << 8)
185 #define RATE_8820 (0x6 << 8)
186 #define RATE_8000 (0x7 << 8)
187 #define RATE_7350 (0x7 << 8)
188
189 #define RATE_LOW 1
190
191
192 #endif