1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * (not much of an) Emulation layer for 32bit guests.
4 *
5 * Copyright (C) 2012,2013 - ARM Ltd
6 * Author: Marc Zyngier <marc.zyngier@arm.com>
7 *
8 * based on arch/arm/kvm/emulate.c
9 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
10 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
11 */
12
13 #include <linux/bits.h>
14 #include <linux/kvm_host.h>
15 #include <asm/kvm_emulate.h>
16 #include <asm/kvm_hyp.h>
17
18 #define DFSR_FSC_EXTABT_LPAE 0x10
19 #define DFSR_FSC_EXTABT_nLPAE 0x08
20 #define DFSR_LPAE BIT(9)
21
22 /*
23 * Table taken from ARMv8 ARM DDI0487B-B, table G1-10.
24 */
25 static const u8 return_offsets[8][2] = {
26 [0] = { 0, 0 }, /* Reset, unused */
27 [1] = { 4, 2 }, /* Undefined */
28 [2] = { 0, 0 }, /* SVC, unused */
29 [3] = { 4, 4 }, /* Prefetch abort */
30 [4] = { 8, 8 }, /* Data abort */
31 [5] = { 0, 0 }, /* HVC, unused */
32 [6] = { 4, 4 }, /* IRQ, unused */
33 [7] = { 4, 4 }, /* FIQ, unused */
34 };
35
36 static bool pre_fault_synchronize(struct kvm_vcpu *vcpu)
37 {
38 preempt_disable();
39 if (kvm_arm_vcpu_loaded(vcpu)) {
40 kvm_arch_vcpu_put(vcpu);
41 return true;
42 }
43
44 preempt_enable();
45 return false;
46 }
47
48 static void post_fault_synchronize(struct kvm_vcpu *vcpu, bool loaded)
49 {
50 if (loaded) {
51 kvm_arch_vcpu_load(vcpu, smp_processor_id());
52 preempt_enable();
53 }
54 }
55
56 /*
57 * When an exception is taken, most CPSR fields are left unchanged in the
58 * handler. However, some are explicitly overridden (e.g. M[4:0]).
59 *
60 * The SPSR/SPSR_ELx layouts differ, and the below is intended to work with
61 * either format. Note: SPSR.J bit doesn't exist in SPSR_ELx, but this bit was
62 * obsoleted by the ARMv7 virtualization extensions and is RES0.
63 *
64 * For the SPSR layout seen from AArch32, see:
65 * - ARM DDI 0406C.d, page B1-1148
66 * - ARM DDI 0487E.a, page G8-6264
67 *
68 * For the SPSR_ELx layout for AArch32 seen from AArch64, see:
69 * - ARM DDI 0487E.a, page C5-426
70 *
71 * Here we manipulate the fields in order of the AArch32 SPSR_ELx layout, from
72 * MSB to LSB.
73 */
74 static unsigned long get_except32_cpsr(struct kvm_vcpu *vcpu, u32 mode)
75 {
76 u32 sctlr = vcpu_cp15(vcpu, c1_SCTLR);
77 unsigned long old, new;
78
79 old = *vcpu_cpsr(vcpu);
80 new = 0;
81
82 new |= (old & PSR_AA32_N_BIT);
83 new |= (old & PSR_AA32_Z_BIT);
84 new |= (old & PSR_AA32_C_BIT);
85 new |= (old & PSR_AA32_V_BIT);
86 new |= (old & PSR_AA32_Q_BIT);
87
88 // CPSR.IT[7:0] are set to zero upon any exception
89 // See ARM DDI 0487E.a, section G1.12.3
90 // See ARM DDI 0406C.d, section B1.8.3
91
92 new |= (old & PSR_AA32_DIT_BIT);
93
94 // CPSR.SSBS is set to SCTLR.DSSBS upon any exception
95 // See ARM DDI 0487E.a, page G8-6244
96 if (sctlr & BIT(31))
97 new |= PSR_AA32_SSBS_BIT;
98
99 // CPSR.PAN is unchanged unless SCTLR.SPAN == 0b0
100 // SCTLR.SPAN is RES1 when ARMv8.1-PAN is not implemented
101 // See ARM DDI 0487E.a, page G8-6246
102 new |= (old & PSR_AA32_PAN_BIT);
103 if (!(sctlr & BIT(23)))
104 new |= PSR_AA32_PAN_BIT;
105
106 // SS does not exist in AArch32, so ignore
107
108 // CPSR.IL is set to zero upon any exception
109 // See ARM DDI 0487E.a, page G1-5527
110
111 new |= (old & PSR_AA32_GE_MASK);
112
113 // CPSR.IT[7:0] are set to zero upon any exception
114 // See prior comment above
115
116 // CPSR.E is set to SCTLR.EE upon any exception
117 // See ARM DDI 0487E.a, page G8-6245
118 // See ARM DDI 0406C.d, page B4-1701
119 if (sctlr & BIT(25))
120 new |= PSR_AA32_E_BIT;
121
122 // CPSR.A is unchanged upon an exception to Undefined, Supervisor
123 // CPSR.A is set upon an exception to other modes
124 // See ARM DDI 0487E.a, pages G1-5515 to G1-5516
125 // See ARM DDI 0406C.d, page B1-1182
126 new |= (old & PSR_AA32_A_BIT);
127 if (mode != PSR_AA32_MODE_UND && mode != PSR_AA32_MODE_SVC)
128 new |= PSR_AA32_A_BIT;
129
130 // CPSR.I is set upon any exception
131 // See ARM DDI 0487E.a, pages G1-5515 to G1-5516
132 // See ARM DDI 0406C.d, page B1-1182
133 new |= PSR_AA32_I_BIT;
134
135 // CPSR.F is set upon an exception to FIQ
136 // CPSR.F is unchanged upon an exception to other modes
137 // See ARM DDI 0487E.a, pages G1-5515 to G1-5516
138 // See ARM DDI 0406C.d, page B1-1182
139 new |= (old & PSR_AA32_F_BIT);
140 if (mode == PSR_AA32_MODE_FIQ)
141 new |= PSR_AA32_F_BIT;
142
143 // CPSR.T is set to SCTLR.TE upon any exception
144 // See ARM DDI 0487E.a, page G8-5514
145 // See ARM DDI 0406C.d, page B1-1181
146 if (sctlr & BIT(30))
147 new |= PSR_AA32_T_BIT;
148
149 new |= mode;
150
151 return new;
152 }
153
154 static void prepare_fault32(struct kvm_vcpu *vcpu, u32 mode, u32 vect_offset)
155 {
156 unsigned long spsr = *vcpu_cpsr(vcpu);
157 bool is_thumb = (spsr & PSR_AA32_T_BIT);
158 u32 return_offset = return_offsets[vect_offset >> 2][is_thumb];
159 u32 sctlr = vcpu_cp15(vcpu, c1_SCTLR);
160
161 *vcpu_cpsr(vcpu) = get_except32_cpsr(vcpu, mode);
162
163 /* Note: These now point to the banked copies */
164 vcpu_write_spsr(vcpu, host_spsr_to_spsr32(spsr));
165 *vcpu_reg32(vcpu, 14) = *vcpu_pc(vcpu) + return_offset;
166
167 /* Branch to exception vector */
168 if (sctlr & (1 << 13))
169 vect_offset += 0xffff0000;
170 else /* always have security exceptions */
171 vect_offset += vcpu_cp15(vcpu, c12_VBAR);
172
173 *vcpu_pc(vcpu) = vect_offset;
174 }
175
176 void kvm_inject_undef32(struct kvm_vcpu *vcpu)
177 {
178 bool loaded = pre_fault_synchronize(vcpu);
179
180 prepare_fault32(vcpu, PSR_AA32_MODE_UND, 4);
181 post_fault_synchronize(vcpu, loaded);
182 }
183
184 /*
185 * Modelled after TakeDataAbortException() and TakePrefetchAbortException
186 * pseudocode.
187 */
188 static void inject_abt32(struct kvm_vcpu *vcpu, bool is_pabt,
189 unsigned long addr)
190 {
191 u32 vect_offset;
192 u32 *far, *fsr;
193 bool is_lpae;
194 bool loaded;
195
196 loaded = pre_fault_synchronize(vcpu);
197
198 if (is_pabt) {
199 vect_offset = 12;
200 far = &vcpu_cp15(vcpu, c6_IFAR);
201 fsr = &vcpu_cp15(vcpu, c5_IFSR);
202 } else { /* !iabt */
203 vect_offset = 16;
204 far = &vcpu_cp15(vcpu, c6_DFAR);
205 fsr = &vcpu_cp15(vcpu, c5_DFSR);
206 }
207
208 prepare_fault32(vcpu, PSR_AA32_MODE_ABT, vect_offset);
209
210 *far = addr;
211
212 /* Give the guest an IMPLEMENTATION DEFINED exception */
213 is_lpae = (vcpu_cp15(vcpu, c2_TTBCR) >> 31);
214 if (is_lpae) {
215 *fsr = DFSR_LPAE | DFSR_FSC_EXTABT_LPAE;
216 } else {
217 /* no need to shuffle FS[4] into DFSR[10] as its 0 */
218 *fsr = DFSR_FSC_EXTABT_nLPAE;
219 }
220
221 post_fault_synchronize(vcpu, loaded);
222 }
223
224 void kvm_inject_dabt32(struct kvm_vcpu *vcpu, unsigned long addr)
225 {
226 inject_abt32(vcpu, false, addr);
227 }
228
229 void kvm_inject_pabt32(struct kvm_vcpu *vcpu, unsigned long addr)
230 {
231 inject_abt32(vcpu, true, addr);
232 }