arch/parisc/include/asm/pdcpat.h

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   1 #ifndef __PARISC_PATPDC_H
   2 #define __PARISC_PATPDC_H
   3 
   4 /*
   5  * This file is subject to the terms and conditions of the GNU General Public
   6  * License.  See the file "COPYING" in the main directory of this archive
   7  * for more details.
   8  *
   9  * Copyright 2000 (c) Hewlett Packard (Paul Bame <bame()spam.parisc-linux.org>)
  10  * Copyright 2000,2004 (c) Grant Grundler <grundler()nahspam.parisc-linux.org>
  11  */
  12 
  13 
  14 #define PDC_PAT_CELL            64L   /* Interface for gaining and 
  15                                          * manipulatin g cell state within PD */
  16 #define PDC_PAT_CELL_GET_NUMBER    0L   /* Return Cell number */
  17 #define PDC_PAT_CELL_GET_INFO      1L   /* Returns info about Cell */
  18 #define PDC_PAT_CELL_MODULE        2L   /* Returns info about Module */
  19 #define PDC_PAT_CELL_SET_ATTENTION 9L   /* Set Cell Attention indicator */
  20 #define PDC_PAT_CELL_NUMBER_TO_LOC 10L   /* Cell Number -> Location */
  21 #define PDC_PAT_CELL_WALK_FABRIC   11L   /* Walk the Fabric */
  22 #define PDC_PAT_CELL_GET_RDT_SIZE  12L   /* Return Route Distance Table Sizes */
  23 #define PDC_PAT_CELL_GET_RDT       13L   /* Return Route Distance Tables */
  24 #define PDC_PAT_CELL_GET_LOCAL_PDH_SZ 14L /* Read Local PDH Buffer Size */
  25 #define PDC_PAT_CELL_SET_LOCAL_PDH    15L  /* Write Local PDH Buffer */
  26 #define PDC_PAT_CELL_GET_REMOTE_PDH_SZ 16L /* Return Remote PDH Buffer Size */
  27 #define PDC_PAT_CELL_GET_REMOTE_PDH 17L /* Read Remote PDH Buffer */
  28 #define PDC_PAT_CELL_GET_DBG_INFO   128L  /* Return DBG Buffer Info */
  29 #define PDC_PAT_CELL_CHANGE_ALIAS   129L  /* Change Non-Equivalent Alias Chacking */
  30 
  31 
  32 /*
  33 ** Arg to PDC_PAT_CELL_MODULE memaddr[4]
  34 **
  35 ** Addresses on the Merced Bus != all Runway Bus addresses.
  36 ** This is intended for programming SBA/LBA chips range registers.
  37 */
  38 #define IO_VIEW      0UL
  39 #define PA_VIEW      1UL
  40 
  41 /* PDC_PAT_CELL_MODULE entity type values */
  42 #define PAT_ENTITY_CA   0       /* central agent */
  43 #define PAT_ENTITY_PROC 1       /* processor */
  44 #define PAT_ENTITY_MEM  2       /* memory controller */
  45 #define PAT_ENTITY_SBA  3       /* system bus adapter */
  46 #define PAT_ENTITY_LBA  4       /* local bus adapter */
  47 #define PAT_ENTITY_PBC  5       /* processor bus converter */
  48 #define PAT_ENTITY_XBC  6       /* crossbar fabric connect */
  49 #define PAT_ENTITY_RC   7       /* fabric interconnect */
  50 
  51 /* PDC_PAT_CELL_MODULE address range type values */
  52 #define PAT_PBNUM           0         /* PCI Bus Number */
  53 #define PAT_LMMIO           1         /* < 4G MMIO Space */
  54 #define PAT_GMMIO           2         /* > 4G MMIO Space */
  55 #define PAT_NPIOP           3         /* Non Postable I/O Port Space */
  56 #define PAT_PIOP            4         /* Postable I/O Port Space */
  57 #define PAT_AHPA            5         /* Addional HPA Space */
  58 #define PAT_UFO             6         /* HPA Space (UFO for Mariposa) */
  59 #define PAT_GNIP            7         /* GNI Reserved Space */
  60 
  61 
  62 
  63 /* PDC PAT CHASSIS LOG -- Platform logging & forward progress functions */
  64 
  65 #define PDC_PAT_CHASSIS_LOG             65L
  66 #define PDC_PAT_CHASSIS_WRITE_LOG       0L /* Write Log Entry */
  67 #define PDC_PAT_CHASSIS_READ_LOG        1L /* Read  Log Entry */
  68 
  69 
  70 /* PDC PAT COMPLEX */
  71 
  72 #define PDC_PAT_COMPLEX                 66L
  73 
  74 /* PDC PAT CPU  -- CPU configuration within the protection domain */
  75 
  76 #define PDC_PAT_CPU                     67L
  77 #define PDC_PAT_CPU_INFO                0L /* Return CPU config info */
  78 #define PDC_PAT_CPU_DELETE              1L /* Delete CPU */
  79 #define PDC_PAT_CPU_ADD                 2L /* Add    CPU */
  80 #define PDC_PAT_CPU_GET_NUMBER          3L /* Return CPU Number */
  81 #define PDC_PAT_CPU_GET_HPA             4L /* Return CPU HPA */
  82 #define PDC_PAT_CPU_STOP                5L /* Stop   CPU */
  83 #define PDC_PAT_CPU_RENDEZVOUS          6L /* Rendezvous CPU */
  84 #define PDC_PAT_CPU_GET_CLOCK_INFO      7L /* Return CPU Clock info */
  85 #define PDC_PAT_CPU_GET_RENDEZVOUS_STATE 8L /* Return Rendezvous State */
  86 #define PDC_PAT_CPU_PLUNGE_FABRIC       128L /* Plunge Fabric */
  87 #define PDC_PAT_CPU_UPDATE_CACHE_CLEANSING 129L /* Manipulate Cache 
  88                                                  * Cleansing Mode */
  89 /*  PDC PAT EVENT -- Platform Events */
  90 
  91 #define PDC_PAT_EVENT                   68L
  92 #define PDC_PAT_EVENT_GET_CAPS          0L /* Get Capabilities */
  93 #define PDC_PAT_EVENT_SET_MODE          1L /* Set Notification Mode */
  94 #define PDC_PAT_EVENT_SCAN              2L /* Scan Event */
  95 #define PDC_PAT_EVENT_HANDLE            3L /* Handle Event */
  96 #define PDC_PAT_EVENT_GET_NB_CALL       4L /* Get Non-Blocking call Args */
  97 
  98 /*  PDC PAT HPMC -- Cause processor to go into spin loop, and wait
  99  *                      for wake up from Monarch Processor.
 100  */
 101 
 102 #define PDC_PAT_HPMC               70L
 103 #define PDC_PAT_HPMC_RENDEZ_CPU     0L /* go into spin loop */
 104 #define PDC_PAT_HPMC_SET_PARAMS     1L /* Allows OS to specify intr which PDC 
 105                                         * will use to interrupt OS during
 106                                         * machine check rendezvous */
 107 
 108 /* parameters for PDC_PAT_HPMC_SET_PARAMS: */
 109 #define HPMC_SET_PARAMS_INTR        1L /* Rendezvous Interrupt */
 110 #define HPMC_SET_PARAMS_WAKE        2L /* Wake up processor */
 111 
 112 
 113 /*  PDC PAT IO  -- On-line services for I/O modules */
 114 
 115 #define PDC_PAT_IO                  71L
 116 #define PDC_PAT_IO_GET_SLOT_STATUS      5L /* Get Slot Status Info*/
 117 #define PDC_PAT_IO_GET_LOC_FROM_HARDWARE 6L /* Get Physical Location from */
 118                                             /* Hardware Path */
 119 #define PDC_PAT_IO_GET_HARDWARE_FROM_LOC 7L /* Get Hardware Path from 
 120                                              * Physical Location */
 121 #define PDC_PAT_IO_GET_PCI_CONFIG_FROM_HW 11L /* Get PCI Configuration
 122                                                * Address from Hardware Path */
 123 #define PDC_PAT_IO_GET_HW_FROM_PCI_CONFIG 12L /* Get Hardware Path 
 124                                                * from PCI Configuration Address */
 125 #define PDC_PAT_IO_READ_HOST_BRIDGE_INFO 13L  /* Read Host Bridge State Info */
 126 #define PDC_PAT_IO_CLEAR_HOST_BRIDGE_INFO 14L /* Clear Host Bridge State Info*/
 127 #define PDC_PAT_IO_GET_PCI_ROUTING_TABLE_SIZE 15L /* Get PCI INT Routing Table 
 128                                                    * Size */
 129 #define PDC_PAT_IO_GET_PCI_ROUTING_TABLE  16L /* Get PCI INT Routing Table */
 130 #define PDC_PAT_IO_GET_HINT_TABLE_SIZE  17L /* Get Hint Table Size */
 131 #define PDC_PAT_IO_GET_HINT_TABLE       18L /* Get Hint Table */
 132 #define PDC_PAT_IO_PCI_CONFIG_READ      19L /* PCI Config Read */
 133 #define PDC_PAT_IO_PCI_CONFIG_WRITE     20L /* PCI Config Write */
 134 #define PDC_PAT_IO_GET_NUM_IO_SLOTS     21L /* Get Number of I/O Bay Slots in 
 135                                                   * Cabinet */
 136 #define PDC_PAT_IO_GET_LOC_IO_SLOTS     22L /* Get Physical Location of I/O */
 137                                                      /* Bay Slots in Cabinet */
 138 #define PDC_PAT_IO_BAY_STATUS_INFO      28L /* Get I/O Bay Slot Status Info */
 139 #define PDC_PAT_IO_GET_PROC_VIEW        29L /* Get Processor view of IO address */
 140 #define PDC_PAT_IO_PROG_SBA_DIR_RANGE   30L /* Program directed range */
 141 
 142 
 143 /* PDC PAT MEM  -- Manage memory page deallocation */
 144 
 145 #define PDC_PAT_MEM            72L
 146 #define PDC_PAT_MEM_PD_INFO             0L /* Return PDT info for PD       */
 147 #define PDC_PAT_MEM_PD_CLEAR            1L /* Clear PDT for PD             */
 148 #define PDC_PAT_MEM_PD_READ             2L /* Read PDT entries for PD      */
 149 #define PDC_PAT_MEM_PD_RESET            3L /* Reset clear bit for PD       */
 150 #define PDC_PAT_MEM_CELL_INFO           5L /* Return PDT info For Cell     */
 151 #define PDC_PAT_MEM_CELL_CLEAR          6L /* Clear PDT For Cell           */
 152 #define PDC_PAT_MEM_CELL_READ           7L /* Read PDT entries For Cell    */
 153 #define PDC_PAT_MEM_CELL_RESET          8L /* Reset clear bit For Cell     */
 154 #define PDC_PAT_MEM_SETGM               9L /* Set Good Memory value        */
 155 #define PDC_PAT_MEM_ADD_PAGE            10L /* ADDs a page to the cell      */
 156 #define PDC_PAT_MEM_ADDRESS             11L /* Get Physical Location From   */
 157                                             /* Memory Address               */
 158 #define PDC_PAT_MEM_GET_TXT_SIZE        12L /* Get Formatted Text Size   */
 159 #define PDC_PAT_MEM_GET_PD_TXT          13L /* Get PD Formatted Text     */
 160 #define PDC_PAT_MEM_GET_CELL_TXT        14L /* Get Cell Formatted Text   */
 161 #define PDC_PAT_MEM_RD_STATE_INFO       15L /* Read Mem Module State Info*/
 162 #define PDC_PAT_MEM_CLR_STATE_INFO      16L /*Clear Mem Module State Info*/
 163 #define PDC_PAT_MEM_CLEAN_RANGE         128L /*Clean Mem in specific range*/
 164 #define PDC_PAT_MEM_GET_TBL_SIZE        131L /* Get Memory Table Size     */
 165 #define PDC_PAT_MEM_GET_TBL             132L /* Get Memory Table          */
 166 
 167 
 168 /* PDC PAT NVOLATILE  --  Access Non-Volatile Memory */
 169 
 170 #define PDC_PAT_NVOLATILE       73L
 171 #define PDC_PAT_NVOLATILE_READ          0L /* Read Non-Volatile Memory   */
 172 #define PDC_PAT_NVOLATILE_WRITE         1L /* Write Non-Volatile Memory  */
 173 #define PDC_PAT_NVOLATILE_GET_SIZE      2L /* Return size of NVM         */
 174 #define PDC_PAT_NVOLATILE_VERIFY        3L /* Verify contents of NVM     */
 175 #define PDC_PAT_NVOLATILE_INIT          4L /* Initialize NVM             */
 176 
 177 /* PDC PAT PD */
 178 #define PDC_PAT_PD              74L         /* Protection Domain Info   */
 179 #define PDC_PAT_PD_GET_ADDR_MAP         0L  /* Get Address Map          */
 180 #define PDC_PAT_PD_GET_PDC_INTERF_REV   1L  /* Get PDC Interface Revisions */
 181 
 182 #define PDC_PAT_CAPABILITY_BIT_PDC_SERIALIZE    (1UL << 0)
 183 #define PDC_PAT_CAPABILITY_BIT_PDC_POLLING      (1UL << 1)
 184 #define PDC_PAT_CAPABILITY_BIT_PDC_NBC          (1UL << 2) /* non-blocking calls */
 185 #define PDC_PAT_CAPABILITY_BIT_PDC_UFO          (1UL << 3)
 186 #define PDC_PAT_CAPABILITY_BIT_PDC_IODC_32      (1UL << 4)
 187 #define PDC_PAT_CAPABILITY_BIT_PDC_IODC_64      (1UL << 5)
 188 #define PDC_PAT_CAPABILITY_BIT_PDC_HPMC_RENDEZ  (1UL << 6)
 189 #define PDC_PAT_CAPABILITY_BIT_SIMULTANEOUS_PTLB (1UL << 7)
 190 
 191 /* PDC_PAT_PD_GET_ADDR_MAP entry types */
 192 #define PAT_MEMORY_DESCRIPTOR           1   
 193 
 194 /* PDC_PAT_PD_GET_ADDR_MAP memory types */
 195 #define PAT_MEMTYPE_MEMORY              0
 196 #define PAT_MEMTYPE_FIRMWARE            4
 197 
 198 /* PDC_PAT_PD_GET_ADDR_MAP memory usage */
 199 #define PAT_MEMUSE_GENERAL              0
 200 #define PAT_MEMUSE_GI                   128
 201 #define PAT_MEMUSE_GNI                  129
 202 
 203 /* PDC PAT REGISTER TOC */
 204 #define PDC_PAT_REGISTER_TOC    75L
 205 #define PDC_PAT_TOC_REGISTER_VECTOR     0L /* Register TOC Vector */
 206 #define PDC_PAT_TOC_READ_VECTOR         1L /* Read TOC Vector     */
 207 
 208 /* PDC PAT SYSTEM_INFO */
 209 #define PDC_PAT_SYSTEM_INFO     76L
 210 /* PDC_PAT_SYSTEM_INFO uses the same options as PDC_SYSTEM_INFO function. */
 211 
 212 #ifndef __ASSEMBLY__
 213 #include <linux/types.h>
 214 
 215 #ifdef CONFIG_64BIT
 216 #define is_pdc_pat()    (PDC_TYPE_PAT == pdc_type)
 217 extern int pdc_pat_get_irt_size(unsigned long *num_entries, unsigned long cell_num);
 218 extern int pdc_pat_get_irt(void *r_addr, unsigned long cell_num);
 219 #else   /* ! CONFIG_64BIT */
 220 /* No PAT support for 32-bit kernels...sorry */
 221 #define is_pdc_pat()    (0)
 222 #define pdc_pat_get_irt_size(num_entries, cell_numn)    PDC_BAD_PROC
 223 #define pdc_pat_get_irt(r_addr, cell_num)               PDC_BAD_PROC
 224 #endif  /* ! CONFIG_64BIT */
 225 
 226 
 227 struct pdc_pat_cell_num {
 228         unsigned long cell_num;
 229         unsigned long cell_loc;
 230 };
 231 
 232 struct pdc_pat_cpu_num {
 233         unsigned long cpu_num;
 234         unsigned long cpu_loc;
 235 };
 236 
 237 struct pdc_pat_mem_retinfo { /* PDC_PAT_MEM/PDC_PAT_MEM_PD_INFO (return info) */
 238         unsigned int ke;        /* bit 0: memory inside good memory? */
 239         unsigned int current_pdt_entries:16;
 240         unsigned int max_pdt_entries:16;
 241         unsigned long Cs_bitmap;
 242         unsigned long Ic_bitmap;
 243         unsigned long good_mem;
 244         unsigned long first_dbe_loc; /* first location of double bit error */
 245         unsigned long clear_time; /* last PDT clear time (since Jan 1970) */
 246 };
 247 
 248 struct pdc_pat_mem_cell_pdt_retinfo { /* PDC_PAT_MEM/PDC_PAT_MEM_CELL_INFO */
 249         u64 reserved:32;
 250         u64 cs:1;               /* clear status: cleared since the last call? */
 251         u64 current_pdt_entries:15;
 252         u64 ic:1;               /* interleaving had to be changed ? */
 253         u64 max_pdt_entries:15;
 254         unsigned long good_mem;
 255         unsigned long first_dbe_loc; /* first location of double bit error */
 256         unsigned long clear_time; /* last PDT clear time (since Jan 1970) */
 257 };
 258 
 259 
 260 struct pdc_pat_mem_read_pd_retinfo { /* PDC_PAT_MEM/PDC_PAT_MEM_PD_READ */
 261         unsigned long actual_count_bytes;
 262         unsigned long pdt_entries;
 263 };
 264 
 265 struct pdc_pat_mem_phys_mem_location { /* PDC_PAT_MEM/PDC_PAT_MEM_ADDRESS */
 266         u64 cabinet:8;
 267         u64 ign1:8;
 268         u64 ign2:8;
 269         u64 cell_slot:8;
 270         u64 ign3:8;
 271         u64 dimm_slot:8; /* DIMM slot, e.g. 0x1A, 0x2B, show user hex value! */
 272         u64 ign4:8;
 273         u64 source:4; /* for mem: always 0x07 */
 274         u64 source_detail:4; /* for mem: always 0x04 (SIMM or DIMM) */
 275 };
 276 
 277 struct pdc_pat_pd_addr_map_entry {
 278         unsigned char entry_type;       /* 1 = Memory Descriptor Entry Type */
 279         unsigned char reserve1[5];
 280         unsigned char memory_type;
 281         unsigned char memory_usage;
 282         unsigned long paddr;
 283         unsigned int  pages;            /* Length in 4K pages */
 284         unsigned int  reserve2;
 285         unsigned long cell_map;
 286 };
 287 
 288 /********************************************************************
 289 * PDC_PAT_CELL[Return Cell Module] memaddr[0] conf_base_addr
 290 * ----------------------------------------------------------
 291 * Bit  0 to 51 - conf_base_addr
 292 * Bit 52 to 62 - reserved
 293 * Bit       63 - endianess bit
 294 ********************************************************************/
 295 #define PAT_GET_CBA(value) ((value) & 0xfffffffffffff000UL)
 296 
 297 /********************************************************************
 298 * PDC_PAT_CELL[Return Cell Module] memaddr[1] mod_info
 299 * ----------------------------------------------------
 300 * Bit  0 to  7 - entity type
 301 *    0 = central agent,            1 = processor,
 302 *    2 = memory controller,        3 = system bus adapter,
 303 *    4 = local bus adapter,        5 = processor bus converter,
 304 *    6 = crossbar fabric connect,  7 = fabric interconnect,
 305 *    8 to 254 reserved,            255 = unknown.
 306 * Bit  8 to 15 - DVI
 307 * Bit 16 to 23 - IOC functions
 308 * Bit 24 to 39 - reserved
 309 * Bit 40 to 63 - mod_pages
 310 *    number of 4K pages a module occupies starting at conf_base_addr
 311 ********************************************************************/
 312 #define PAT_GET_ENTITY(value)   (((value) >> 56) & 0xffUL)
 313 #define PAT_GET_DVI(value)      (((value) >> 48) & 0xffUL)
 314 #define PAT_GET_IOC(value)      (((value) >> 40) & 0xffUL)
 315 #define PAT_GET_MOD_PAGES(value) ((value) & 0xffffffUL)
 316 
 317 
 318 /*
 319 ** PDC_PAT_CELL_GET_INFO return block
 320 */
 321 typedef struct pdc_pat_cell_info_rtn_block {
 322         unsigned long pdc_rev;
 323         unsigned long capabilities; /* see PDC_PAT_CAPABILITY_BIT_* */
 324         unsigned long reserved0[2];
 325         unsigned long cell_info;        /* 0x20 */
 326         unsigned long cell_phys_location;
 327         unsigned long cpu_info;
 328         unsigned long cpu_speed;
 329         unsigned long io_chassis_phys_location;
 330         unsigned long cell_io_information;
 331         unsigned long reserved1[2];
 332         unsigned long io_slot_info_size; /* 0x60 */
 333         struct {
 334                 unsigned long header, info0, info1;
 335                 unsigned long phys_loc, hw_path;
 336         } io_slot[16];
 337         unsigned long cell_mem_size;    /* 0x2e8 */
 338         unsigned long cell_dimm_info_size;
 339         unsigned long dimm_info[16];
 340         unsigned long fabric_info_size; /* 0x3f8 */
 341         struct {                        /* 0x380 */
 342                 unsigned long fabric_info_xbc_port;
 343                 unsigned long rc_attached_to_xbc;
 344         } xbc[8*4];
 345 } pdc_pat_cell_info_rtn_block_t;
 346 
 347 
 348 /* FIXME: mod[508] should really be a union of the various mod components */
 349 struct pdc_pat_cell_mod_maddr_block {   /* PDC_PAT_CELL_MODULE */
 350         unsigned long cba;              /* func 0 cfg space address */
 351         unsigned long mod_info;         /* module information */
 352         unsigned long mod_location;     /* physical location of the module */
 353         struct hardware_path mod_path;  /* module path (device path - layers) */
 354         unsigned long mod[508];         /* PAT cell module components */
 355 } __attribute__((aligned(8))) ;
 356 
 357 typedef struct pdc_pat_cell_mod_maddr_block pdc_pat_cell_mod_maddr_block_t;
 358 
 359 
 360 extern int pdc_pat_chassis_send_log(unsigned long status, unsigned long data);
 361 extern int pdc_pat_cell_get_number(struct pdc_pat_cell_num *cell_info);
 362 extern int pdc_pat_cell_info(struct pdc_pat_cell_info_rtn_block *info,
 363                 unsigned long *actcnt, unsigned long offset,
 364                 unsigned long cell_number);
 365 extern int pdc_pat_cell_module(unsigned long *actcnt, unsigned long ploc,
 366                 unsigned long mod, unsigned long view_type, void *mem_addr);
 367 extern int pdc_pat_cell_num_to_loc(void *, unsigned long);
 368 
 369 extern int pdc_pat_cpu_get_number(struct pdc_pat_cpu_num *cpu_info, unsigned long hpa);
 370 
 371 extern int pdc_pat_pd_get_addr_map(unsigned long *actual_len, void *mem_addr,
 372                 unsigned long count, unsigned long offset);
 373 extern int pdc_pat_pd_get_pdc_revisions(unsigned long *legacy_rev,
 374                 unsigned long *pat_rev, unsigned long *pdc_cap);
 375 
 376 extern int pdc_pat_io_pci_cfg_read(unsigned long pci_addr, int pci_size, u32 *val); 
 377 extern int pdc_pat_io_pci_cfg_write(unsigned long pci_addr, int pci_size, u32 val); 
 378 
 379 extern int pdc_pat_mem_pdt_info(struct pdc_pat_mem_retinfo *rinfo);
 380 extern int pdc_pat_mem_pdt_cell_info(struct pdc_pat_mem_cell_pdt_retinfo *rinfo,
 381                 unsigned long cell);
 382 extern int pdc_pat_mem_read_cell_pdt(struct pdc_pat_mem_read_pd_retinfo *pret,
 383                 unsigned long *pdt_entries_ptr, unsigned long max_entries);
 384 extern int pdc_pat_mem_read_pd_pdt(struct pdc_pat_mem_read_pd_retinfo *pret,
 385                 unsigned long *pdt_entries_ptr, unsigned long count,
 386                 unsigned long offset);
 387 extern int pdc_pat_mem_get_dimm_phys_location(
 388                 struct pdc_pat_mem_phys_mem_location *pret,
 389                 unsigned long phys_addr);
 390 
 391 #endif /* __ASSEMBLY__ */
 392 
 393 #endif /* ! __PARISC_PATPDC_H */
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root/arch/parisc/include/asm/pdcpat.h

INCLUDED FROM
