1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _PARISC_DMA_MAPPING_H
3 #define _PARISC_DMA_MAPPING_H
4
5 /*
6 ** We need to support 4 different coherent dma models with one binary:
7 **
8 ** I/O MMU consistent method dma_sync behavior
9 ** ============= ====================== =======================
10 ** a) PA-7x00LC uncachable host memory flush/purge
11 ** b) U2/Uturn cachable host memory NOP
12 ** c) Ike/Astro cachable host memory NOP
13 ** d) EPIC/SAGA memory on EPIC/SAGA flush/reset DMA channel
14 **
15 ** PA-7[13]00LC processors have a GSC bus interface and no I/O MMU.
16 **
17 ** Systems (eg PCX-T workstations) that don't fall into the above
18 ** categories will need to modify the needed drivers to perform
19 ** flush/purge and allocate "regular" cacheable pages for everything.
20 */
21
22 extern const struct dma_map_ops *hppa_dma_ops;
23
24 static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
25 {
26 return hppa_dma_ops;
27 }
28
29 #endif