This source file includes following definitions.
- PCI_PORT_OUT
- pcibios_fixup_bus
- pcibios_set_master
- pcibios_init_bridge
- pcibios_align_resource
- pcibios_enable_device
- pcibios_register_hba
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11 #include <linux/eisa.h>
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/types.h>
17
18 #include <asm/io.h>
19 #include <asm/superio.h>
20
21 #define DEBUG_RESOURCES 0
22 #define DEBUG_CONFIG 0
23
24 #if DEBUG_CONFIG
25 # define DBGC(x...) printk(KERN_DEBUG x)
26 #else
27 # define DBGC(x...)
28 #endif
29
30
31 #if DEBUG_RESOURCES
32 #define DBG_RES(x...) printk(KERN_DEBUG x)
33 #else
34 #define DBG_RES(x...)
35 #endif
36
37 struct pci_port_ops *pci_port __ro_after_init;
38 struct pci_bios_ops *pci_bios __ro_after_init;
39
40 static int pci_hba_count __ro_after_init;
41
42
43 #define PCI_HBA_MAX 32
44 static struct pci_hba_data *parisc_pci_hba[PCI_HBA_MAX] __ro_after_init;
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60 #ifdef CONFIG_EISA
61 #define EISA_IN(size) if (EISA_bus && (b == 0)) return eisa_in##size(addr)
62 #define EISA_OUT(size) if (EISA_bus && (b == 0)) return eisa_out##size(d, addr)
63 #else
64 #define EISA_IN(size)
65 #define EISA_OUT(size)
66 #endif
67
68 #define PCI_PORT_IN(type, size) \
69 u##size in##type (int addr) \
70 { \
71 int b = PCI_PORT_HBA(addr); \
72 EISA_IN(size); \
73 if (!parisc_pci_hba[b]) return (u##size) -1; \
74 return pci_port->in##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr)); \
75 } \
76 EXPORT_SYMBOL(in##type);
77
78 PCI_PORT_IN(b, 8)
79 PCI_PORT_IN(w, 16)
80 PCI_PORT_IN(l, 32)
81
82
83 #define PCI_PORT_OUT(type, size) \
84 void out##type (u##size d, int addr) \
85 { \
86 int b = PCI_PORT_HBA(addr); \
87 EISA_OUT(size); \
88 if (!parisc_pci_hba[b]) return; \
89 pci_port->out##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr), d); \
90 } \
91 EXPORT_SYMBOL(out##type);
92
93 PCI_PORT_OUT(b, 8)
94 PCI_PORT_OUT(w, 16)
95 PCI_PORT_OUT(l, 32)
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101
102 static int __init pcibios_init(void)
103 {
104 if (!pci_bios)
105 return -1;
106
107 if (pci_bios->init) {
108 pci_bios->init();
109 } else {
110 printk(KERN_WARNING "pci_bios != NULL but init() is!\n");
111 }
112
113
114 pci_cache_line_size = pci_dfl_cache_line_size;
115
116 return 0;
117 }
118
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120
121 void pcibios_fixup_bus(struct pci_bus *bus)
122 {
123 if (pci_bios->fixup_bus) {
124 pci_bios->fixup_bus(bus);
125 } else {
126 printk(KERN_WARNING "pci_bios != NULL but fixup_bus() is!\n");
127 }
128 }
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146 void pcibios_set_master(struct pci_dev *dev)
147 {
148 u8 lat;
149
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151 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
152 if (lat >= 16) return;
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158 pci_write_config_word(dev, PCI_CACHE_LINE_SIZE,
159 (0x80 << 8) | pci_cache_line_size);
160 }
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166 void __ref pcibios_init_bridge(struct pci_dev *dev)
167 {
168 unsigned short bridge_ctl, bridge_ctl_new;
169
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171 if (!dev || (dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
172 return;
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177 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 32);
178
179 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bridge_ctl);
180
181 bridge_ctl_new = bridge_ctl | PCI_BRIDGE_CTL_PARITY |
182 PCI_BRIDGE_CTL_SERR | PCI_BRIDGE_CTL_MASTER_ABORT;
183 dev_info(&dev->dev, "Changing bridge control from 0x%08x to 0x%08x\n",
184 bridge_ctl, bridge_ctl_new);
185
186 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bridge_ctl_new);
187 }
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198 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
199 resource_size_t size, resource_size_t alignment)
200 {
201 resource_size_t mask, align, start = res->start;
202
203 DBG_RES("pcibios_align_resource(%s, (%p) [%lx,%lx]/%x, 0x%lx, 0x%lx)\n",
204 pci_name(((struct pci_dev *) data)),
205 res->parent, res->start, res->end,
206 (int) res->flags, size, alignment);
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209 align = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
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212 mask = max(alignment, align) - 1;
213 start += mask;
214 start &= ~mask;
215
216 return start;
217 }
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227 int pcibios_enable_device(struct pci_dev *dev, int mask)
228 {
229 int err;
230 u16 cmd, old_cmd;
231
232 err = pci_enable_resources(dev, mask);
233 if (err < 0)
234 return err;
235
236 pci_read_config_word(dev, PCI_COMMAND, &cmd);
237 old_cmd = cmd;
238
239 cmd |= (PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
240
241 #if 0
242
243 if (dev->bus->bridge_ctl & PCI_BRIDGE_CTL_FAST_BACK)
244 cmd |= PCI_COMMAND_FAST_BACK;
245 #endif
246
247 if (cmd != old_cmd) {
248 dev_info(&dev->dev, "enabling SERR and PARITY (%04x -> %04x)\n",
249 old_cmd, cmd);
250 pci_write_config_word(dev, PCI_COMMAND, cmd);
251 }
252 return 0;
253 }
254
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256
257 void pcibios_register_hba(struct pci_hba_data *hba)
258 {
259 if (pci_hba_count >= PCI_HBA_MAX) {
260 printk(KERN_ERR "PCI: Too many Host Bus Adapters\n");
261 return;
262 }
263
264 parisc_pci_hba[pci_hba_count] = hba;
265 hba->hba_num = pci_hba_count++;
266 }
267
268 subsys_initcall(pcibios_init);