1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * First-level interrupt controller model for Hexagon.
4 *
5 * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
6 */
7
8 #include <linux/interrupt.h>
9 #include <asm/irq.h>
10 #include <asm/hexagon_vm.h>
11
12 static void mask_irq(struct irq_data *data)
13 {
14 __vmintop_locdis((long) data->irq);
15 }
16
17 static void mask_irq_num(unsigned int irq)
18 {
19 __vmintop_locdis((long) irq);
20 }
21
22 static void unmask_irq(struct irq_data *data)
23 {
24 __vmintop_locen((long) data->irq);
25 }
26
27 /* This is actually all we need for handle_fasteoi_irq */
28 static void eoi_irq(struct irq_data *data)
29 {
30 __vmintop_globen((long) data->irq);
31 }
32
33 /* Power mamangement wake call. We don't need this, however,
34 * if this is absent, then an -ENXIO error is returned to the
35 * msm_serial driver, and it fails to correctly initialize.
36 * This is a bug in the msm_serial driver, but, for now, we
37 * work around it here, by providing this bogus handler.
38 * XXX FIXME!!! remove this when msm_serial is fixed.
39 */
40 static int set_wake(struct irq_data *data, unsigned int on)
41 {
42 return 0;
43 }
44
45 static struct irq_chip hexagon_irq_chip = {
46 .name = "HEXAGON",
47 .irq_mask = mask_irq,
48 .irq_unmask = unmask_irq,
49 .irq_set_wake = set_wake,
50 .irq_eoi = eoi_irq
51 };
52
53 /**
54 * The hexagon core comes with a first-level interrupt controller
55 * with 32 total possible interrupts. When the core is embedded
56 * into different systems/platforms, it is typically wrapped by
57 * macro cells that provide one or more second-level interrupt
58 * controllers that are cascaded into one or more of the first-level
59 * interrupts handled here. The precise wiring of these other
60 * irqs varies from platform to platform, and are set up & configured
61 * in the platform-specific files.
62 *
63 * The first-level interrupt controller is wrapped by the VM, which
64 * virtualizes the interrupt controller for us. It provides a very
65 * simple, fast & efficient API, and so the fasteoi handler is
66 * appropriate for this case.
67 */
68 void __init init_IRQ(void)
69 {
70 int irq;
71
72 for (irq = 0; irq < HEXAGON_CPUINTS; irq++) {
73 mask_irq_num(irq);
74 irq_set_chip_and_handler(irq, &hexagon_irq_chip,
75 handle_fasteoi_irq);
76 }
77 }