root/arch/arm/mm/tlb-v4wbi.S

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  *  linux/arch/arm/mm/tlbv4wbi.S
   4  *
   5  *  Copyright (C) 1997-2002 Russell King
   6  *
   7  *  ARM architecture version 4 and version 5 TLB handling functions.
   8  *  These assume a split I/D TLBs, with a write buffer.
   9  *
  10  *  Processors: ARM920 ARM922 ARM925 ARM926 XScale
  11  */
  12 #include <linux/linkage.h>
  13 #include <linux/init.h>
  14 #include <asm/assembler.h>
  15 #include <asm/asm-offsets.h>
  16 #include <asm/tlbflush.h>
  17 #include "proc-macros.S"
  18 
  19 /*
  20  *      v4wb_flush_user_tlb_range(start, end, mm)
  21  *
  22  *      Invalidate a range of TLB entries in the specified address space.
  23  *
  24  *      - start - range start address
  25  *      - end   - range end address
  26  *      - mm    - mm_struct describing address space
  27  */
  28         .align  5
  29 ENTRY(v4wbi_flush_user_tlb_range)
  30         vma_vm_mm ip, r2
  31         act_mm  r3                              @ get current->active_mm
  32         eors    r3, ip, r3                      @ == mm ?
  33         retne   lr                              @ no, we dont do anything
  34         mov     r3, #0
  35         mcr     p15, 0, r3, c7, c10, 4          @ drain WB
  36         vma_vm_flags r2, r2
  37         bic     r0, r0, #0x0ff
  38         bic     r0, r0, #0xf00
  39 1:      tst     r2, #VM_EXEC
  40         mcrne   p15, 0, r0, c8, c5, 1           @ invalidate I TLB entry
  41         mcr     p15, 0, r0, c8, c6, 1           @ invalidate D TLB entry
  42         add     r0, r0, #PAGE_SZ
  43         cmp     r0, r1
  44         blo     1b
  45         ret     lr
  46 
  47 ENTRY(v4wbi_flush_kern_tlb_range)
  48         mov     r3, #0
  49         mcr     p15, 0, r3, c7, c10, 4          @ drain WB
  50         bic     r0, r0, #0x0ff
  51         bic     r0, r0, #0xf00
  52 1:      mcr     p15, 0, r0, c8, c5, 1           @ invalidate I TLB entry
  53         mcr     p15, 0, r0, c8, c6, 1           @ invalidate D TLB entry
  54         add     r0, r0, #PAGE_SZ
  55         cmp     r0, r1
  56         blo     1b
  57         ret     lr
  58 
  59         __INITDATA
  60 
  61         /* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
  62         define_tlb_functions v4wbi, v4wbi_tlb_flags