root/arch/arm/mm/tlb-v4wb.S

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  *  linux/arch/arm/mm/tlbv4wb.S
   4  *
   5  *  Copyright (C) 1997-2002 Russell King
   6  *
   7  *  ARM architecture version 4 TLB handling functions.
   8  *  These assume a split I/D TLBs w/o I TLB entry, with a write buffer.
   9  *
  10  *  Processors: SA110 SA1100 SA1110
  11  */
  12 #include <linux/linkage.h>
  13 #include <linux/init.h>
  14 #include <asm/assembler.h>
  15 #include <asm/asm-offsets.h>
  16 #include <asm/tlbflush.h>
  17 #include "proc-macros.S"
  18 
  19         .align  5
  20 /*
  21  *      v4wb_flush_user_tlb_range(start, end, mm)
  22  *
  23  *      Invalidate a range of TLB entries in the specified address space.
  24  *
  25  *      - start - range start address
  26  *      - end   - range end address
  27  *      - mm    - mm_struct describing address space
  28  */
  29         .align  5
  30 ENTRY(v4wb_flush_user_tlb_range)
  31         vma_vm_mm ip, r2
  32         act_mm  r3                              @ get current->active_mm
  33         eors    r3, ip, r3                              @ == mm ?
  34         retne   lr                              @ no, we dont do anything
  35         vma_vm_flags r2, r2
  36         mcr     p15, 0, r3, c7, c10, 4          @ drain WB
  37         tst     r2, #VM_EXEC
  38         mcrne   p15, 0, r3, c8, c5, 0           @ invalidate I TLB
  39         bic     r0, r0, #0x0ff
  40         bic     r0, r0, #0xf00
  41 1:      mcr     p15, 0, r0, c8, c6, 1           @ invalidate D TLB entry
  42         add     r0, r0, #PAGE_SZ
  43         cmp     r0, r1
  44         blo     1b
  45         ret     lr
  46 
  47 /*
  48  *      v4_flush_kern_tlb_range(start, end)
  49  *
  50  *      Invalidate a range of TLB entries in the specified kernel
  51  *      address range.
  52  *
  53  *      - start - virtual address (may not be aligned)
  54  *      - end   - virtual address (may not be aligned)
  55  */
  56 ENTRY(v4wb_flush_kern_tlb_range)
  57         mov     r3, #0
  58         mcr     p15, 0, r3, c7, c10, 4          @ drain WB
  59         bic     r0, r0, #0x0ff
  60         bic     r0, r0, #0xf00
  61         mcr     p15, 0, r3, c8, c5, 0           @ invalidate I TLB
  62 1:      mcr     p15, 0, r0, c8, c6, 1           @ invalidate D TLB entry
  63         add     r0, r0, #PAGE_SZ
  64         cmp     r0, r1
  65         blo     1b
  66         ret     lr
  67 
  68         __INITDATA
  69 
  70         /* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
  71         define_tlb_functions v4wb, v4wb_tlb_flags