root/arch/arm/mm/proc-arm1020e.S

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   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  *  linux/arch/arm/mm/proc-arm1020e.S: MMU functions for ARM1020
   4  *
   5  *  Copyright (C) 2000 ARM Limited
   6  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
   7  *  hacked for non-paged-MM by Hyok S. Choi, 2003.
   8  *
   9  * These are the low level assembler for performing cache and TLB
  10  * functions on the arm1020e.
  11  */
  12 #include <linux/linkage.h>
  13 #include <linux/init.h>
  14 #include <asm/assembler.h>
  15 #include <asm/asm-offsets.h>
  16 #include <asm/hwcap.h>
  17 #include <asm/pgtable-hwdef.h>
  18 #include <asm/pgtable.h>
  19 #include <asm/ptrace.h>
  20 
  21 #include "proc-macros.S"
  22 
  23 /*
  24  * This is the maximum size of an area which will be invalidated
  25  * using the single invalidate entry instructions.  Anything larger
  26  * than this, and we go for the whole cache.
  27  *
  28  * This value should be chosen such that we choose the cheapest
  29  * alternative.
  30  */
  31 #define MAX_AREA_SIZE   32768
  32 
  33 /*
  34  * The size of one data cache line.
  35  */
  36 #define CACHE_DLINESIZE 32
  37 
  38 /*
  39  * The number of data cache segments.
  40  */
  41 #define CACHE_DSEGMENTS 16
  42 
  43 /*
  44  * The number of lines in a cache segment.
  45  */
  46 #define CACHE_DENTRIES  64
  47 
  48 /*
  49  * This is the size at which it becomes more efficient to
  50  * clean the whole cache, rather than using the individual
  51  * cache line maintenance instructions.
  52  */
  53 #define CACHE_DLIMIT    32768
  54 
  55         .text
  56 /*
  57  * cpu_arm1020e_proc_init()
  58  */
  59 ENTRY(cpu_arm1020e_proc_init)
  60         ret     lr
  61 
  62 /*
  63  * cpu_arm1020e_proc_fin()
  64  */
  65 ENTRY(cpu_arm1020e_proc_fin)
  66         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
  67         bic     r0, r0, #0x1000                 @ ...i............
  68         bic     r0, r0, #0x000e                 @ ............wca.
  69         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
  70         ret     lr
  71 
  72 /*
  73  * cpu_arm1020e_reset(loc)
  74  *
  75  * Perform a soft reset of the system.  Put the CPU into the
  76  * same state as it would be if it had been reset, and branch
  77  * to what would be the reset vector.
  78  *
  79  * loc: location to jump to for soft reset
  80  */
  81         .align  5
  82         .pushsection    .idmap.text, "ax"
  83 ENTRY(cpu_arm1020e_reset)
  84         mov     ip, #0
  85         mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
  86         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
  87 #ifdef CONFIG_MMU
  88         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
  89 #endif
  90         mrc     p15, 0, ip, c1, c0, 0           @ ctrl register
  91         bic     ip, ip, #0x000f                 @ ............wcam
  92         bic     ip, ip, #0x1100                 @ ...i...s........
  93         mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
  94         ret     r0
  95 ENDPROC(cpu_arm1020e_reset)
  96         .popsection
  97 
  98 /*
  99  * cpu_arm1020e_do_idle()
 100  */
 101         .align  5
 102 ENTRY(cpu_arm1020e_do_idle)
 103         mcr     p15, 0, r0, c7, c0, 4           @ Wait for interrupt
 104         ret     lr
 105 
 106 /* ================================= CACHE ================================ */
 107 
 108         .align  5
 109 
 110 /*
 111  *      flush_icache_all()
 112  *
 113  *      Unconditionally clean and invalidate the entire icache.
 114  */
 115 ENTRY(arm1020e_flush_icache_all)
 116 #ifndef CONFIG_CPU_ICACHE_DISABLE
 117         mov     r0, #0
 118         mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
 119 #endif
 120         ret     lr
 121 ENDPROC(arm1020e_flush_icache_all)
 122 
 123 /*
 124  *      flush_user_cache_all()
 125  *
 126  *      Invalidate all cache entries in a particular address
 127  *      space.
 128  */
 129 ENTRY(arm1020e_flush_user_cache_all)
 130         /* FALLTHROUGH */
 131 /*
 132  *      flush_kern_cache_all()
 133  *
 134  *      Clean and invalidate the entire cache.
 135  */
 136 ENTRY(arm1020e_flush_kern_cache_all)
 137         mov     r2, #VM_EXEC
 138         mov     ip, #0
 139 __flush_whole_cache:
 140 #ifndef CONFIG_CPU_DCACHE_DISABLE
 141         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 142         mov     r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
 143 1:      orr     r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
 144 2:      mcr     p15, 0, r3, c7, c14, 2          @ clean+invalidate D index
 145         subs    r3, r3, #1 << 26
 146         bcs     2b                              @ entries 63 to 0
 147         subs    r1, r1, #1 << 5
 148         bcs     1b                              @ segments 15 to 0
 149 #endif
 150         tst     r2, #VM_EXEC
 151 #ifndef CONFIG_CPU_ICACHE_DISABLE
 152         mcrne   p15, 0, ip, c7, c5, 0           @ invalidate I cache
 153 #endif
 154         mcrne   p15, 0, ip, c7, c10, 4          @ drain WB
 155         ret     lr
 156 
 157 /*
 158  *      flush_user_cache_range(start, end, flags)
 159  *
 160  *      Invalidate a range of cache entries in the specified
 161  *      address space.
 162  *
 163  *      - start - start address (inclusive)
 164  *      - end   - end address (exclusive)
 165  *      - flags - vm_flags for this space
 166  */
 167 ENTRY(arm1020e_flush_user_cache_range)
 168         mov     ip, #0
 169         sub     r3, r1, r0                      @ calculate total size
 170         cmp     r3, #CACHE_DLIMIT
 171         bhs     __flush_whole_cache
 172 
 173 #ifndef CONFIG_CPU_DCACHE_DISABLE
 174 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
 175         add     r0, r0, #CACHE_DLINESIZE
 176         cmp     r0, r1
 177         blo     1b
 178 #endif
 179         tst     r2, #VM_EXEC
 180 #ifndef CONFIG_CPU_ICACHE_DISABLE
 181         mcrne   p15, 0, ip, c7, c5, 0           @ invalidate I cache
 182 #endif
 183         mcrne   p15, 0, ip, c7, c10, 4          @ drain WB
 184         ret     lr
 185 
 186 /*
 187  *      coherent_kern_range(start, end)
 188  *
 189  *      Ensure coherency between the Icache and the Dcache in the
 190  *      region described by start.  If you have non-snooping
 191  *      Harvard caches, you need to implement this function.
 192  *
 193  *      - start - virtual start address
 194  *      - end   - virtual end address
 195  */
 196 ENTRY(arm1020e_coherent_kern_range)
 197         /* FALLTHROUGH */
 198 /*
 199  *      coherent_user_range(start, end)
 200  *
 201  *      Ensure coherency between the Icache and the Dcache in the
 202  *      region described by start.  If you have non-snooping
 203  *      Harvard caches, you need to implement this function.
 204  *
 205  *      - start - virtual start address
 206  *      - end   - virtual end address
 207  */
 208 ENTRY(arm1020e_coherent_user_range)
 209         mov     ip, #0
 210         bic     r0, r0, #CACHE_DLINESIZE - 1
 211 1:
 212 #ifndef CONFIG_CPU_DCACHE_DISABLE
 213         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 214 #endif
 215 #ifndef CONFIG_CPU_ICACHE_DISABLE
 216         mcr     p15, 0, r0, c7, c5, 1           @ invalidate I entry
 217 #endif
 218         add     r0, r0, #CACHE_DLINESIZE
 219         cmp     r0, r1
 220         blo     1b
 221         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 222         mov     r0, #0
 223         ret     lr
 224 
 225 /*
 226  *      flush_kern_dcache_area(void *addr, size_t size)
 227  *
 228  *      Ensure no D cache aliasing occurs, either with itself or
 229  *      the I cache
 230  *
 231  *      - addr  - kernel address
 232  *      - size  - region size
 233  */
 234 ENTRY(arm1020e_flush_kern_dcache_area)
 235         mov     ip, #0
 236 #ifndef CONFIG_CPU_DCACHE_DISABLE
 237         add     r1, r0, r1
 238 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
 239         add     r0, r0, #CACHE_DLINESIZE
 240         cmp     r0, r1
 241         blo     1b
 242 #endif
 243         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 244         ret     lr
 245 
 246 /*
 247  *      dma_inv_range(start, end)
 248  *
 249  *      Invalidate (discard) the specified virtual address range.
 250  *      May not write back any entries.  If 'start' or 'end'
 251  *      are not cache line aligned, those lines must be written
 252  *      back.
 253  *
 254  *      - start - virtual start address
 255  *      - end   - virtual end address
 256  *
 257  * (same as v4wb)
 258  */
 259 arm1020e_dma_inv_range:
 260         mov     ip, #0
 261 #ifndef CONFIG_CPU_DCACHE_DISABLE
 262         tst     r0, #CACHE_DLINESIZE - 1
 263         bic     r0, r0, #CACHE_DLINESIZE - 1
 264         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
 265         tst     r1, #CACHE_DLINESIZE - 1
 266         mcrne   p15, 0, r1, c7, c10, 1          @ clean D entry
 267 1:      mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
 268         add     r0, r0, #CACHE_DLINESIZE
 269         cmp     r0, r1
 270         blo     1b
 271 #endif
 272         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 273         ret     lr
 274 
 275 /*
 276  *      dma_clean_range(start, end)
 277  *
 278  *      Clean the specified virtual address range.
 279  *
 280  *      - start - virtual start address
 281  *      - end   - virtual end address
 282  *
 283  * (same as v4wb)
 284  */
 285 arm1020e_dma_clean_range:
 286         mov     ip, #0
 287 #ifndef CONFIG_CPU_DCACHE_DISABLE
 288         bic     r0, r0, #CACHE_DLINESIZE - 1
 289 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 290         add     r0, r0, #CACHE_DLINESIZE
 291         cmp     r0, r1
 292         blo     1b
 293 #endif
 294         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 295         ret     lr
 296 
 297 /*
 298  *      dma_flush_range(start, end)
 299  *
 300  *      Clean and invalidate the specified virtual address range.
 301  *
 302  *      - start - virtual start address
 303  *      - end   - virtual end address
 304  */
 305 ENTRY(arm1020e_dma_flush_range)
 306         mov     ip, #0
 307 #ifndef CONFIG_CPU_DCACHE_DISABLE
 308         bic     r0, r0, #CACHE_DLINESIZE - 1
 309 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
 310         add     r0, r0, #CACHE_DLINESIZE
 311         cmp     r0, r1
 312         blo     1b
 313 #endif
 314         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 315         ret     lr
 316 
 317 /*
 318  *      dma_map_area(start, size, dir)
 319  *      - start - kernel virtual start address
 320  *      - size  - size of region
 321  *      - dir   - DMA direction
 322  */
 323 ENTRY(arm1020e_dma_map_area)
 324         add     r1, r1, r0
 325         cmp     r2, #DMA_TO_DEVICE
 326         beq     arm1020e_dma_clean_range
 327         bcs     arm1020e_dma_inv_range
 328         b       arm1020e_dma_flush_range
 329 ENDPROC(arm1020e_dma_map_area)
 330 
 331 /*
 332  *      dma_unmap_area(start, size, dir)
 333  *      - start - kernel virtual start address
 334  *      - size  - size of region
 335  *      - dir   - DMA direction
 336  */
 337 ENTRY(arm1020e_dma_unmap_area)
 338         ret     lr
 339 ENDPROC(arm1020e_dma_unmap_area)
 340 
 341         .globl  arm1020e_flush_kern_cache_louis
 342         .equ    arm1020e_flush_kern_cache_louis, arm1020e_flush_kern_cache_all
 343 
 344         @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
 345         define_cache_functions arm1020e
 346 
 347         .align  5
 348 ENTRY(cpu_arm1020e_dcache_clean_area)
 349 #ifndef CONFIG_CPU_DCACHE_DISABLE
 350         mov     ip, #0
 351 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 352         add     r0, r0, #CACHE_DLINESIZE
 353         subs    r1, r1, #CACHE_DLINESIZE
 354         bhi     1b
 355 #endif
 356         ret     lr
 357 
 358 /* =============================== PageTable ============================== */
 359 
 360 /*
 361  * cpu_arm1020e_switch_mm(pgd)
 362  *
 363  * Set the translation base pointer to be as described by pgd.
 364  *
 365  * pgd: new page tables
 366  */
 367         .align  5
 368 ENTRY(cpu_arm1020e_switch_mm)
 369 #ifdef CONFIG_MMU
 370 #ifndef CONFIG_CPU_DCACHE_DISABLE
 371         mcr     p15, 0, r3, c7, c10, 4
 372         mov     r1, #0xF                        @ 16 segments
 373 1:      mov     r3, #0x3F                       @ 64 entries
 374 2:      mov     ip, r3, LSL #26                 @ shift up entry
 375         orr     ip, ip, r1, LSL #5              @ shift in/up index
 376         mcr     p15, 0, ip, c7, c14, 2          @ Clean & Inval DCache entry
 377         mov     ip, #0
 378         subs    r3, r3, #1
 379         cmp     r3, #0
 380         bge     2b                              @ entries 3F to 0
 381         subs    r1, r1, #1
 382         cmp     r1, #0
 383         bge     1b                              @ segments 15 to 0
 384 
 385 #endif
 386         mov     r1, #0
 387 #ifndef CONFIG_CPU_ICACHE_DISABLE
 388         mcr     p15, 0, r1, c7, c5, 0           @ invalidate I cache
 389 #endif
 390         mcr     p15, 0, r1, c7, c10, 4          @ drain WB
 391         mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
 392         mcr     p15, 0, r1, c8, c7, 0           @ invalidate I & D TLBs
 393 #endif
 394         ret     lr
 395         
 396 /*
 397  * cpu_arm1020e_set_pte(ptep, pte)
 398  *
 399  * Set a PTE and flush it out
 400  */
 401         .align  5
 402 ENTRY(cpu_arm1020e_set_pte_ext)
 403 #ifdef CONFIG_MMU
 404         armv3_set_pte_ext
 405         mov     r0, r0
 406 #ifndef CONFIG_CPU_DCACHE_DISABLE
 407         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 408 #endif
 409 #endif /* CONFIG_MMU */
 410         ret     lr
 411 
 412         .type   __arm1020e_setup, #function
 413 __arm1020e_setup:
 414         mov     r0, #0
 415         mcr     p15, 0, r0, c7, c7              @ invalidate I,D caches on v4
 416         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer on v4
 417 #ifdef CONFIG_MMU
 418         mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
 419 #endif
 420         adr     r5, arm1020e_crval
 421         ldmia   r5, {r5, r6}
 422         mrc     p15, 0, r0, c1, c0              @ get control register v4
 423         bic     r0, r0, r5
 424         orr     r0, r0, r6
 425 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
 426         orr     r0, r0, #0x4000                 @ .R.. .... .... ....
 427 #endif
 428         ret     lr
 429         .size   __arm1020e_setup, . - __arm1020e_setup
 430 
 431         /*
 432          *  R
 433          * .RVI ZFRS BLDP WCAM
 434          * .011 1001 ..11 0101
 435          */
 436         .type   arm1020e_crval, #object
 437 arm1020e_crval:
 438         crval   clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
 439 
 440         __INITDATA
 441         @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
 442         define_processor_functions arm1020e, dabort=v4t_early_abort, pabort=legacy_pabort
 443 
 444         .section ".rodata"
 445 
 446         string  cpu_arch_name, "armv5te"
 447         string  cpu_elf_name, "v5"
 448         string  cpu_arm1020e_name, "ARM1020E"
 449 
 450         .align
 451 
 452         .section ".proc.info.init", #alloc
 453 
 454         .type   __arm1020e_proc_info,#object
 455 __arm1020e_proc_info:
 456         .long   0x4105a200                      @ ARM 1020TE (Architecture v5TE)
 457         .long   0xff0ffff0
 458         .long   PMD_TYPE_SECT | \
 459                 PMD_BIT4 | \
 460                 PMD_SECT_AP_WRITE | \
 461                 PMD_SECT_AP_READ
 462         .long   PMD_TYPE_SECT | \
 463                 PMD_BIT4 | \
 464                 PMD_SECT_AP_WRITE | \
 465                 PMD_SECT_AP_READ
 466         initfn  __arm1020e_setup, __arm1020e_proc_info
 467         .long   cpu_arch_name
 468         .long   cpu_elf_name
 469         .long   HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP
 470         .long   cpu_arm1020e_name
 471         .long   arm1020e_processor_functions
 472         .long   v4wbi_tlb_fns
 473         .long   v4wb_user_fns
 474         .long   arm1020e_cache_fns
 475         .size   __arm1020e_proc_info, . - __arm1020e_proc_info
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