root/arch/arm/mm/proc-v6.S

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   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  *  linux/arch/arm/mm/proc-v6.S
   4  *
   5  *  Copyright (C) 2001 Deep Blue Solutions Ltd.
   6  *  Modified by Catalin Marinas for noMMU support
   7  *
   8  *  This is the "shell" of the ARMv6 processor support.
   9  */
  10 #include <linux/init.h>
  11 #include <linux/linkage.h>
  12 #include <asm/assembler.h>
  13 #include <asm/asm-offsets.h>
  14 #include <asm/hwcap.h>
  15 #include <asm/pgtable-hwdef.h>
  16 #include <asm/pgtable.h>
  17 
  18 #include "proc-macros.S"
  19 
  20 #define D_CACHE_LINE_SIZE       32
  21 
  22 #define TTB_C           (1 << 0)
  23 #define TTB_S           (1 << 1)
  24 #define TTB_IMP         (1 << 2)
  25 #define TTB_RGN_NC      (0 << 3)
  26 #define TTB_RGN_WBWA    (1 << 3)
  27 #define TTB_RGN_WT      (2 << 3)
  28 #define TTB_RGN_WB      (3 << 3)
  29 
  30 #define TTB_FLAGS_UP    TTB_RGN_WBWA
  31 #define PMD_FLAGS_UP    PMD_SECT_WB
  32 #define TTB_FLAGS_SMP   TTB_RGN_WBWA|TTB_S
  33 #define PMD_FLAGS_SMP   PMD_SECT_WBWA|PMD_SECT_S
  34 
  35 ENTRY(cpu_v6_proc_init)
  36         ret     lr
  37 
  38 ENTRY(cpu_v6_proc_fin)
  39         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
  40         bic     r0, r0, #0x1000                 @ ...i............
  41         bic     r0, r0, #0x0006                 @ .............ca.
  42         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
  43         ret     lr
  44 
  45 /*
  46  *      cpu_v6_reset(loc)
  47  *
  48  *      Perform a soft reset of the system.  Put the CPU into the
  49  *      same state as it would be if it had been reset, and branch
  50  *      to what would be the reset vector.
  51  *
  52  *      - loc   - location to jump to for soft reset
  53  */
  54         .align  5
  55         .pushsection    .idmap.text, "ax"
  56 ENTRY(cpu_v6_reset)
  57         mrc     p15, 0, r1, c1, c0, 0           @ ctrl register
  58         bic     r1, r1, #0x1                    @ ...............m
  59         mcr     p15, 0, r1, c1, c0, 0           @ disable MMU
  60         mov     r1, #0
  61         mcr     p15, 0, r1, c7, c5, 4           @ ISB
  62         ret     r0
  63 ENDPROC(cpu_v6_reset)
  64         .popsection
  65 
  66 /*
  67  *      cpu_v6_do_idle()
  68  *
  69  *      Idle the processor (eg, wait for interrupt).
  70  *
  71  *      IRQs are already disabled.
  72  */
  73 ENTRY(cpu_v6_do_idle)
  74         mov     r1, #0
  75         mcr     p15, 0, r1, c7, c10, 4          @ DWB - WFI may enter a low-power mode
  76         mcr     p15, 0, r1, c7, c0, 4           @ wait for interrupt
  77         ret     lr
  78 
  79 ENTRY(cpu_v6_dcache_clean_area)
  80 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
  81         add     r0, r0, #D_CACHE_LINE_SIZE
  82         subs    r1, r1, #D_CACHE_LINE_SIZE
  83         bhi     1b
  84         ret     lr
  85 
  86 /*
  87  *      cpu_v6_switch_mm(pgd_phys, tsk)
  88  *
  89  *      Set the translation table base pointer to be pgd_phys
  90  *
  91  *      - pgd_phys - physical address of new TTB
  92  *
  93  *      It is assumed that:
  94  *      - we are not using split page tables
  95  */
  96 ENTRY(cpu_v6_switch_mm)
  97 #ifdef CONFIG_MMU
  98         mov     r2, #0
  99         mmid    r1, r1                          @ get mm->context.id
 100         ALT_SMP(orr     r0, r0, #TTB_FLAGS_SMP)
 101         ALT_UP(orr      r0, r0, #TTB_FLAGS_UP)
 102         mcr     p15, 0, r2, c7, c5, 6           @ flush BTAC/BTB
 103         mcr     p15, 0, r2, c7, c10, 4          @ drain write buffer
 104         mcr     p15, 0, r0, c2, c0, 0           @ set TTB 0
 105 #ifdef CONFIG_PID_IN_CONTEXTIDR
 106         mrc     p15, 0, r2, c13, c0, 1          @ read current context ID
 107         bic     r2, r2, #0xff                   @ extract the PID
 108         and     r1, r1, #0xff
 109         orr     r1, r1, r2                      @ insert into new context ID
 110 #endif
 111         mcr     p15, 0, r1, c13, c0, 1          @ set context ID
 112 #endif
 113         ret     lr
 114 
 115 /*
 116  *      cpu_v6_set_pte_ext(ptep, pte, ext)
 117  *
 118  *      Set a level 2 translation table entry.
 119  *
 120  *      - ptep  - pointer to level 2 translation table entry
 121  *                (hardware version is stored at -1024 bytes)
 122  *      - pte   - PTE value to store
 123  *      - ext   - value for extended PTE bits
 124  */
 125         armv6_mt_table cpu_v6
 126 
 127 ENTRY(cpu_v6_set_pte_ext)
 128 #ifdef CONFIG_MMU
 129         armv6_set_pte_ext cpu_v6
 130 #endif
 131         ret     lr
 132 
 133 /* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */
 134 .globl  cpu_v6_suspend_size
 135 .equ    cpu_v6_suspend_size, 4 * 6
 136 #ifdef CONFIG_ARM_CPU_SUSPEND
 137 ENTRY(cpu_v6_do_suspend)
 138         stmfd   sp!, {r4 - r9, lr}
 139         mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
 140 #ifdef CONFIG_MMU
 141         mrc     p15, 0, r5, c3, c0, 0   @ Domain ID
 142         mrc     p15, 0, r6, c2, c0, 1   @ Translation table base 1
 143 #endif
 144         mrc     p15, 0, r7, c1, c0, 1   @ auxiliary control register
 145         mrc     p15, 0, r8, c1, c0, 2   @ co-processor access control
 146         mrc     p15, 0, r9, c1, c0, 0   @ control register
 147         stmia   r0, {r4 - r9}
 148         ldmfd   sp!, {r4- r9, pc}
 149 ENDPROC(cpu_v6_do_suspend)
 150 
 151 ENTRY(cpu_v6_do_resume)
 152         mov     ip, #0
 153         mcr     p15, 0, ip, c7, c14, 0  @ clean+invalidate D cache
 154         mcr     p15, 0, ip, c7, c5, 0   @ invalidate I cache
 155         mcr     p15, 0, ip, c7, c15, 0  @ clean+invalidate cache
 156         mcr     p15, 0, ip, c7, c10, 4  @ drain write buffer
 157         mcr     p15, 0, ip, c13, c0, 1  @ set reserved context ID
 158         ldmia   r0, {r4 - r9}
 159         mcr     p15, 0, r4, c13, c0, 0  @ FCSE/PID
 160 #ifdef CONFIG_MMU
 161         mcr     p15, 0, r5, c3, c0, 0   @ Domain ID
 162         ALT_SMP(orr     r1, r1, #TTB_FLAGS_SMP)
 163         ALT_UP(orr      r1, r1, #TTB_FLAGS_UP)
 164         mcr     p15, 0, r1, c2, c0, 0   @ Translation table base 0
 165         mcr     p15, 0, r6, c2, c0, 1   @ Translation table base 1
 166         mcr     p15, 0, ip, c2, c0, 2   @ TTB control register
 167 #endif
 168         mcr     p15, 0, r7, c1, c0, 1   @ auxiliary control register
 169         mcr     p15, 0, r8, c1, c0, 2   @ co-processor access control
 170         mcr     p15, 0, ip, c7, c5, 4   @ ISB
 171         mov     r0, r9                  @ control register
 172         b       cpu_resume_mmu
 173 ENDPROC(cpu_v6_do_resume)
 174 #endif
 175 
 176         string  cpu_v6_name, "ARMv6-compatible processor"
 177 
 178         .align
 179 
 180 /*
 181  *      __v6_setup
 182  *
 183  *      Initialise TLB, Caches, and MMU state ready to switch the MMU
 184  *      on.  Return in r0 the new CP15 C1 control register setting.
 185  *
 186  *      We automatically detect if we have a Harvard cache, and use the
 187  *      Harvard cache control instructions insead of the unified cache
 188  *      control instructions.
 189  *
 190  *      This should be able to cover all ARMv6 cores.
 191  *
 192  *      It is assumed that:
 193  *      - cache type register is implemented
 194  */
 195 __v6_setup:
 196 #ifdef CONFIG_SMP
 197         ALT_SMP(mrc     p15, 0, r0, c1, c0, 1)  @ Enable SMP/nAMP mode
 198         ALT_UP(nop)
 199         orr     r0, r0, #0x20
 200         ALT_SMP(mcr     p15, 0, r0, c1, c0, 1)
 201         ALT_UP(nop)
 202 #endif
 203 
 204         mov     r0, #0
 205         mcr     p15, 0, r0, c7, c14, 0          @ clean+invalidate D cache
 206         mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
 207         mcr     p15, 0, r0, c7, c15, 0          @ clean+invalidate cache
 208 #ifdef CONFIG_MMU
 209         mcr     p15, 0, r0, c8, c7, 0           @ invalidate I + D TLBs
 210         mcr     p15, 0, r0, c2, c0, 2           @ TTB control register
 211         ALT_SMP(orr     r4, r4, #TTB_FLAGS_SMP)
 212         ALT_UP(orr      r4, r4, #TTB_FLAGS_UP)
 213         ALT_SMP(orr     r8, r8, #TTB_FLAGS_SMP)
 214         ALT_UP(orr      r8, r8, #TTB_FLAGS_UP)
 215         mcr     p15, 0, r8, c2, c0, 1           @ load TTB1
 216 #endif /* CONFIG_MMU */
 217         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer and
 218                                                 @ complete invalidations
 219         adr     r5, v6_crval
 220         ldmia   r5, {r5, r6}
 221  ARM_BE8(orr    r6, r6, #1 << 25)               @ big-endian page tables
 222         mrc     p15, 0, r0, c1, c0, 0           @ read control register
 223         bic     r0, r0, r5                      @ clear bits them
 224         orr     r0, r0, r6                      @ set them
 225 #ifdef CONFIG_ARM_ERRATA_364296
 226         /*
 227          * Workaround for the 364296 ARM1136 r0p2 erratum (possible cache data
 228          * corruption with hit-under-miss enabled). The conditional code below
 229          * (setting the undocumented bit 31 in the auxiliary control register
 230          * and the FI bit in the control register) disables hit-under-miss
 231          * without putting the processor into full low interrupt latency mode.
 232          */
 233         ldr     r6, =0x4107b362                 @ id for ARM1136 r0p2
 234         mrc     p15, 0, r5, c0, c0, 0           @ get processor id
 235         teq     r5, r6                          @ check for the faulty core
 236         mrceq   p15, 0, r5, c1, c0, 1           @ load aux control reg
 237         orreq   r5, r5, #(1 << 31)              @ set the undocumented bit 31
 238         mcreq   p15, 0, r5, c1, c0, 1           @ write aux control reg
 239         orreq   r0, r0, #(1 << 21)              @ low interrupt latency configuration
 240 #endif
 241         ret     lr                              @ return to head.S:__ret
 242 
 243         /*
 244          *         V X F   I D LR
 245          * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
 246          * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
 247          *         0 110       0011 1.00 .111 1101 < we want
 248          */
 249         .type   v6_crval, #object
 250 v6_crval:
 251         crval   clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
 252 
 253         __INITDATA
 254 
 255         @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
 256         define_processor_functions v6, dabort=v6_early_abort, pabort=v6_pabort, suspend=1
 257 
 258         .section ".rodata"
 259 
 260         string  cpu_arch_name, "armv6"
 261         string  cpu_elf_name, "v6"
 262         .align
 263 
 264         .section ".proc.info.init", #alloc
 265 
 266         /*
 267          * Match any ARMv6 processor core.
 268          */
 269         .type   __v6_proc_info, #object
 270 __v6_proc_info:
 271         .long   0x0007b000
 272         .long   0x0007f000
 273         ALT_SMP(.long \
 274                 PMD_TYPE_SECT | \
 275                 PMD_SECT_AP_WRITE | \
 276                 PMD_SECT_AP_READ | \
 277                 PMD_FLAGS_SMP)
 278         ALT_UP(.long \
 279                 PMD_TYPE_SECT | \
 280                 PMD_SECT_AP_WRITE | \
 281                 PMD_SECT_AP_READ | \
 282                 PMD_FLAGS_UP)
 283         .long   PMD_TYPE_SECT | \
 284                 PMD_SECT_XN | \
 285                 PMD_SECT_AP_WRITE | \
 286                 PMD_SECT_AP_READ
 287         initfn  __v6_setup, __v6_proc_info
 288         .long   cpu_arch_name
 289         .long   cpu_elf_name
 290         /* See also feat_v6_fixup() for HWCAP_TLS */
 291         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS
 292         .long   cpu_v6_name
 293         .long   v6_processor_functions
 294         .long   v6wbi_tlb_fns
 295         .long   v6_user_fns
 296         .long   v6_cache_fns
 297         .size   __v6_proc_info, . - __v6_proc_info
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