arch/arm/net/bpf_jit

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This source file includes following definitions.
jit_udiv32
jit_mod32
_emit
emit
imm8m
arm_bpf_ldst_imm12
arm_bpf_ldst_imm8
jit_fill_hole
imm_offset
bpf2a32_offset
emit_mov_i_no8m
emit_mov_i
emit_bx_r
emit_blx_r
epilogue_offset
emit_udivmod
is_stacked
arm_bpf_get_reg32
arm_bpf_get_reg64
arm_bpf_put_reg32
arm_bpf_put_reg64
emit_a32_mov_i
emit_a32_mov_i64
emit_a32_mov_se_i64
emit_a32_add_r
emit_a32_sub_r
emit_alu_r
emit_a32_alu_r
emit_a32_alu_r64
emit_a32_mov_r
emit_a32_mov_r64
emit_a32_alu_i
emit_a32_neg64
emit_a32_lsh_r64
emit_a32_arsh_r64
emit_a32_rsh_r64
emit_a32_lsh_i64
emit_a32_rsh_i64
emit_a32_arsh_i64
emit_a32_mul_r64
is_ldst_imm
emit_str_r
emit_ldx_r
emit_ar_r
emit_bpf_tail_call
emit_rev16
emit_rev32
emit_push_r64
build_prologue
build_epilogue
build_insn
build_body
validate_code
bpf_jit_compile
bpf_jit_needs_zext
bpf_int_jit_compile
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Just-In-Time compiler for eBPF filters on 32bit ARM
   4  *
   5  * Copyright (c) 2017 Shubham Bansal <illusionist.neo@gmail.com>
   6  * Copyright (c) 2011 Mircea Gherzan <mgherzan@gmail.com>
   7  */
   8 
   9 #include <linux/bpf.h>
  10 #include <linux/bitops.h>
  11 #include <linux/compiler.h>
  12 #include <linux/errno.h>
  13 #include <linux/filter.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/string.h>
  16 #include <linux/slab.h>
  17 #include <linux/if_vlan.h>
  18 
  19 #include <asm/cacheflush.h>
  20 #include <asm/hwcap.h>
  21 #include <asm/opcodes.h>
  22 #include <asm/system_info.h>
  23 
  24 #include "bpf_jit_32.h"
  25 
  26 /*
  27  * eBPF prog stack layout:
  28  *
  29  *                         high
  30  * original ARM_SP =>     +-----+
  31  *                        |     | callee saved registers
  32  *                        +-----+ <= (BPF_FP + SCRATCH_SIZE)
  33  *                        | ... | eBPF JIT scratch space
  34  * eBPF fp register =>    +-----+
  35  *   (BPF_FP)             | ... | eBPF prog stack
  36  *                        +-----+
  37  *                        |RSVD | JIT scratchpad
  38  * current ARM_SP =>      +-----+ <= (BPF_FP - STACK_SIZE + SCRATCH_SIZE)
  39  *                        |     |
  40  *                        | ... | Function call stack
  41  *                        |     |
  42  *                        +-----+
  43  *                          low
  44  *
  45  * The callee saved registers depends on whether frame pointers are enabled.
  46  * With frame pointers (to be compliant with the ABI):
  47  *
  48  *                              high
  49  * original ARM_SP =>     +--------------+ \
  50  *                        |      pc      | |
  51  * current ARM_FP =>      +--------------+ } callee saved registers
  52  *                        |r4-r9,fp,ip,lr| |
  53  *                        +--------------+ /
  54  *                              low
  55  *
  56  * Without frame pointers:
  57  *
  58  *                              high
  59  * original ARM_SP =>     +--------------+
  60  *                        |  r4-r9,fp,lr | callee saved registers
  61  * current ARM_FP =>      +--------------+
  62  *                              low
  63  *
  64  * When popping registers off the stack at the end of a BPF function, we
  65  * reference them via the current ARM_FP register.
  66  */
  67 #define CALLEE_MASK     (1 << ARM_R4 | 1 << ARM_R5 | 1 << ARM_R6 | \
  68                          1 << ARM_R7 | 1 << ARM_R8 | 1 << ARM_R9 | \
  69                          1 << ARM_FP)
  70 #define CALLEE_PUSH_MASK (CALLEE_MASK | 1 << ARM_LR)
  71 #define CALLEE_POP_MASK  (CALLEE_MASK | 1 << ARM_PC)
  72 
  73 enum {
  74         /* Stack layout - these are offsets from (top of stack - 4) */
  75         BPF_R2_HI,
  76         BPF_R2_LO,
  77         BPF_R3_HI,
  78         BPF_R3_LO,
  79         BPF_R4_HI,
  80         BPF_R4_LO,
  81         BPF_R5_HI,
  82         BPF_R5_LO,
  83         BPF_R7_HI,
  84         BPF_R7_LO,
  85         BPF_R8_HI,
  86         BPF_R8_LO,
  87         BPF_R9_HI,
  88         BPF_R9_LO,
  89         BPF_FP_HI,
  90         BPF_FP_LO,
  91         BPF_TC_HI,
  92         BPF_TC_LO,
  93         BPF_AX_HI,
  94         BPF_AX_LO,
  95         /* Stack space for BPF_REG_2, BPF_REG_3, BPF_REG_4,
  96          * BPF_REG_5, BPF_REG_7, BPF_REG_8, BPF_REG_9,
  97          * BPF_REG_FP and Tail call counts.
  98          */
  99         BPF_JIT_SCRATCH_REGS,
 100 };
 101 
 102 /*
 103  * Negative "register" values indicate the register is stored on the stack
 104  * and are the offset from the top of the eBPF JIT scratch space.
 105  */
 106 #define STACK_OFFSET(k) (-4 - (k) * 4)
 107 #define SCRATCH_SIZE    (BPF_JIT_SCRATCH_REGS * 4)
 108 
 109 #ifdef CONFIG_FRAME_POINTER
 110 #define EBPF_SCRATCH_TO_ARM_FP(x) ((x) - 4 * hweight16(CALLEE_PUSH_MASK) - 4)
 111 #else
 112 #define EBPF_SCRATCH_TO_ARM_FP(x) (x)
 113 #endif
 114 
 115 #define TMP_REG_1       (MAX_BPF_JIT_REG + 0)   /* TEMP Register 1 */
 116 #define TMP_REG_2       (MAX_BPF_JIT_REG + 1)   /* TEMP Register 2 */
 117 #define TCALL_CNT       (MAX_BPF_JIT_REG + 2)   /* Tail Call Count */
 118 
 119 #define FLAG_IMM_OVERFLOW       (1 << 0)
 120 
 121 /*
 122  * Map eBPF registers to ARM 32bit registers or stack scratch space.
 123  *
 124  * 1. First argument is passed using the arm 32bit registers and rest of the
 125  * arguments are passed on stack scratch space.
 126  * 2. First callee-saved argument is mapped to arm 32 bit registers and rest
 127  * arguments are mapped to scratch space on stack.
 128  * 3. We need two 64 bit temp registers to do complex operations on eBPF
 129  * registers.
 130  *
 131  * As the eBPF registers are all 64 bit registers and arm has only 32 bit
 132  * registers, we have to map each eBPF registers with two arm 32 bit regs or
 133  * scratch memory space and we have to build eBPF 64 bit register from those.
 134  *
 135  */
 136 static const s8 bpf2a32[][2] = {
 137         /* return value from in-kernel function, and exit value from eBPF */
 138         [BPF_REG_0] = {ARM_R1, ARM_R0},
 139         /* arguments from eBPF program to in-kernel function */
 140         [BPF_REG_1] = {ARM_R3, ARM_R2},
 141         /* Stored on stack scratch space */
 142         [BPF_REG_2] = {STACK_OFFSET(BPF_R2_HI), STACK_OFFSET(BPF_R2_LO)},
 143         [BPF_REG_3] = {STACK_OFFSET(BPF_R3_HI), STACK_OFFSET(BPF_R3_LO)},
 144         [BPF_REG_4] = {STACK_OFFSET(BPF_R4_HI), STACK_OFFSET(BPF_R4_LO)},
 145         [BPF_REG_5] = {STACK_OFFSET(BPF_R5_HI), STACK_OFFSET(BPF_R5_LO)},
 146         /* callee saved registers that in-kernel function will preserve */
 147         [BPF_REG_6] = {ARM_R5, ARM_R4},
 148         /* Stored on stack scratch space */
 149         [BPF_REG_7] = {STACK_OFFSET(BPF_R7_HI), STACK_OFFSET(BPF_R7_LO)},
 150         [BPF_REG_8] = {STACK_OFFSET(BPF_R8_HI), STACK_OFFSET(BPF_R8_LO)},
 151         [BPF_REG_9] = {STACK_OFFSET(BPF_R9_HI), STACK_OFFSET(BPF_R9_LO)},
 152         /* Read only Frame Pointer to access Stack */
 153         [BPF_REG_FP] = {STACK_OFFSET(BPF_FP_HI), STACK_OFFSET(BPF_FP_LO)},
 154         /* Temporary Register for internal BPF JIT, can be used
 155          * for constant blindings and others.
 156          */
 157         [TMP_REG_1] = {ARM_R7, ARM_R6},
 158         [TMP_REG_2] = {ARM_R9, ARM_R8},
 159         /* Tail call count. Stored on stack scratch space. */
 160         [TCALL_CNT] = {STACK_OFFSET(BPF_TC_HI), STACK_OFFSET(BPF_TC_LO)},
 161         /* temporary register for blinding constants.
 162          * Stored on stack scratch space.
 163          */
 164         [BPF_REG_AX] = {STACK_OFFSET(BPF_AX_HI), STACK_OFFSET(BPF_AX_LO)},
 165 };
 166 
 167 #define dst_lo  dst[1]
 168 #define dst_hi  dst[0]
 169 #define src_lo  src[1]
 170 #define src_hi  src[0]
 171 
 172 /*
 173  * JIT Context:
 174  *
 175  * prog                 :       bpf_prog
 176  * idx                  :       index of current last JITed instruction.
 177  * prologue_bytes       :       bytes used in prologue.
 178  * epilogue_offset      :       offset of epilogue starting.
 179  * offsets              :       array of eBPF instruction offsets in
 180  *                              JITed code.
 181  * target               :       final JITed code.
 182  * epilogue_bytes       :       no of bytes used in epilogue.
 183  * imm_count            :       no of immediate counts used for global
 184  *                              variables.
 185  * imms                 :       array of global variable addresses.
 186  */
 187 
 188 struct jit_ctx {
 189         const struct bpf_prog *prog;
 190         unsigned int idx;
 191         unsigned int prologue_bytes;
 192         unsigned int epilogue_offset;
 193         unsigned int cpu_architecture;
 194         u32 flags;
 195         u32 *offsets;
 196         u32 *target;
 197         u32 stack_size;
 198 #if __LINUX_ARM_ARCH__ < 7
 199         u16 epilogue_bytes;
 200         u16 imm_count;
 201         u32 *imms;
 202 #endif
 203 };
 204 
 205 /*
 206  * Wrappers which handle both OABI and EABI and assures Thumb2 interworking
 207  * (where the assembly routines like __aeabi_uidiv could cause problems).
 208  */
 209 static u32 jit_udiv32(u32 dividend, u32 divisor)
 210 {
 211         return dividend / divisor;
 212 }
 213 
 214 static u32 jit_mod32(u32 dividend, u32 divisor)
 215 {
 216         return dividend % divisor;
 217 }
 218 
 219 static inline void _emit(int cond, u32 inst, struct jit_ctx *ctx)
 220 {
 221         inst |= (cond << 28);
 222         inst = __opcode_to_mem_arm(inst);
 223 
 224         if (ctx->target != NULL)
 225                 ctx->target[ctx->idx] = inst;
 226 
 227         ctx->idx++;
 228 }
 229 
 230 /*
 231  * Emit an instruction that will be executed unconditionally.
 232  */
 233 static inline void emit(u32 inst, struct jit_ctx *ctx)
 234 {
 235         _emit(ARM_COND_AL, inst, ctx);
 236 }
 237 
 238 /*
 239  * This is rather horrid, but necessary to convert an integer constant
 240  * to an immediate operand for the opcodes, and be able to detect at
 241  * build time whether the constant can't be converted (iow, usable in
 242  * BUILD_BUG_ON()).
 243  */
 244 #define imm12val(v, s) (rol32(v, (s)) | (s) << 7)
 245 #define const_imm8m(x)                                  \
 246         ({ int r;                                       \
 247            u32 v = (x);                                 \
 248            if (!(v & ~0x000000ff))                      \
 249                 r = imm12val(v, 0);                     \
 250            else if (!(v & ~0xc000003f))                 \
 251                 r = imm12val(v, 2);                     \
 252            else if (!(v & ~0xf000000f))                 \
 253                 r = imm12val(v, 4);                     \
 254            else if (!(v & ~0xfc000003))                 \
 255                 r = imm12val(v, 6);                     \
 256            else if (!(v & ~0xff000000))                 \
 257                 r = imm12val(v, 8);                     \
 258            else if (!(v & ~0x3fc00000))                 \
 259                 r = imm12val(v, 10);                    \
 260            else if (!(v & ~0x0ff00000))                 \
 261                 r = imm12val(v, 12);                    \
 262            else if (!(v & ~0x03fc0000))                 \
 263                 r = imm12val(v, 14);                    \
 264            else if (!(v & ~0x00ff0000))                 \
 265                 r = imm12val(v, 16);                    \
 266            else if (!(v & ~0x003fc000))                 \
 267                 r = imm12val(v, 18);                    \
 268            else if (!(v & ~0x000ff000))                 \
 269                 r = imm12val(v, 20);                    \
 270            else if (!(v & ~0x0003fc00))                 \
 271                 r = imm12val(v, 22);                    \
 272            else if (!(v & ~0x0000ff00))                 \
 273                 r = imm12val(v, 24);                    \
 274            else if (!(v & ~0x00003fc0))                 \
 275                 r = imm12val(v, 26);                    \
 276            else if (!(v & ~0x00000ff0))                 \
 277                 r = imm12val(v, 28);                    \
 278            else if (!(v & ~0x000003fc))                 \
 279                 r = imm12val(v, 30);                    \
 280            else                                         \
 281                 r = -1;                                 \
 282            r; })
 283 
 284 /*
 285  * Checks if immediate value can be converted to imm12(12 bits) value.
 286  */
 287 static int imm8m(u32 x)
 288 {
 289         u32 rot;
 290 
 291         for (rot = 0; rot < 16; rot++)
 292                 if ((x & ~ror32(0xff, 2 * rot)) == 0)
 293                         return rol32(x, 2 * rot) | (rot << 8);
 294         return -1;
 295 }
 296 
 297 #define imm8m(x) (__builtin_constant_p(x) ? const_imm8m(x) : imm8m(x))
 298 
 299 static u32 arm_bpf_ldst_imm12(u32 op, u8 rt, u8 rn, s16 imm12)
 300 {
 301         op |= rt << 12 | rn << 16;
 302         if (imm12 >= 0)
 303                 op |= ARM_INST_LDST__U;
 304         else
 305                 imm12 = -imm12;
 306         return op | (imm12 & ARM_INST_LDST__IMM12);
 307 }
 308 
 309 static u32 arm_bpf_ldst_imm8(u32 op, u8 rt, u8 rn, s16 imm8)
 310 {
 311         op |= rt << 12 | rn << 16;
 312         if (imm8 >= 0)
 313                 op |= ARM_INST_LDST__U;
 314         else
 315                 imm8 = -imm8;
 316         return op | (imm8 & 0xf0) << 4 | (imm8 & 0x0f);
 317 }
 318 
 319 #define ARM_LDR_I(rt, rn, off)  arm_bpf_ldst_imm12(ARM_INST_LDR_I, rt, rn, off)
 320 #define ARM_LDRB_I(rt, rn, off) arm_bpf_ldst_imm12(ARM_INST_LDRB_I, rt, rn, off)
 321 #define ARM_LDRD_I(rt, rn, off) arm_bpf_ldst_imm8(ARM_INST_LDRD_I, rt, rn, off)
 322 #define ARM_LDRH_I(rt, rn, off) arm_bpf_ldst_imm8(ARM_INST_LDRH_I, rt, rn, off)
 323 
 324 #define ARM_STR_I(rt, rn, off)  arm_bpf_ldst_imm12(ARM_INST_STR_I, rt, rn, off)
 325 #define ARM_STRB_I(rt, rn, off) arm_bpf_ldst_imm12(ARM_INST_STRB_I, rt, rn, off)
 326 #define ARM_STRD_I(rt, rn, off) arm_bpf_ldst_imm8(ARM_INST_STRD_I, rt, rn, off)
 327 #define ARM_STRH_I(rt, rn, off) arm_bpf_ldst_imm8(ARM_INST_STRH_I, rt, rn, off)
 328 
 329 /*
 330  * Initializes the JIT space with undefined instructions.
 331  */
 332 static void jit_fill_hole(void *area, unsigned int size)
 333 {
 334         u32 *ptr;
 335         /* We are guaranteed to have aligned memory. */
 336         for (ptr = area; size >= sizeof(u32); size -= sizeof(u32))
 337                 *ptr++ = __opcode_to_mem_arm(ARM_INST_UDF);
 338 }
 339 
 340 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
 341 /* EABI requires the stack to be aligned to 64-bit boundaries */
 342 #define STACK_ALIGNMENT 8
 343 #else
 344 /* Stack must be aligned to 32-bit boundaries */
 345 #define STACK_ALIGNMENT 4
 346 #endif
 347 
 348 /* total stack size used in JITed code */
 349 #define _STACK_SIZE     (ctx->prog->aux->stack_depth + SCRATCH_SIZE)
 350 #define STACK_SIZE      ALIGN(_STACK_SIZE, STACK_ALIGNMENT)
 351 
 352 #if __LINUX_ARM_ARCH__ < 7
 353 
 354 static u16 imm_offset(u32 k, struct jit_ctx *ctx)
 355 {
 356         unsigned int i = 0, offset;
 357         u16 imm;
 358 
 359         /* on the "fake" run we just count them (duplicates included) */
 360         if (ctx->target == NULL) {
 361                 ctx->imm_count++;
 362                 return 0;
 363         }
 364 
 365         while ((i < ctx->imm_count) && ctx->imms[i]) {
 366                 if (ctx->imms[i] == k)
 367                         break;
 368                 i++;
 369         }
 370 
 371         if (ctx->imms[i] == 0)
 372                 ctx->imms[i] = k;
 373 
 374         /* constants go just after the epilogue */
 375         offset =  ctx->offsets[ctx->prog->len - 1] * 4;
 376         offset += ctx->prologue_bytes;
 377         offset += ctx->epilogue_bytes;
 378         offset += i * 4;
 379 
 380         ctx->target[offset / 4] = k;
 381 
 382         /* PC in ARM mode == address of the instruction + 8 */
 383         imm = offset - (8 + ctx->idx * 4);
 384 
 385         if (imm & ~0xfff) {
 386                 /*
 387                  * literal pool is too far, signal it into flags. we
 388                  * can only detect it on the second pass unfortunately.
 389                  */
 390                 ctx->flags |= FLAG_IMM_OVERFLOW;
 391                 return 0;
 392         }
 393 
 394         return imm;
 395 }
 396 
 397 #endif /* __LINUX_ARM_ARCH__ */
 398 
 399 static inline int bpf2a32_offset(int bpf_to, int bpf_from,
 400                                  const struct jit_ctx *ctx) {
 401         int to, from;
 402 
 403         if (ctx->target == NULL)
 404                 return 0;
 405         to = ctx->offsets[bpf_to];
 406         from = ctx->offsets[bpf_from];
 407 
 408         return to - from - 1;
 409 }
 410 
 411 /*
 412  * Move an immediate that's not an imm8m to a core register.
 413  */
 414 static inline void emit_mov_i_no8m(const u8 rd, u32 val, struct jit_ctx *ctx)
 415 {
 416 #if __LINUX_ARM_ARCH__ < 7
 417         emit(ARM_LDR_I(rd, ARM_PC, imm_offset(val, ctx)), ctx);
 418 #else
 419         emit(ARM_MOVW(rd, val & 0xffff), ctx);
 420         if (val > 0xffff)
 421                 emit(ARM_MOVT(rd, val >> 16), ctx);
 422 #endif
 423 }
 424 
 425 static inline void emit_mov_i(const u8 rd, u32 val, struct jit_ctx *ctx)
 426 {
 427         int imm12 = imm8m(val);
 428 
 429         if (imm12 >= 0)
 430                 emit(ARM_MOV_I(rd, imm12), ctx);
 431         else
 432                 emit_mov_i_no8m(rd, val, ctx);
 433 }
 434 
 435 static void emit_bx_r(u8 tgt_reg, struct jit_ctx *ctx)
 436 {
 437         if (elf_hwcap & HWCAP_THUMB)
 438                 emit(ARM_BX(tgt_reg), ctx);
 439         else
 440                 emit(ARM_MOV_R(ARM_PC, tgt_reg), ctx);
 441 }
 442 
 443 static inline void emit_blx_r(u8 tgt_reg, struct jit_ctx *ctx)
 444 {
 445 #if __LINUX_ARM_ARCH__ < 5
 446         emit(ARM_MOV_R(ARM_LR, ARM_PC), ctx);
 447         emit_bx_r(tgt_reg, ctx);
 448 #else
 449         emit(ARM_BLX_R(tgt_reg), ctx);
 450 #endif
 451 }
 452 
 453 static inline int epilogue_offset(const struct jit_ctx *ctx)
 454 {
 455         int to, from;
 456         /* No need for 1st dummy run */
 457         if (ctx->target == NULL)
 458                 return 0;
 459         to = ctx->epilogue_offset;
 460         from = ctx->idx;
 461 
 462         return to - from - 2;
 463 }
 464 
 465 static inline void emit_udivmod(u8 rd, u8 rm, u8 rn, struct jit_ctx *ctx, u8 op)
 466 {
 467         const s8 *tmp = bpf2a32[TMP_REG_1];
 468 
 469 #if __LINUX_ARM_ARCH__ == 7
 470         if (elf_hwcap & HWCAP_IDIVA) {
 471                 if (op == BPF_DIV)
 472                         emit(ARM_UDIV(rd, rm, rn), ctx);
 473                 else {
 474                         emit(ARM_UDIV(ARM_IP, rm, rn), ctx);
 475                         emit(ARM_MLS(rd, rn, ARM_IP, rm), ctx);
 476                 }
 477                 return;
 478         }
 479 #endif
 480 
 481         /*
 482          * For BPF_ALU | BPF_DIV | BPF_K instructions
 483          * As ARM_R1 and ARM_R0 contains 1st argument of bpf
 484          * function, we need to save it on caller side to save
 485          * it from getting destroyed within callee.
 486          * After the return from the callee, we restore ARM_R0
 487          * ARM_R1.
 488          */
 489         if (rn != ARM_R1) {
 490                 emit(ARM_MOV_R(tmp[0], ARM_R1), ctx);
 491                 emit(ARM_MOV_R(ARM_R1, rn), ctx);
 492         }
 493         if (rm != ARM_R0) {
 494                 emit(ARM_MOV_R(tmp[1], ARM_R0), ctx);
 495                 emit(ARM_MOV_R(ARM_R0, rm), ctx);
 496         }
 497 
 498         /* Call appropriate function */
 499         emit_mov_i(ARM_IP, op == BPF_DIV ?
 500                    (u32)jit_udiv32 : (u32)jit_mod32, ctx);
 501         emit_blx_r(ARM_IP, ctx);
 502 
 503         /* Save return value */
 504         if (rd != ARM_R0)
 505                 emit(ARM_MOV_R(rd, ARM_R0), ctx);
 506 
 507         /* Restore ARM_R0 and ARM_R1 */
 508         if (rn != ARM_R1)
 509                 emit(ARM_MOV_R(ARM_R1, tmp[0]), ctx);
 510         if (rm != ARM_R0)
 511                 emit(ARM_MOV_R(ARM_R0, tmp[1]), ctx);
 512 }
 513 
 514 /* Is the translated BPF register on stack? */
 515 static bool is_stacked(s8 reg)
 516 {
 517         return reg < 0;
 518 }
 519 
 520 /* If a BPF register is on the stack (stk is true), load it to the
 521  * supplied temporary register and return the temporary register
 522  * for subsequent operations, otherwise just use the CPU register.
 523  */
 524 static s8 arm_bpf_get_reg32(s8 reg, s8 tmp, struct jit_ctx *ctx)
 525 {
 526         if (is_stacked(reg)) {
 527                 emit(ARM_LDR_I(tmp, ARM_FP, EBPF_SCRATCH_TO_ARM_FP(reg)), ctx);
 528                 reg = tmp;
 529         }
 530         return reg;
 531 }
 532 
 533 static const s8 *arm_bpf_get_reg64(const s8 *reg, const s8 *tmp,
 534                                    struct jit_ctx *ctx)
 535 {
 536         if (is_stacked(reg[1])) {
 537                 if (__LINUX_ARM_ARCH__ >= 6 ||
 538                     ctx->cpu_architecture >= CPU_ARCH_ARMv5TE) {
 539                         emit(ARM_LDRD_I(tmp[1], ARM_FP,
 540                                         EBPF_SCRATCH_TO_ARM_FP(reg[1])), ctx);
 541                 } else {
 542                         emit(ARM_LDR_I(tmp[1], ARM_FP,
 543                                        EBPF_SCRATCH_TO_ARM_FP(reg[1])), ctx);
 544                         emit(ARM_LDR_I(tmp[0], ARM_FP,
 545                                        EBPF_SCRATCH_TO_ARM_FP(reg[0])), ctx);
 546                 }
 547                 reg = tmp;
 548         }
 549         return reg;
 550 }
 551 
 552 /* If a BPF register is on the stack (stk is true), save the register
 553  * back to the stack.  If the source register is not the same, then
 554  * move it into the correct register.
 555  */
 556 static void arm_bpf_put_reg32(s8 reg, s8 src, struct jit_ctx *ctx)
 557 {
 558         if (is_stacked(reg))
 559                 emit(ARM_STR_I(src, ARM_FP, EBPF_SCRATCH_TO_ARM_FP(reg)), ctx);
 560         else if (reg != src)
 561                 emit(ARM_MOV_R(reg, src), ctx);
 562 }
 563 
 564 static void arm_bpf_put_reg64(const s8 *reg, const s8 *src,
 565                               struct jit_ctx *ctx)
 566 {
 567         if (is_stacked(reg[1])) {
 568                 if (__LINUX_ARM_ARCH__ >= 6 ||
 569                     ctx->cpu_architecture >= CPU_ARCH_ARMv5TE) {
 570                         emit(ARM_STRD_I(src[1], ARM_FP,
 571                                        EBPF_SCRATCH_TO_ARM_FP(reg[1])), ctx);
 572                 } else {
 573                         emit(ARM_STR_I(src[1], ARM_FP,
 574                                        EBPF_SCRATCH_TO_ARM_FP(reg[1])), ctx);
 575                         emit(ARM_STR_I(src[0], ARM_FP,
 576                                        EBPF_SCRATCH_TO_ARM_FP(reg[0])), ctx);
 577                 }
 578         } else {
 579                 if (reg[1] != src[1])
 580                         emit(ARM_MOV_R(reg[1], src[1]), ctx);
 581                 if (reg[0] != src[0])
 582                         emit(ARM_MOV_R(reg[0], src[0]), ctx);
 583         }
 584 }
 585 
 586 static inline void emit_a32_mov_i(const s8 dst, const u32 val,
 587                                   struct jit_ctx *ctx)
 588 {
 589         const s8 *tmp = bpf2a32[TMP_REG_1];
 590 
 591         if (is_stacked(dst)) {
 592                 emit_mov_i(tmp[1], val, ctx);
 593                 arm_bpf_put_reg32(dst, tmp[1], ctx);
 594         } else {
 595                 emit_mov_i(dst, val, ctx);
 596         }
 597 }
 598 
 599 static void emit_a32_mov_i64(const s8 dst[], u64 val, struct jit_ctx *ctx)
 600 {
 601         const s8 *tmp = bpf2a32[TMP_REG_1];
 602         const s8 *rd = is_stacked(dst_lo) ? tmp : dst;
 603 
 604         emit_mov_i(rd[1], (u32)val, ctx);
 605         emit_mov_i(rd[0], val >> 32, ctx);
 606 
 607         arm_bpf_put_reg64(dst, rd, ctx);
 608 }
 609 
 610 /* Sign extended move */
 611 static inline void emit_a32_mov_se_i64(const bool is64, const s8 dst[],
 612                                        const u32 val, struct jit_ctx *ctx) {
 613         u64 val64 = val;
 614 
 615         if (is64 && (val & (1<<31)))
 616                 val64 |= 0xffffffff00000000ULL;
 617         emit_a32_mov_i64(dst, val64, ctx);
 618 }
 619 
 620 static inline void emit_a32_add_r(const u8 dst, const u8 src,
 621                               const bool is64, const bool hi,
 622                               struct jit_ctx *ctx) {
 623         /* 64 bit :
 624          *      adds dst_lo, dst_lo, src_lo
 625          *      adc dst_hi, dst_hi, src_hi
 626          * 32 bit :
 627          *      add dst_lo, dst_lo, src_lo
 628          */
 629         if (!hi && is64)
 630                 emit(ARM_ADDS_R(dst, dst, src), ctx);
 631         else if (hi && is64)
 632                 emit(ARM_ADC_R(dst, dst, src), ctx);
 633         else
 634                 emit(ARM_ADD_R(dst, dst, src), ctx);
 635 }
 636 
 637 static inline void emit_a32_sub_r(const u8 dst, const u8 src,
 638                                   const bool is64, const bool hi,
 639                                   struct jit_ctx *ctx) {
 640         /* 64 bit :
 641          *      subs dst_lo, dst_lo, src_lo
 642          *      sbc dst_hi, dst_hi, src_hi
 643          * 32 bit :
 644          *      sub dst_lo, dst_lo, src_lo
 645          */
 646         if (!hi && is64)
 647                 emit(ARM_SUBS_R(dst, dst, src), ctx);
 648         else if (hi && is64)
 649                 emit(ARM_SBC_R(dst, dst, src), ctx);
 650         else
 651                 emit(ARM_SUB_R(dst, dst, src), ctx);
 652 }
 653 
 654 static inline void emit_alu_r(const u8 dst, const u8 src, const bool is64,
 655                               const bool hi, const u8 op, struct jit_ctx *ctx){
 656         switch (BPF_OP(op)) {
 657         /* dst = dst + src */
 658         case BPF_ADD:
 659                 emit_a32_add_r(dst, src, is64, hi, ctx);
 660                 break;
 661         /* dst = dst - src */
 662         case BPF_SUB:
 663                 emit_a32_sub_r(dst, src, is64, hi, ctx);
 664                 break;
 665         /* dst = dst | src */
 666         case BPF_OR:
 667                 emit(ARM_ORR_R(dst, dst, src), ctx);
 668                 break;
 669         /* dst = dst & src */
 670         case BPF_AND:
 671                 emit(ARM_AND_R(dst, dst, src), ctx);
 672                 break;
 673         /* dst = dst ^ src */
 674         case BPF_XOR:
 675                 emit(ARM_EOR_R(dst, dst, src), ctx);
 676                 break;
 677         /* dst = dst * src */
 678         case BPF_MUL:
 679                 emit(ARM_MUL(dst, dst, src), ctx);
 680                 break;
 681         /* dst = dst << src */
 682         case BPF_LSH:
 683                 emit(ARM_LSL_R(dst, dst, src), ctx);
 684                 break;
 685         /* dst = dst >> src */
 686         case BPF_RSH:
 687                 emit(ARM_LSR_R(dst, dst, src), ctx);
 688                 break;
 689         /* dst = dst >> src (signed)*/
 690         case BPF_ARSH:
 691                 emit(ARM_MOV_SR(dst, dst, SRTYPE_ASR, src), ctx);
 692                 break;
 693         }
 694 }
 695 
 696 /* ALU operation (32 bit)
 697  * dst = dst (op) src
 698  */
 699 static inline void emit_a32_alu_r(const s8 dst, const s8 src,
 700                                   struct jit_ctx *ctx, const bool is64,
 701                                   const bool hi, const u8 op) {
 702         const s8 *tmp = bpf2a32[TMP_REG_1];
 703         s8 rn, rd;
 704 
 705         rn = arm_bpf_get_reg32(src, tmp[1], ctx);
 706         rd = arm_bpf_get_reg32(dst, tmp[0], ctx);
 707         /* ALU operation */
 708         emit_alu_r(rd, rn, is64, hi, op, ctx);
 709         arm_bpf_put_reg32(dst, rd, ctx);
 710 }
 711 
 712 /* ALU operation (64 bit) */
 713 static inline void emit_a32_alu_r64(const bool is64, const s8 dst[],
 714                                   const s8 src[], struct jit_ctx *ctx,
 715                                   const u8 op) {
 716         const s8 *tmp = bpf2a32[TMP_REG_1];
 717         const s8 *tmp2 = bpf2a32[TMP_REG_2];
 718         const s8 *rd;
 719 
 720         rd = arm_bpf_get_reg64(dst, tmp, ctx);
 721         if (is64) {
 722                 const s8 *rs;
 723 
 724                 rs = arm_bpf_get_reg64(src, tmp2, ctx);
 725 
 726                 /* ALU operation */
 727                 emit_alu_r(rd[1], rs[1], true, false, op, ctx);
 728                 emit_alu_r(rd[0], rs[0], true, true, op, ctx);
 729         } else {
 730                 s8 rs;
 731 
 732                 rs = arm_bpf_get_reg32(src_lo, tmp2[1], ctx);
 733 
 734                 /* ALU operation */
 735                 emit_alu_r(rd[1], rs, true, false, op, ctx);
 736                 if (!ctx->prog->aux->verifier_zext)
 737                         emit_a32_mov_i(rd[0], 0, ctx);
 738         }
 739 
 740         arm_bpf_put_reg64(dst, rd, ctx);
 741 }
 742 
 743 /* dst = src (4 bytes)*/
 744 static inline void emit_a32_mov_r(const s8 dst, const s8 src,
 745                                   struct jit_ctx *ctx) {
 746         const s8 *tmp = bpf2a32[TMP_REG_1];
 747         s8 rt;
 748 
 749         rt = arm_bpf_get_reg32(src, tmp[0], ctx);
 750         arm_bpf_put_reg32(dst, rt, ctx);
 751 }
 752 
 753 /* dst = src */
 754 static inline void emit_a32_mov_r64(const bool is64, const s8 dst[],
 755                                   const s8 src[],
 756                                   struct jit_ctx *ctx) {
 757         if (!is64) {
 758                 emit_a32_mov_r(dst_lo, src_lo, ctx);
 759                 if (!ctx->prog->aux->verifier_zext)
 760                         /* Zero out high 4 bytes */
 761                         emit_a32_mov_i(dst_hi, 0, ctx);
 762         } else if (__LINUX_ARM_ARCH__ < 6 &&
 763                    ctx->cpu_architecture < CPU_ARCH_ARMv5TE) {
 764                 /* complete 8 byte move */
 765                 emit_a32_mov_r(dst_lo, src_lo, ctx);
 766                 emit_a32_mov_r(dst_hi, src_hi, ctx);
 767         } else if (is_stacked(src_lo) && is_stacked(dst_lo)) {
 768                 const u8 *tmp = bpf2a32[TMP_REG_1];
 769 
 770                 emit(ARM_LDRD_I(tmp[1], ARM_FP, EBPF_SCRATCH_TO_ARM_FP(src_lo)), ctx);
 771                 emit(ARM_STRD_I(tmp[1], ARM_FP, EBPF_SCRATCH_TO_ARM_FP(dst_lo)), ctx);
 772         } else if (is_stacked(src_lo)) {
 773                 emit(ARM_LDRD_I(dst[1], ARM_FP, EBPF_SCRATCH_TO_ARM_FP(src_lo)), ctx);
 774         } else if (is_stacked(dst_lo)) {
 775                 emit(ARM_STRD_I(src[1], ARM_FP, EBPF_SCRATCH_TO_ARM_FP(dst_lo)), ctx);
 776         } else {
 777                 emit(ARM_MOV_R(dst[0], src[0]), ctx);
 778                 emit(ARM_MOV_R(dst[1], src[1]), ctx);
 779         }
 780 }
 781 
 782 /* Shift operations */
 783 static inline void emit_a32_alu_i(const s8 dst, const u32 val,
 784                                 struct jit_ctx *ctx, const u8 op) {
 785         const s8 *tmp = bpf2a32[TMP_REG_1];
 786         s8 rd;
 787 
 788         rd = arm_bpf_get_reg32(dst, tmp[0], ctx);
 789 
 790         /* Do shift operation */
 791         switch (op) {
 792         case BPF_LSH:
 793                 emit(ARM_LSL_I(rd, rd, val), ctx);
 794                 break;
 795         case BPF_RSH:
 796                 emit(ARM_LSR_I(rd, rd, val), ctx);
 797                 break;
 798         case BPF_NEG:
 799                 emit(ARM_RSB_I(rd, rd, val), ctx);
 800                 break;
 801         }
 802 
 803         arm_bpf_put_reg32(dst, rd, ctx);
 804 }
 805 
 806 /* dst = ~dst (64 bit) */
 807 static inline void emit_a32_neg64(const s8 dst[],
 808                                 struct jit_ctx *ctx){
 809         const s8 *tmp = bpf2a32[TMP_REG_1];
 810         const s8 *rd;
 811 
 812         /* Setup Operand */
 813         rd = arm_bpf_get_reg64(dst, tmp, ctx);
 814 
 815         /* Do Negate Operation */
 816         emit(ARM_RSBS_I(rd[1], rd[1], 0), ctx);
 817         emit(ARM_RSC_I(rd[0], rd[0], 0), ctx);
 818 
 819         arm_bpf_put_reg64(dst, rd, ctx);
 820 }
 821 
 822 /* dst = dst << src */
 823 static inline void emit_a32_lsh_r64(const s8 dst[], const s8 src[],
 824                                     struct jit_ctx *ctx) {
 825         const s8 *tmp = bpf2a32[TMP_REG_1];
 826         const s8 *tmp2 = bpf2a32[TMP_REG_2];
 827         const s8 *rd;
 828         s8 rt;
 829 
 830         /* Setup Operands */
 831         rt = arm_bpf_get_reg32(src_lo, tmp2[1], ctx);
 832         rd = arm_bpf_get_reg64(dst, tmp, ctx);
 833 
 834         /* Do LSH operation */
 835         emit(ARM_SUB_I(ARM_IP, rt, 32), ctx);
 836         emit(ARM_RSB_I(tmp2[0], rt, 32), ctx);
 837         emit(ARM_MOV_SR(ARM_LR, rd[0], SRTYPE_ASL, rt), ctx);
 838         emit(ARM_ORR_SR(ARM_LR, ARM_LR, rd[1], SRTYPE_ASL, ARM_IP), ctx);
 839         emit(ARM_ORR_SR(ARM_IP, ARM_LR, rd[1], SRTYPE_LSR, tmp2[0]), ctx);
 840         emit(ARM_MOV_SR(ARM_LR, rd[1], SRTYPE_ASL, rt), ctx);
 841 
 842         arm_bpf_put_reg32(dst_lo, ARM_LR, ctx);
 843         arm_bpf_put_reg32(dst_hi, ARM_IP, ctx);
 844 }
 845 
 846 /* dst = dst >> src (signed)*/
 847 static inline void emit_a32_arsh_r64(const s8 dst[], const s8 src[],
 848                                      struct jit_ctx *ctx) {
 849         const s8 *tmp = bpf2a32[TMP_REG_1];
 850         const s8 *tmp2 = bpf2a32[TMP_REG_2];
 851         const s8 *rd;
 852         s8 rt;
 853 
 854         /* Setup Operands */
 855         rt = arm_bpf_get_reg32(src_lo, tmp2[1], ctx);
 856         rd = arm_bpf_get_reg64(dst, tmp, ctx);
 857 
 858         /* Do the ARSH operation */
 859         emit(ARM_RSB_I(ARM_IP, rt, 32), ctx);
 860         emit(ARM_SUBS_I(tmp2[0], rt, 32), ctx);
 861         emit(ARM_MOV_SR(ARM_LR, rd[1], SRTYPE_LSR, rt), ctx);
 862         emit(ARM_ORR_SR(ARM_LR, ARM_LR, rd[0], SRTYPE_ASL, ARM_IP), ctx);
 863         _emit(ARM_COND_MI, ARM_B(0), ctx);
 864         emit(ARM_ORR_SR(ARM_LR, ARM_LR, rd[0], SRTYPE_ASR, tmp2[0]), ctx);
 865         emit(ARM_MOV_SR(ARM_IP, rd[0], SRTYPE_ASR, rt), ctx);
 866 
 867         arm_bpf_put_reg32(dst_lo, ARM_LR, ctx);
 868         arm_bpf_put_reg32(dst_hi, ARM_IP, ctx);
 869 }
 870 
 871 /* dst = dst >> src */
 872 static inline void emit_a32_rsh_r64(const s8 dst[], const s8 src[],
 873                                     struct jit_ctx *ctx) {
 874         const s8 *tmp = bpf2a32[TMP_REG_1];
 875         const s8 *tmp2 = bpf2a32[TMP_REG_2];
 876         const s8 *rd;
 877         s8 rt;
 878 
 879         /* Setup Operands */
 880         rt = arm_bpf_get_reg32(src_lo, tmp2[1], ctx);
 881         rd = arm_bpf_get_reg64(dst, tmp, ctx);
 882 
 883         /* Do RSH operation */
 884         emit(ARM_RSB_I(ARM_IP, rt, 32), ctx);
 885         emit(ARM_SUBS_I(tmp2[0], rt, 32), ctx);
 886         emit(ARM_MOV_SR(ARM_LR, rd[1], SRTYPE_LSR, rt), ctx);
 887         emit(ARM_ORR_SR(ARM_LR, ARM_LR, rd[0], SRTYPE_ASL, ARM_IP), ctx);
 888         emit(ARM_ORR_SR(ARM_LR, ARM_LR, rd[0], SRTYPE_LSR, tmp2[0]), ctx);
 889         emit(ARM_MOV_SR(ARM_IP, rd[0], SRTYPE_LSR, rt), ctx);
 890 
 891         arm_bpf_put_reg32(dst_lo, ARM_LR, ctx);
 892         arm_bpf_put_reg32(dst_hi, ARM_IP, ctx);
 893 }
 894 
 895 /* dst = dst << val */
 896 static inline void emit_a32_lsh_i64(const s8 dst[],
 897                                     const u32 val, struct jit_ctx *ctx){
 898         const s8 *tmp = bpf2a32[TMP_REG_1];
 899         const s8 *tmp2 = bpf2a32[TMP_REG_2];
 900         const s8 *rd;
 901 
 902         /* Setup operands */
 903         rd = arm_bpf_get_reg64(dst, tmp, ctx);
 904 
 905         /* Do LSH operation */
 906         if (val < 32) {
 907                 emit(ARM_MOV_SI(tmp2[0], rd[0], SRTYPE_ASL, val), ctx);
 908                 emit(ARM_ORR_SI(rd[0], tmp2[0], rd[1], SRTYPE_LSR, 32 - val), ctx);
 909                 emit(ARM_MOV_SI(rd[1], rd[1], SRTYPE_ASL, val), ctx);
 910         } else {
 911                 if (val == 32)
 912                         emit(ARM_MOV_R(rd[0], rd[1]), ctx);
 913                 else
 914                         emit(ARM_MOV_SI(rd[0], rd[1], SRTYPE_ASL, val - 32), ctx);
 915                 emit(ARM_EOR_R(rd[1], rd[1], rd[1]), ctx);
 916         }
 917 
 918         arm_bpf_put_reg64(dst, rd, ctx);
 919 }
 920 
 921 /* dst = dst >> val */
 922 static inline void emit_a32_rsh_i64(const s8 dst[],
 923                                     const u32 val, struct jit_ctx *ctx) {
 924         const s8 *tmp = bpf2a32[TMP_REG_1];
 925         const s8 *tmp2 = bpf2a32[TMP_REG_2];
 926         const s8 *rd;
 927 
 928         /* Setup operands */
 929         rd = arm_bpf_get_reg64(dst, tmp, ctx);
 930 
 931         /* Do LSR operation */
 932         if (val == 0) {
 933                 /* An immediate value of 0 encodes a shift amount of 32
 934                  * for LSR. To shift by 0, don't do anything.
 935                  */
 936         } else if (val < 32) {
 937                 emit(ARM_MOV_SI(tmp2[1], rd[1], SRTYPE_LSR, val), ctx);
 938                 emit(ARM_ORR_SI(rd[1], tmp2[1], rd[0], SRTYPE_ASL, 32 - val), ctx);
 939                 emit(ARM_MOV_SI(rd[0], rd[0], SRTYPE_LSR, val), ctx);
 940         } else if (val == 32) {
 941                 emit(ARM_MOV_R(rd[1], rd[0]), ctx);
 942                 emit(ARM_MOV_I(rd[0], 0), ctx);
 943         } else {
 944                 emit(ARM_MOV_SI(rd[1], rd[0], SRTYPE_LSR, val - 32), ctx);
 945                 emit(ARM_MOV_I(rd[0], 0), ctx);
 946         }
 947 
 948         arm_bpf_put_reg64(dst, rd, ctx);
 949 }
 950 
 951 /* dst = dst >> val (signed) */
 952 static inline void emit_a32_arsh_i64(const s8 dst[],
 953                                      const u32 val, struct jit_ctx *ctx){
 954         const s8 *tmp = bpf2a32[TMP_REG_1];
 955         const s8 *tmp2 = bpf2a32[TMP_REG_2];
 956         const s8 *rd;
 957 
 958         /* Setup operands */
 959         rd = arm_bpf_get_reg64(dst, tmp, ctx);
 960 
 961         /* Do ARSH operation */
 962         if (val == 0) {
 963                 /* An immediate value of 0 encodes a shift amount of 32
 964                  * for ASR. To shift by 0, don't do anything.
 965                  */
 966         } else if (val < 32) {
 967                 emit(ARM_MOV_SI(tmp2[1], rd[1], SRTYPE_LSR, val), ctx);
 968                 emit(ARM_ORR_SI(rd[1], tmp2[1], rd[0], SRTYPE_ASL, 32 - val), ctx);
 969                 emit(ARM_MOV_SI(rd[0], rd[0], SRTYPE_ASR, val), ctx);
 970         } else if (val == 32) {
 971                 emit(ARM_MOV_R(rd[1], rd[0]), ctx);
 972                 emit(ARM_MOV_SI(rd[0], rd[0], SRTYPE_ASR, 31), ctx);
 973         } else {
 974                 emit(ARM_MOV_SI(rd[1], rd[0], SRTYPE_ASR, val - 32), ctx);
 975                 emit(ARM_MOV_SI(rd[0], rd[0], SRTYPE_ASR, 31), ctx);
 976         }
 977 
 978         arm_bpf_put_reg64(dst, rd, ctx);
 979 }
 980 
 981 static inline void emit_a32_mul_r64(const s8 dst[], const s8 src[],
 982                                     struct jit_ctx *ctx) {
 983         const s8 *tmp = bpf2a32[TMP_REG_1];
 984         const s8 *tmp2 = bpf2a32[TMP_REG_2];
 985         const s8 *rd, *rt;
 986 
 987         /* Setup operands for multiplication */
 988         rd = arm_bpf_get_reg64(dst, tmp, ctx);
 989         rt = arm_bpf_get_reg64(src, tmp2, ctx);
 990 
 991         /* Do Multiplication */
 992         emit(ARM_MUL(ARM_IP, rd[1], rt[0]), ctx);
 993         emit(ARM_MUL(ARM_LR, rd[0], rt[1]), ctx);
 994         emit(ARM_ADD_R(ARM_LR, ARM_IP, ARM_LR), ctx);
 995 
 996         emit(ARM_UMULL(ARM_IP, rd[0], rd[1], rt[1]), ctx);
 997         emit(ARM_ADD_R(rd[0], ARM_LR, rd[0]), ctx);
 998 
 999         arm_bpf_put_reg32(dst_lo, ARM_IP, ctx);
1000         arm_bpf_put_reg32(dst_hi, rd[0], ctx);
1001 }
1002 
1003 static bool is_ldst_imm(s16 off, const u8 size)
1004 {
1005         s16 off_max = 0;
1006 
1007         switch (size) {
1008         case BPF_B:
1009         case BPF_W:
1010                 off_max = 0xfff;
1011                 break;
1012         case BPF_H:
1013                 off_max = 0xff;
1014                 break;
1015         case BPF_DW:
1016                 /* Need to make sure off+4 does not overflow. */
1017                 off_max = 0xfff - 4;
1018                 break;
1019         }
1020         return -off_max <= off && off <= off_max;
1021 }
1022 
1023 /* *(size *)(dst + off) = src */
1024 static inline void emit_str_r(const s8 dst, const s8 src[],
1025                               s16 off, struct jit_ctx *ctx, const u8 sz){
1026         const s8 *tmp = bpf2a32[TMP_REG_1];
1027         s8 rd;
1028 
1029         rd = arm_bpf_get_reg32(dst, tmp[1], ctx);
1030 
1031         if (!is_ldst_imm(off, sz)) {
1032                 emit_a32_mov_i(tmp[0], off, ctx);
1033                 emit(ARM_ADD_R(tmp[0], tmp[0], rd), ctx);
1034                 rd = tmp[0];
1035                 off = 0;
1036         }
1037         switch (sz) {
1038         case BPF_B:
1039                 /* Store a Byte */
1040                 emit(ARM_STRB_I(src_lo, rd, off), ctx);
1041                 break;
1042         case BPF_H:
1043                 /* Store a HalfWord */
1044                 emit(ARM_STRH_I(src_lo, rd, off), ctx);
1045                 break;
1046         case BPF_W:
1047                 /* Store a Word */
1048                 emit(ARM_STR_I(src_lo, rd, off), ctx);
1049                 break;
1050         case BPF_DW:
1051                 /* Store a Double Word */
1052                 emit(ARM_STR_I(src_lo, rd, off), ctx);
1053                 emit(ARM_STR_I(src_hi, rd, off + 4), ctx);
1054                 break;
1055         }
1056 }
1057 
1058 /* dst = *(size*)(src + off) */
1059 static inline void emit_ldx_r(const s8 dst[], const s8 src,
1060                               s16 off, struct jit_ctx *ctx, const u8 sz){
1061         const s8 *tmp = bpf2a32[TMP_REG_1];
1062         const s8 *rd = is_stacked(dst_lo) ? tmp : dst;
1063         s8 rm = src;
1064 
1065         if (!is_ldst_imm(off, sz)) {
1066                 emit_a32_mov_i(tmp[0], off, ctx);
1067                 emit(ARM_ADD_R(tmp[0], tmp[0], src), ctx);
1068                 rm = tmp[0];
1069                 off = 0;
1070         } else if (rd[1] == rm) {
1071                 emit(ARM_MOV_R(tmp[0], rm), ctx);
1072                 rm = tmp[0];
1073         }
1074         switch (sz) {
1075         case BPF_B:
1076                 /* Load a Byte */
1077                 emit(ARM_LDRB_I(rd[1], rm, off), ctx);
1078                 if (!ctx->prog->aux->verifier_zext)
1079                         emit_a32_mov_i(rd[0], 0, ctx);
1080                 break;
1081         case BPF_H:
1082                 /* Load a HalfWord */
1083                 emit(ARM_LDRH_I(rd[1], rm, off), ctx);
1084                 if (!ctx->prog->aux->verifier_zext)
1085                         emit_a32_mov_i(rd[0], 0, ctx);
1086                 break;
1087         case BPF_W:
1088                 /* Load a Word */
1089                 emit(ARM_LDR_I(rd[1], rm, off), ctx);
1090                 if (!ctx->prog->aux->verifier_zext)
1091                         emit_a32_mov_i(rd[0], 0, ctx);
1092                 break;
1093         case BPF_DW:
1094                 /* Load a Double Word */
1095                 emit(ARM_LDR_I(rd[1], rm, off), ctx);
1096                 emit(ARM_LDR_I(rd[0], rm, off + 4), ctx);
1097                 break;
1098         }
1099         arm_bpf_put_reg64(dst, rd, ctx);
1100 }
1101 
1102 /* Arithmatic Operation */
1103 static inline void emit_ar_r(const u8 rd, const u8 rt, const u8 rm,
1104                              const u8 rn, struct jit_ctx *ctx, u8 op,
1105                              bool is_jmp64) {
1106         switch (op) {
1107         case BPF_JSET:
1108                 if (is_jmp64) {
1109                         emit(ARM_AND_R(ARM_IP, rt, rn), ctx);
1110                         emit(ARM_AND_R(ARM_LR, rd, rm), ctx);
1111                         emit(ARM_ORRS_R(ARM_IP, ARM_LR, ARM_IP), ctx);
1112                 } else {
1113                         emit(ARM_ANDS_R(ARM_IP, rt, rn), ctx);
1114                 }
1115                 break;
1116         case BPF_JEQ:
1117         case BPF_JNE:
1118         case BPF_JGT:
1119         case BPF_JGE:
1120         case BPF_JLE:
1121         case BPF_JLT:
1122                 if (is_jmp64) {
1123                         emit(ARM_CMP_R(rd, rm), ctx);
1124                         /* Only compare low halve if high halve are equal. */
1125                         _emit(ARM_COND_EQ, ARM_CMP_R(rt, rn), ctx);
1126                 } else {
1127                         emit(ARM_CMP_R(rt, rn), ctx);
1128                 }
1129                 break;
1130         case BPF_JSLE:
1131         case BPF_JSGT:
1132                 emit(ARM_CMP_R(rn, rt), ctx);
1133                 if (is_jmp64)
1134                         emit(ARM_SBCS_R(ARM_IP, rm, rd), ctx);
1135                 break;
1136         case BPF_JSLT:
1137         case BPF_JSGE:
1138                 emit(ARM_CMP_R(rt, rn), ctx);
1139                 if (is_jmp64)
1140                         emit(ARM_SBCS_R(ARM_IP, rd, rm), ctx);
1141                 break;
1142         }
1143 }
1144 
1145 static int out_offset = -1; /* initialized on the first pass of build_body() */
1146 static int emit_bpf_tail_call(struct jit_ctx *ctx)
1147 {
1148 
1149         /* bpf_tail_call(void *prog_ctx, struct bpf_array *array, u64 index) */
1150         const s8 *r2 = bpf2a32[BPF_REG_2];
1151         const s8 *r3 = bpf2a32[BPF_REG_3];
1152         const s8 *tmp = bpf2a32[TMP_REG_1];
1153         const s8 *tmp2 = bpf2a32[TMP_REG_2];
1154         const s8 *tcc = bpf2a32[TCALL_CNT];
1155         const s8 *tc;
1156         const int idx0 = ctx->idx;
1157 #define cur_offset (ctx->idx - idx0)
1158 #define jmp_offset (out_offset - (cur_offset) - 2)
1159         u32 lo, hi;
1160         s8 r_array, r_index;
1161         int off;
1162 
1163         /* if (index >= array->map.max_entries)
1164          *      goto out;
1165          */
1166         BUILD_BUG_ON(offsetof(struct bpf_array, map.max_entries) >
1167                      ARM_INST_LDST__IMM12);
1168         off = offsetof(struct bpf_array, map.max_entries);
1169         r_array = arm_bpf_get_reg32(r2[1], tmp2[0], ctx);
1170         /* index is 32-bit for arrays */
1171         r_index = arm_bpf_get_reg32(r3[1], tmp2[1], ctx);
1172         /* array->map.max_entries */
1173         emit(ARM_LDR_I(tmp[1], r_array, off), ctx);
1174         /* index >= array->map.max_entries */
1175         emit(ARM_CMP_R(r_index, tmp[1]), ctx);
1176         _emit(ARM_COND_CS, ARM_B(jmp_offset), ctx);
1177 
1178         /* tmp2[0] = array, tmp2[1] = index */
1179 
1180         /* if (tail_call_cnt > MAX_TAIL_CALL_CNT)
1181          *      goto out;
1182          * tail_call_cnt++;
1183          */
1184         lo = (u32)MAX_TAIL_CALL_CNT;
1185         hi = (u32)((u64)MAX_TAIL_CALL_CNT >> 32);
1186         tc = arm_bpf_get_reg64(tcc, tmp, ctx);
1187         emit(ARM_CMP_I(tc[0], hi), ctx);
1188         _emit(ARM_COND_EQ, ARM_CMP_I(tc[1], lo), ctx);
1189         _emit(ARM_COND_HI, ARM_B(jmp_offset), ctx);
1190         emit(ARM_ADDS_I(tc[1], tc[1], 1), ctx);
1191         emit(ARM_ADC_I(tc[0], tc[0], 0), ctx);
1192         arm_bpf_put_reg64(tcc, tmp, ctx);
1193 
1194         /* prog = array->ptrs[index]
1195          * if (prog == NULL)
1196          *      goto out;
1197          */
1198         BUILD_BUG_ON(imm8m(offsetof(struct bpf_array, ptrs)) < 0);
1199         off = imm8m(offsetof(struct bpf_array, ptrs));
1200         emit(ARM_ADD_I(tmp[1], r_array, off), ctx);
1201         emit(ARM_LDR_R_SI(tmp[1], tmp[1], r_index, SRTYPE_ASL, 2), ctx);
1202         emit(ARM_CMP_I(tmp[1], 0), ctx);
1203         _emit(ARM_COND_EQ, ARM_B(jmp_offset), ctx);
1204 
1205         /* goto *(prog->bpf_func + prologue_size); */
1206         BUILD_BUG_ON(offsetof(struct bpf_prog, bpf_func) >
1207                      ARM_INST_LDST__IMM12);
1208         off = offsetof(struct bpf_prog, bpf_func);
1209         emit(ARM_LDR_I(tmp[1], tmp[1], off), ctx);
1210         emit(ARM_ADD_I(tmp[1], tmp[1], ctx->prologue_bytes), ctx);
1211         emit_bx_r(tmp[1], ctx);
1212 
1213         /* out: */
1214         if (out_offset == -1)
1215                 out_offset = cur_offset;
1216         if (cur_offset != out_offset) {
1217                 pr_err_once("tail_call out_offset = %d, expected %d!\n",
1218                             cur_offset, out_offset);
1219                 return -1;
1220         }
1221         return 0;
1222 #undef cur_offset
1223 #undef jmp_offset
1224 }
1225 
1226 /* 0xabcd => 0xcdab */
1227 static inline void emit_rev16(const u8 rd, const u8 rn, struct jit_ctx *ctx)
1228 {
1229 #if __LINUX_ARM_ARCH__ < 6
1230         const s8 *tmp2 = bpf2a32[TMP_REG_2];
1231 
1232         emit(ARM_AND_I(tmp2[1], rn, 0xff), ctx);
1233         emit(ARM_MOV_SI(tmp2[0], rn, SRTYPE_LSR, 8), ctx);
1234         emit(ARM_AND_I(tmp2[0], tmp2[0], 0xff), ctx);
1235         emit(ARM_ORR_SI(rd, tmp2[0], tmp2[1], SRTYPE_LSL, 8), ctx);
1236 #else /* ARMv6+ */
1237         emit(ARM_REV16(rd, rn), ctx);
1238 #endif
1239 }
1240 
1241 /* 0xabcdefgh => 0xghefcdab */
1242 static inline void emit_rev32(const u8 rd, const u8 rn, struct jit_ctx *ctx)
1243 {
1244 #if __LINUX_ARM_ARCH__ < 6
1245         const s8 *tmp2 = bpf2a32[TMP_REG_2];
1246 
1247         emit(ARM_AND_I(tmp2[1], rn, 0xff), ctx);
1248         emit(ARM_MOV_SI(tmp2[0], rn, SRTYPE_LSR, 24), ctx);
1249         emit(ARM_ORR_SI(ARM_IP, tmp2[0], tmp2[1], SRTYPE_LSL, 24), ctx);
1250 
1251         emit(ARM_MOV_SI(tmp2[1], rn, SRTYPE_LSR, 8), ctx);
1252         emit(ARM_AND_I(tmp2[1], tmp2[1], 0xff), ctx);
1253         emit(ARM_MOV_SI(tmp2[0], rn, SRTYPE_LSR, 16), ctx);
1254         emit(ARM_AND_I(tmp2[0], tmp2[0], 0xff), ctx);
1255         emit(ARM_MOV_SI(tmp2[0], tmp2[0], SRTYPE_LSL, 8), ctx);
1256         emit(ARM_ORR_SI(tmp2[0], tmp2[0], tmp2[1], SRTYPE_LSL, 16), ctx);
1257         emit(ARM_ORR_R(rd, ARM_IP, tmp2[0]), ctx);
1258 
1259 #else /* ARMv6+ */
1260         emit(ARM_REV(rd, rn), ctx);
1261 #endif
1262 }
1263 
1264 // push the scratch stack register on top of the stack
1265 static inline void emit_push_r64(const s8 src[], struct jit_ctx *ctx)
1266 {
1267         const s8 *tmp2 = bpf2a32[TMP_REG_2];
1268         const s8 *rt;
1269         u16 reg_set = 0;
1270 
1271         rt = arm_bpf_get_reg64(src, tmp2, ctx);
1272 
1273         reg_set = (1 << rt[1]) | (1 << rt[0]);
1274         emit(ARM_PUSH(reg_set), ctx);
1275 }
1276 
1277 static void build_prologue(struct jit_ctx *ctx)
1278 {
1279         const s8 r0 = bpf2a32[BPF_REG_0][1];
1280         const s8 r2 = bpf2a32[BPF_REG_1][1];
1281         const s8 r3 = bpf2a32[BPF_REG_1][0];
1282         const s8 r4 = bpf2a32[BPF_REG_6][1];
1283         const s8 fplo = bpf2a32[BPF_REG_FP][1];
1284         const s8 fphi = bpf2a32[BPF_REG_FP][0];
1285         const s8 *tcc = bpf2a32[TCALL_CNT];
1286 
1287         /* Save callee saved registers. */
1288 #ifdef CONFIG_FRAME_POINTER
1289         u16 reg_set = CALLEE_PUSH_MASK | 1 << ARM_IP | 1 << ARM_PC;
1290         emit(ARM_MOV_R(ARM_IP, ARM_SP), ctx);
1291         emit(ARM_PUSH(reg_set), ctx);
1292         emit(ARM_SUB_I(ARM_FP, ARM_IP, 4), ctx);
1293 #else
1294         emit(ARM_PUSH(CALLEE_PUSH_MASK), ctx);
1295         emit(ARM_MOV_R(ARM_FP, ARM_SP), ctx);
1296 #endif
1297         /* Save frame pointer for later */
1298         emit(ARM_SUB_I(ARM_IP, ARM_SP, SCRATCH_SIZE), ctx);
1299 
1300         ctx->stack_size = imm8m(STACK_SIZE);
1301 
1302         /* Set up function call stack */
1303         emit(ARM_SUB_I(ARM_SP, ARM_SP, ctx->stack_size), ctx);
1304 
1305         /* Set up BPF prog stack base register */
1306         emit_a32_mov_r(fplo, ARM_IP, ctx);
1307         emit_a32_mov_i(fphi, 0, ctx);
1308 
1309         /* mov r4, 0 */
1310         emit(ARM_MOV_I(r4, 0), ctx);
1311 
1312         /* Move BPF_CTX to BPF_R1 */
1313         emit(ARM_MOV_R(r3, r4), ctx);
1314         emit(ARM_MOV_R(r2, r0), ctx);
1315         /* Initialize Tail Count */
1316         emit(ARM_STR_I(r4, ARM_FP, EBPF_SCRATCH_TO_ARM_FP(tcc[0])), ctx);
1317         emit(ARM_STR_I(r4, ARM_FP, EBPF_SCRATCH_TO_ARM_FP(tcc[1])), ctx);
1318         /* end of prologue */
1319 }
1320 
1321 /* restore callee saved registers. */
1322 static void build_epilogue(struct jit_ctx *ctx)
1323 {
1324 #ifdef CONFIG_FRAME_POINTER
1325         /* When using frame pointers, some additional registers need to
1326          * be loaded. */
1327         u16 reg_set = CALLEE_POP_MASK | 1 << ARM_SP;
1328         emit(ARM_SUB_I(ARM_SP, ARM_FP, hweight16(reg_set) * 4), ctx);
1329         emit(ARM_LDM(ARM_SP, reg_set), ctx);
1330 #else
1331         /* Restore callee saved registers. */
1332         emit(ARM_MOV_R(ARM_SP, ARM_FP), ctx);
1333         emit(ARM_POP(CALLEE_POP_MASK), ctx);
1334 #endif
1335 }
1336 
1337 /*
1338  * Convert an eBPF instruction to native instruction, i.e
1339  * JITs an eBPF instruction.
1340  * Returns :
1341  *      0  - Successfully JITed an 8-byte eBPF instruction
1342  *      >0 - Successfully JITed a 16-byte eBPF instruction
1343  *      <0 - Failed to JIT.
1344  */
1345 static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx)
1346 {
1347         const u8 code = insn->code;
1348         const s8 *dst = bpf2a32[insn->dst_reg];
1349         const s8 *src = bpf2a32[insn->src_reg];
1350         const s8 *tmp = bpf2a32[TMP_REG_1];
1351         const s8 *tmp2 = bpf2a32[TMP_REG_2];
1352         const s16 off = insn->off;
1353         const s32 imm = insn->imm;
1354         const int i = insn - ctx->prog->insnsi;
1355         const bool is64 = BPF_CLASS(code) == BPF_ALU64;
1356         const s8 *rd, *rs;
1357         s8 rd_lo, rt, rm, rn;
1358         s32 jmp_offset;
1359 
1360 #define check_imm(bits, imm) do {                               \
1361         if ((imm) >= (1 << ((bits) - 1)) ||                     \
1362             (imm) < -(1 << ((bits) - 1))) {                     \
1363                 pr_info("[%2d] imm=%d(0x%x) out of range\n",    \
1364                         i, imm, imm);                           \
1365                 return -EINVAL;                                 \
1366         }                                                       \
1367 } while (0)
1368 #define check_imm24(imm) check_imm(24, imm)
1369 
1370         switch (code) {
1371         /* ALU operations */
1372 
1373         /* dst = src */
1374         case BPF_ALU | BPF_MOV | BPF_K:
1375         case BPF_ALU | BPF_MOV | BPF_X:
1376         case BPF_ALU64 | BPF_MOV | BPF_K:
1377         case BPF_ALU64 | BPF_MOV | BPF_X:
1378                 switch (BPF_SRC(code)) {
1379                 case BPF_X:
1380                         if (imm == 1) {
1381                                 /* Special mov32 for zext */
1382                                 emit_a32_mov_i(dst_hi, 0, ctx);
1383                                 break;
1384                         }
1385                         emit_a32_mov_r64(is64, dst, src, ctx);
1386                         break;
1387                 case BPF_K:
1388                         /* Sign-extend immediate value to destination reg */
1389                         emit_a32_mov_se_i64(is64, dst, imm, ctx);
1390                         break;
1391                 }
1392                 break;
1393         /* dst = dst + src/imm */
1394         /* dst = dst - src/imm */
1395         /* dst = dst | src/imm */
1396         /* dst = dst & src/imm */
1397         /* dst = dst ^ src/imm */
1398         /* dst = dst * src/imm */
1399         /* dst = dst << src */
1400         /* dst = dst >> src */
1401         case BPF_ALU | BPF_ADD | BPF_K:
1402         case BPF_ALU | BPF_ADD | BPF_X:
1403         case BPF_ALU | BPF_SUB | BPF_K:
1404         case BPF_ALU | BPF_SUB | BPF_X:
1405         case BPF_ALU | BPF_OR | BPF_K:
1406         case BPF_ALU | BPF_OR | BPF_X:
1407         case BPF_ALU | BPF_AND | BPF_K:
1408         case BPF_ALU | BPF_AND | BPF_X:
1409         case BPF_ALU | BPF_XOR | BPF_K:
1410         case BPF_ALU | BPF_XOR | BPF_X:
1411         case BPF_ALU | BPF_MUL | BPF_K:
1412         case BPF_ALU | BPF_MUL | BPF_X:
1413         case BPF_ALU | BPF_LSH | BPF_X:
1414         case BPF_ALU | BPF_RSH | BPF_X:
1415         case BPF_ALU | BPF_ARSH | BPF_K:
1416         case BPF_ALU | BPF_ARSH | BPF_X:
1417         case BPF_ALU64 | BPF_ADD | BPF_K:
1418         case BPF_ALU64 | BPF_ADD | BPF_X:
1419         case BPF_ALU64 | BPF_SUB | BPF_K:
1420         case BPF_ALU64 | BPF_SUB | BPF_X:
1421         case BPF_ALU64 | BPF_OR | BPF_K:
1422         case BPF_ALU64 | BPF_OR | BPF_X:
1423         case BPF_ALU64 | BPF_AND | BPF_K:
1424         case BPF_ALU64 | BPF_AND | BPF_X:
1425         case BPF_ALU64 | BPF_XOR | BPF_K:
1426         case BPF_ALU64 | BPF_XOR | BPF_X:
1427                 switch (BPF_SRC(code)) {
1428                 case BPF_X:
1429                         emit_a32_alu_r64(is64, dst, src, ctx, BPF_OP(code));
1430                         break;
1431                 case BPF_K:
1432                         /* Move immediate value to the temporary register
1433                          * and then do the ALU operation on the temporary
1434                          * register as this will sign-extend the immediate
1435                          * value into temporary reg and then it would be
1436                          * safe to do the operation on it.
1437                          */
1438                         emit_a32_mov_se_i64(is64, tmp2, imm, ctx);
1439                         emit_a32_alu_r64(is64, dst, tmp2, ctx, BPF_OP(code));
1440                         break;
1441                 }
1442                 break;
1443         /* dst = dst / src(imm) */
1444         /* dst = dst % src(imm) */
1445         case BPF_ALU | BPF_DIV | BPF_K:
1446         case BPF_ALU | BPF_DIV | BPF_X:
1447         case BPF_ALU | BPF_MOD | BPF_K:
1448         case BPF_ALU | BPF_MOD | BPF_X:
1449                 rd_lo = arm_bpf_get_reg32(dst_lo, tmp2[1], ctx);
1450                 switch (BPF_SRC(code)) {
1451                 case BPF_X:
1452                         rt = arm_bpf_get_reg32(src_lo, tmp2[0], ctx);
1453                         break;
1454                 case BPF_K:
1455                         rt = tmp2[0];
1456                         emit_a32_mov_i(rt, imm, ctx);
1457                         break;
1458                 default:
1459                         rt = src_lo;
1460                         break;
1461                 }
1462                 emit_udivmod(rd_lo, rd_lo, rt, ctx, BPF_OP(code));
1463                 arm_bpf_put_reg32(dst_lo, rd_lo, ctx);
1464                 if (!ctx->prog->aux->verifier_zext)
1465                         emit_a32_mov_i(dst_hi, 0, ctx);
1466                 break;
1467         case BPF_ALU64 | BPF_DIV | BPF_K:
1468         case BPF_ALU64 | BPF_DIV | BPF_X:
1469         case BPF_ALU64 | BPF_MOD | BPF_K:
1470         case BPF_ALU64 | BPF_MOD | BPF_X:
1471                 goto notyet;
1472         /* dst = dst >> imm */
1473         /* dst = dst << imm */
1474         case BPF_ALU | BPF_RSH | BPF_K:
1475         case BPF_ALU | BPF_LSH | BPF_K:
1476                 if (unlikely(imm > 31))
1477                         return -EINVAL;
1478                 if (imm)
1479                         emit_a32_alu_i(dst_lo, imm, ctx, BPF_OP(code));
1480                 if (!ctx->prog->aux->verifier_zext)
1481                         emit_a32_mov_i(dst_hi, 0, ctx);
1482                 break;
1483         /* dst = dst << imm */
1484         case BPF_ALU64 | BPF_LSH | BPF_K:
1485                 if (unlikely(imm > 63))
1486                         return -EINVAL;
1487                 emit_a32_lsh_i64(dst, imm, ctx);
1488                 break;
1489         /* dst = dst >> imm */
1490         case BPF_ALU64 | BPF_RSH | BPF_K:
1491                 if (unlikely(imm > 63))
1492                         return -EINVAL;
1493                 emit_a32_rsh_i64(dst, imm, ctx);
1494                 break;
1495         /* dst = dst << src */
1496         case BPF_ALU64 | BPF_LSH | BPF_X:
1497                 emit_a32_lsh_r64(dst, src, ctx);
1498                 break;
1499         /* dst = dst >> src */
1500         case BPF_ALU64 | BPF_RSH | BPF_X:
1501                 emit_a32_rsh_r64(dst, src, ctx);
1502                 break;
1503         /* dst = dst >> src (signed) */
1504         case BPF_ALU64 | BPF_ARSH | BPF_X:
1505                 emit_a32_arsh_r64(dst, src, ctx);
1506                 break;
1507         /* dst = dst >> imm (signed) */
1508         case BPF_ALU64 | BPF_ARSH | BPF_K:
1509                 if (unlikely(imm > 63))
1510                         return -EINVAL;
1511                 emit_a32_arsh_i64(dst, imm, ctx);
1512                 break;
1513         /* dst = ~dst */
1514         case BPF_ALU | BPF_NEG:
1515                 emit_a32_alu_i(dst_lo, 0, ctx, BPF_OP(code));
1516                 if (!ctx->prog->aux->verifier_zext)
1517                         emit_a32_mov_i(dst_hi, 0, ctx);
1518                 break;
1519         /* dst = ~dst (64 bit) */
1520         case BPF_ALU64 | BPF_NEG:
1521                 emit_a32_neg64(dst, ctx);
1522                 break;
1523         /* dst = dst * src/imm */
1524         case BPF_ALU64 | BPF_MUL | BPF_X:
1525         case BPF_ALU64 | BPF_MUL | BPF_K:
1526                 switch (BPF_SRC(code)) {
1527                 case BPF_X:
1528                         emit_a32_mul_r64(dst, src, ctx);
1529                         break;
1530                 case BPF_K:
1531                         /* Move immediate value to the temporary register
1532                          * and then do the multiplication on it as this
1533                          * will sign-extend the immediate value into temp
1534                          * reg then it would be safe to do the operation
1535                          * on it.
1536                          */
1537                         emit_a32_mov_se_i64(is64, tmp2, imm, ctx);
1538                         emit_a32_mul_r64(dst, tmp2, ctx);
1539                         break;
1540                 }
1541                 break;
1542         /* dst = htole(dst) */
1543         /* dst = htobe(dst) */
1544         case BPF_ALU | BPF_END | BPF_FROM_LE:
1545         case BPF_ALU | BPF_END | BPF_FROM_BE:
1546                 rd = arm_bpf_get_reg64(dst, tmp, ctx);
1547                 if (BPF_SRC(code) == BPF_FROM_LE)
1548                         goto emit_bswap_uxt;
1549                 switch (imm) {
1550                 case 16:
1551                         emit_rev16(rd[1], rd[1], ctx);
1552                         goto emit_bswap_uxt;
1553                 case 32:
1554                         emit_rev32(rd[1], rd[1], ctx);
1555                         goto emit_bswap_uxt;
1556                 case 64:
1557                         emit_rev32(ARM_LR, rd[1], ctx);
1558                         emit_rev32(rd[1], rd[0], ctx);
1559                         emit(ARM_MOV_R(rd[0], ARM_LR), ctx);
1560                         break;
1561                 }
1562                 goto exit;
1563 emit_bswap_uxt:
1564                 switch (imm) {
1565                 case 16:
1566                         /* zero-extend 16 bits into 64 bits */
1567 #if __LINUX_ARM_ARCH__ < 6
1568                         emit_a32_mov_i(tmp2[1], 0xffff, ctx);
1569                         emit(ARM_AND_R(rd[1], rd[1], tmp2[1]), ctx);
1570 #else /* ARMv6+ */
1571                         emit(ARM_UXTH(rd[1], rd[1]), ctx);
1572 #endif
1573                         if (!ctx->prog->aux->verifier_zext)
1574                                 emit(ARM_EOR_R(rd[0], rd[0], rd[0]), ctx);
1575                         break;
1576                 case 32:
1577                         /* zero-extend 32 bits into 64 bits */
1578                         if (!ctx->prog->aux->verifier_zext)
1579                                 emit(ARM_EOR_R(rd[0], rd[0], rd[0]), ctx);
1580                         break;
1581                 case 64:
1582                         /* nop */
1583                         break;
1584                 }
1585 exit:
1586                 arm_bpf_put_reg64(dst, rd, ctx);
1587                 break;
1588         /* dst = imm64 */
1589         case BPF_LD | BPF_IMM | BPF_DW:
1590         {
1591                 u64 val = (u32)imm | (u64)insn[1].imm << 32;
1592 
1593                 emit_a32_mov_i64(dst, val, ctx);
1594 
1595                 return 1;
1596         }
1597         /* LDX: dst = *(size *)(src + off) */
1598         case BPF_LDX | BPF_MEM | BPF_W:
1599         case BPF_LDX | BPF_MEM | BPF_H:
1600         case BPF_LDX | BPF_MEM | BPF_B:
1601         case BPF_LDX | BPF_MEM | BPF_DW:
1602                 rn = arm_bpf_get_reg32(src_lo, tmp2[1], ctx);
1603                 emit_ldx_r(dst, rn, off, ctx, BPF_SIZE(code));
1604                 break;
1605         /* ST: *(size *)(dst + off) = imm */
1606         case BPF_ST | BPF_MEM | BPF_W:
1607         case BPF_ST | BPF_MEM | BPF_H:
1608         case BPF_ST | BPF_MEM | BPF_B:
1609         case BPF_ST | BPF_MEM | BPF_DW:
1610                 switch (BPF_SIZE(code)) {
1611                 case BPF_DW:
1612                         /* Sign-extend immediate value into temp reg */
1613                         emit_a32_mov_se_i64(true, tmp2, imm, ctx);
1614                         break;
1615                 case BPF_W:
1616                 case BPF_H:
1617                 case BPF_B:
1618                         emit_a32_mov_i(tmp2[1], imm, ctx);
1619                         break;
1620                 }
1621                 emit_str_r(dst_lo, tmp2, off, ctx, BPF_SIZE(code));
1622                 break;
1623         /* STX XADD: lock *(u32 *)(dst + off) += src */
1624         case BPF_STX | BPF_XADD | BPF_W:
1625         /* STX XADD: lock *(u64 *)(dst + off) += src */
1626         case BPF_STX | BPF_XADD | BPF_DW:
1627                 goto notyet;
1628         /* STX: *(size *)(dst + off) = src */
1629         case BPF_STX | BPF_MEM | BPF_W:
1630         case BPF_STX | BPF_MEM | BPF_H:
1631         case BPF_STX | BPF_MEM | BPF_B:
1632         case BPF_STX | BPF_MEM | BPF_DW:
1633                 rs = arm_bpf_get_reg64(src, tmp2, ctx);
1634                 emit_str_r(dst_lo, rs, off, ctx, BPF_SIZE(code));
1635                 break;
1636         /* PC += off if dst == src */
1637         /* PC += off if dst > src */
1638         /* PC += off if dst >= src */
1639         /* PC += off if dst < src */
1640         /* PC += off if dst <= src */
1641         /* PC += off if dst != src */
1642         /* PC += off if dst > src (signed) */
1643         /* PC += off if dst >= src (signed) */
1644         /* PC += off if dst < src (signed) */
1645         /* PC += off if dst <= src (signed) */
1646         /* PC += off if dst & src */
1647         case BPF_JMP | BPF_JEQ | BPF_X:
1648         case BPF_JMP | BPF_JGT | BPF_X:
1649         case BPF_JMP | BPF_JGE | BPF_X:
1650         case BPF_JMP | BPF_JNE | BPF_X:
1651         case BPF_JMP | BPF_JSGT | BPF_X:
1652         case BPF_JMP | BPF_JSGE | BPF_X:
1653         case BPF_JMP | BPF_JSET | BPF_X:
1654         case BPF_JMP | BPF_JLE | BPF_X:
1655         case BPF_JMP | BPF_JLT | BPF_X:
1656         case BPF_JMP | BPF_JSLT | BPF_X:
1657         case BPF_JMP | BPF_JSLE | BPF_X:
1658         case BPF_JMP32 | BPF_JEQ | BPF_X:
1659         case BPF_JMP32 | BPF_JGT | BPF_X:
1660         case BPF_JMP32 | BPF_JGE | BPF_X:
1661         case BPF_JMP32 | BPF_JNE | BPF_X:
1662         case BPF_JMP32 | BPF_JSGT | BPF_X:
1663         case BPF_JMP32 | BPF_JSGE | BPF_X:
1664         case BPF_JMP32 | BPF_JSET | BPF_X:
1665         case BPF_JMP32 | BPF_JLE | BPF_X:
1666         case BPF_JMP32 | BPF_JLT | BPF_X:
1667         case BPF_JMP32 | BPF_JSLT | BPF_X:
1668         case BPF_JMP32 | BPF_JSLE | BPF_X:
1669                 /* Setup source registers */
1670                 rm = arm_bpf_get_reg32(src_hi, tmp2[0], ctx);
1671                 rn = arm_bpf_get_reg32(src_lo, tmp2[1], ctx);
1672                 goto go_jmp;
1673         /* PC += off if dst == imm */
1674         /* PC += off if dst > imm */
1675         /* PC += off if dst >= imm */
1676         /* PC += off if dst < imm */
1677         /* PC += off if dst <= imm */
1678         /* PC += off if dst != imm */
1679         /* PC += off if dst > imm (signed) */
1680         /* PC += off if dst >= imm (signed) */
1681         /* PC += off if dst < imm (signed) */
1682         /* PC += off if dst <= imm (signed) */
1683         /* PC += off if dst & imm */
1684         case BPF_JMP | BPF_JEQ | BPF_K:
1685         case BPF_JMP | BPF_JGT | BPF_K:
1686         case BPF_JMP | BPF_JGE | BPF_K:
1687         case BPF_JMP | BPF_JNE | BPF_K:
1688         case BPF_JMP | BPF_JSGT | BPF_K:
1689         case BPF_JMP | BPF_JSGE | BPF_K:
1690         case BPF_JMP | BPF_JSET | BPF_K:
1691         case BPF_JMP | BPF_JLT | BPF_K:
1692         case BPF_JMP | BPF_JLE | BPF_K:
1693         case BPF_JMP | BPF_JSLT | BPF_K:
1694         case BPF_JMP | BPF_JSLE | BPF_K:
1695         case BPF_JMP32 | BPF_JEQ | BPF_K:
1696         case BPF_JMP32 | BPF_JGT | BPF_K:
1697         case BPF_JMP32 | BPF_JGE | BPF_K:
1698         case BPF_JMP32 | BPF_JNE | BPF_K:
1699         case BPF_JMP32 | BPF_JSGT | BPF_K:
1700         case BPF_JMP32 | BPF_JSGE | BPF_K:
1701         case BPF_JMP32 | BPF_JSET | BPF_K:
1702         case BPF_JMP32 | BPF_JLT | BPF_K:
1703         case BPF_JMP32 | BPF_JLE | BPF_K:
1704         case BPF_JMP32 | BPF_JSLT | BPF_K:
1705         case BPF_JMP32 | BPF_JSLE | BPF_K:
1706                 if (off == 0)
1707                         break;
1708                 rm = tmp2[0];
1709                 rn = tmp2[1];
1710                 /* Sign-extend immediate value */
1711                 emit_a32_mov_se_i64(true, tmp2, imm, ctx);
1712 go_jmp:
1713                 /* Setup destination register */
1714                 rd = arm_bpf_get_reg64(dst, tmp, ctx);
1715 
1716                 /* Check for the condition */
1717                 emit_ar_r(rd[0], rd[1], rm, rn, ctx, BPF_OP(code),
1718                           BPF_CLASS(code) == BPF_JMP);
1719 
1720                 /* Setup JUMP instruction */
1721                 jmp_offset = bpf2a32_offset(i+off, i, ctx);
1722                 switch (BPF_OP(code)) {
1723                 case BPF_JNE:
1724                 case BPF_JSET:
1725                         _emit(ARM_COND_NE, ARM_B(jmp_offset), ctx);
1726                         break;
1727                 case BPF_JEQ:
1728                         _emit(ARM_COND_EQ, ARM_B(jmp_offset), ctx);
1729                         break;
1730                 case BPF_JGT:
1731                         _emit(ARM_COND_HI, ARM_B(jmp_offset), ctx);
1732                         break;
1733                 case BPF_JGE:
1734                         _emit(ARM_COND_CS, ARM_B(jmp_offset), ctx);
1735                         break;
1736                 case BPF_JSGT:
1737                         _emit(ARM_COND_LT, ARM_B(jmp_offset), ctx);
1738                         break;
1739                 case BPF_JSGE:
1740                         _emit(ARM_COND_GE, ARM_B(jmp_offset), ctx);
1741                         break;
1742                 case BPF_JLE:
1743                         _emit(ARM_COND_LS, ARM_B(jmp_offset), ctx);
1744                         break;
1745                 case BPF_JLT:
1746                         _emit(ARM_COND_CC, ARM_B(jmp_offset), ctx);
1747                         break;
1748                 case BPF_JSLT:
1749                         _emit(ARM_COND_LT, ARM_B(jmp_offset), ctx);
1750                         break;
1751                 case BPF_JSLE:
1752                         _emit(ARM_COND_GE, ARM_B(jmp_offset), ctx);
1753                         break;
1754                 }
1755                 break;
1756         /* JMP OFF */
1757         case BPF_JMP | BPF_JA:
1758         {
1759                 if (off == 0)
1760                         break;
1761                 jmp_offset = bpf2a32_offset(i+off, i, ctx);
1762                 check_imm24(jmp_offset);
1763                 emit(ARM_B(jmp_offset), ctx);
1764                 break;
1765         }
1766         /* tail call */
1767         case BPF_JMP | BPF_TAIL_CALL:
1768                 if (emit_bpf_tail_call(ctx))
1769                         return -EFAULT;
1770                 break;
1771         /* function call */
1772         case BPF_JMP | BPF_CALL:
1773         {
1774                 const s8 *r0 = bpf2a32[BPF_REG_0];
1775                 const s8 *r1 = bpf2a32[BPF_REG_1];
1776                 const s8 *r2 = bpf2a32[BPF_REG_2];
1777                 const s8 *r3 = bpf2a32[BPF_REG_3];
1778                 const s8 *r4 = bpf2a32[BPF_REG_4];
1779                 const s8 *r5 = bpf2a32[BPF_REG_5];
1780                 const u32 func = (u32)__bpf_call_base + (u32)imm;
1781 
1782                 emit_a32_mov_r64(true, r0, r1, ctx);
1783                 emit_a32_mov_r64(true, r1, r2, ctx);
1784                 emit_push_r64(r5, ctx);
1785                 emit_push_r64(r4, ctx);
1786                 emit_push_r64(r3, ctx);
1787 
1788                 emit_a32_mov_i(tmp[1], func, ctx);
1789                 emit_blx_r(tmp[1], ctx);
1790 
1791                 emit(ARM_ADD_I(ARM_SP, ARM_SP, imm8m(24)), ctx); // callee clean
1792                 break;
1793         }
1794         /* function return */
1795         case BPF_JMP | BPF_EXIT:
1796                 /* Optimization: when last instruction is EXIT
1797                  * simply fallthrough to epilogue.
1798                  */
1799                 if (i == ctx->prog->len - 1)
1800                         break;
1801                 jmp_offset = epilogue_offset(ctx);
1802                 check_imm24(jmp_offset);
1803                 emit(ARM_B(jmp_offset), ctx);
1804                 break;
1805 notyet:
1806                 pr_info_once("*** NOT YET: opcode %02x ***\n", code);
1807                 return -EFAULT;
1808         default:
1809                 pr_err_once("unknown opcode %02x\n", code);
1810                 return -EINVAL;
1811         }
1812 
1813         if (ctx->flags & FLAG_IMM_OVERFLOW)
1814                 /*
1815                  * this instruction generated an overflow when
1816                  * trying to access the literal pool, so
1817                  * delegate this filter to the kernel interpreter.
1818                  */
1819                 return -1;
1820         return 0;
1821 }
1822 
1823 static int build_body(struct jit_ctx *ctx)
1824 {
1825         const struct bpf_prog *prog = ctx->prog;
1826         unsigned int i;
1827 
1828         for (i = 0; i < prog->len; i++) {
1829                 const struct bpf_insn *insn = &(prog->insnsi[i]);
1830                 int ret;
1831 
1832                 ret = build_insn(insn, ctx);
1833 
1834                 /* It's used with loading the 64 bit immediate value. */
1835                 if (ret > 0) {
1836                         i++;
1837                         if (ctx->target == NULL)
1838                                 ctx->offsets[i] = ctx->idx;
1839                         continue;
1840                 }
1841 
1842                 if (ctx->target == NULL)
1843                         ctx->offsets[i] = ctx->idx;
1844 
1845                 /* If unsuccesfull, return with error code */
1846                 if (ret)
1847                         return ret;
1848         }
1849         return 0;
1850 }
1851 
1852 static int validate_code(struct jit_ctx *ctx)
1853 {
1854         int i;
1855 
1856         for (i = 0; i < ctx->idx; i++) {
1857                 if (ctx->target[i] == __opcode_to_mem_arm(ARM_INST_UDF))
1858                         return -1;
1859         }
1860 
1861         return 0;
1862 }
1863 
1864 void bpf_jit_compile(struct bpf_prog *prog)
1865 {
1866         /* Nothing to do here. We support Internal BPF. */
1867 }
1868 
1869 bool bpf_jit_needs_zext(void)
1870 {
1871         return true;
1872 }
1873 
1874 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
1875 {
1876         struct bpf_prog *tmp, *orig_prog = prog;
1877         struct bpf_binary_header *header;
1878         bool tmp_blinded = false;
1879         struct jit_ctx ctx;
1880         unsigned int tmp_idx;
1881         unsigned int image_size;
1882         u8 *image_ptr;
1883 
1884         /* If BPF JIT was not enabled then we must fall back to
1885          * the interpreter.
1886          */
1887         if (!prog->jit_requested)
1888                 return orig_prog;
1889 
1890         /* If constant blinding was enabled and we failed during blinding
1891          * then we must fall back to the interpreter. Otherwise, we save
1892          * the new JITed code.
1893          */
1894         tmp = bpf_jit_blind_constants(prog);
1895 
1896         if (IS_ERR(tmp))
1897                 return orig_prog;
1898         if (tmp != prog) {
1899                 tmp_blinded = true;
1900                 prog = tmp;
1901         }
1902 
1903         memset(&ctx, 0, sizeof(ctx));
1904         ctx.prog = prog;
1905         ctx.cpu_architecture = cpu_architecture();
1906 
1907         /* Not able to allocate memory for offsets[] , then
1908          * we must fall back to the interpreter
1909          */
1910         ctx.offsets = kcalloc(prog->len, sizeof(int), GFP_KERNEL);
1911         if (ctx.offsets == NULL) {
1912                 prog = orig_prog;
1913                 goto out;
1914         }
1915 
1916         /* 1) fake pass to find in the length of the JITed code,
1917          * to compute ctx->offsets and other context variables
1918          * needed to compute final JITed code.
1919          * Also, calculate random starting pointer/start of JITed code
1920          * which is prefixed by random number of fault instructions.
1921          *
1922          * If the first pass fails then there is no chance of it
1923          * being successful in the second pass, so just fall back
1924          * to the interpreter.
1925          */
1926         if (build_body(&ctx)) {
1927                 prog = orig_prog;
1928                 goto out_off;
1929         }
1930 
1931         tmp_idx = ctx.idx;
1932         build_prologue(&ctx);
1933         ctx.prologue_bytes = (ctx.idx - tmp_idx) * 4;
1934 
1935         ctx.epilogue_offset = ctx.idx;
1936 
1937 #if __LINUX_ARM_ARCH__ < 7
1938         tmp_idx = ctx.idx;
1939         build_epilogue(&ctx);
1940         ctx.epilogue_bytes = (ctx.idx - tmp_idx) * 4;
1941 
1942         ctx.idx += ctx.imm_count;
1943         if (ctx.imm_count) {
1944                 ctx.imms = kcalloc(ctx.imm_count, sizeof(u32), GFP_KERNEL);
1945                 if (ctx.imms == NULL) {
1946                         prog = orig_prog;
1947                         goto out_off;
1948                 }
1949         }
1950 #else
1951         /* there's nothing about the epilogue on ARMv7 */
1952         build_epilogue(&ctx);
1953 #endif
1954         /* Now we can get the actual image size of the JITed arm code.
1955          * Currently, we are not considering the THUMB-2 instructions
1956          * for jit, although it can decrease the size of the image.
1957          *
1958          * As each arm instruction is of length 32bit, we are translating
1959          * number of JITed intructions into the size required to store these
1960          * JITed code.
1961          */
1962         image_size = sizeof(u32) * ctx.idx;
1963 
1964         /* Now we know the size of the structure to make */
1965         header = bpf_jit_binary_alloc(image_size, &image_ptr,
1966                                       sizeof(u32), jit_fill_hole);
1967         /* Not able to allocate memory for the structure then
1968          * we must fall back to the interpretation
1969          */
1970         if (header == NULL) {
1971                 prog = orig_prog;
1972                 goto out_imms;
1973         }
1974 
1975         /* 2.) Actual pass to generate final JIT code */
1976         ctx.target = (u32 *) image_ptr;
1977         ctx.idx = 0;
1978 
1979         build_prologue(&ctx);
1980 
1981         /* If building the body of the JITed code fails somehow,
1982          * we fall back to the interpretation.
1983          */
1984         if (build_body(&ctx) < 0) {
1985                 image_ptr = NULL;
1986                 bpf_jit_binary_free(header);
1987                 prog = orig_prog;
1988                 goto out_imms;
1989         }
1990         build_epilogue(&ctx);
1991 
1992         /* 3.) Extra pass to validate JITed Code */
1993         if (validate_code(&ctx)) {
1994                 image_ptr = NULL;
1995                 bpf_jit_binary_free(header);
1996                 prog = orig_prog;
1997                 goto out_imms;
1998         }
1999         flush_icache_range((u32)header, (u32)(ctx.target + ctx.idx));
2000 
2001         if (bpf_jit_enable > 1)
2002                 /* there are 2 passes here */
2003                 bpf_jit_dump(prog->len, image_size, 2, ctx.target);
2004 
2005         bpf_jit_binary_lock_ro(header);
2006         prog->bpf_func = (void *)ctx.target;
2007         prog->jited = 1;
2008         prog->jited_len = image_size;
2009 
2010 out_imms:
2011 #if __LINUX_ARM_ARCH__ < 7
2012         if (ctx.imm_count)
2013                 kfree(ctx.imms);
2014 #endif
2015 out_off:
2016         kfree(ctx.offsets);
2017 out:
2018         if (tmp_blinded)
2019                 bpf_jit_prog_release_other(prog, prog == orig_prog ?
2020                                            tmp : orig_prog);
2021         return prog;
2022 }
2023
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root/arch/arm/net/bpf_jit_32.c

DEFINITIONS
