root/arch/arm/mach-s3c24xx/include/mach/regs-irq.h

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INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
   4  *                    http://www.simtec.co.uk/products/SWLINUX/
   5  */
   6 
   7 
   8 #ifndef ___ASM_ARCH_REGS_IRQ_H
   9 #define ___ASM_ARCH_REGS_IRQ_H
  10 
  11 /* interrupt controller */
  12 
  13 #define S3C2410_IRQREG(x)   ((x) + S3C24XX_VA_IRQ)
  14 #define S3C2410_EINTREG(x)  ((x) + S3C24XX_VA_GPIO)
  15 #define S3C24XX_EINTREG(x)  ((x) + S3C24XX_VA_GPIO2)
  16 
  17 #define S3C2410_SRCPND         S3C2410_IRQREG(0x000)
  18 #define S3C2410_INTMOD         S3C2410_IRQREG(0x004)
  19 #define S3C2410_INTMSK         S3C2410_IRQREG(0x008)
  20 #define S3C2410_PRIORITY       S3C2410_IRQREG(0x00C)
  21 #define S3C2410_INTPND         S3C2410_IRQREG(0x010)
  22 #define S3C2410_INTOFFSET      S3C2410_IRQREG(0x014)
  23 #define S3C2410_SUBSRCPND      S3C2410_IRQREG(0x018)
  24 #define S3C2410_INTSUBMSK      S3C2410_IRQREG(0x01C)
  25 
  26 #define S3C2416_PRIORITY_MODE1          S3C2410_IRQREG(0x030)
  27 #define S3C2416_PRIORITY_UPDATE1        S3C2410_IRQREG(0x034)
  28 #define S3C2416_SRCPND2                 S3C2410_IRQREG(0x040)
  29 #define S3C2416_INTMOD2                 S3C2410_IRQREG(0x044)
  30 #define S3C2416_INTMSK2                 S3C2410_IRQREG(0x048)
  31 #define S3C2416_INTPND2                 S3C2410_IRQREG(0x050)
  32 #define S3C2416_INTOFFSET2              S3C2410_IRQREG(0x054)
  33 #define S3C2416_PRIORITY_MODE2          S3C2410_IRQREG(0x070)
  34 #define S3C2416_PRIORITY_UPDATE2        S3C2410_IRQREG(0x074)
  35 
  36 /* mask: 0=enable, 1=disable
  37  * 1 bit EINT, 4=EINT4, 23=EINT23
  38  * EINT0,1,2,3 are not handled here.
  39 */
  40 
  41 #define S3C2410_EINTMASK       S3C2410_EINTREG(0x0A4)
  42 #define S3C2410_EINTPEND       S3C2410_EINTREG(0X0A8)
  43 #define S3C2412_EINTMASK       S3C2410_EINTREG(0x0B4)
  44 #define S3C2412_EINTPEND       S3C2410_EINTREG(0X0B8)
  45 
  46 #define S3C24XX_EINTMASK       S3C24XX_EINTREG(0x0A4)
  47 #define S3C24XX_EINTPEND       S3C24XX_EINTREG(0X0A8)
  48 
  49 #endif /* ___ASM_ARCH_REGS_IRQ_H */
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