root/arch/arm/mach-s3c24xx/sleep.S

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (c) 2004 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2410 Power Manager (Suspend-To-RAM) support
   7  *
   8  * Based on PXA/SA1100 sleep code by:
   9  *      Nicolas Pitre, (c) 2002 Monta Vista Software Inc
  10  *      Cliff Brake, (c) 2001
  11  */
  12 
  13 #include <linux/linkage.h>
  14 #include <linux/serial_s3c.h>
  15 #include <asm/assembler.h>
  16 #include <mach/hardware.h>
  17 #include <mach/map.h>
  18 
  19 #include <mach/regs-gpio.h>
  20 #include <mach/regs-clock.h>
  21 
  22 /*
  23  * S3C24XX_DEBUG_RESUME is dangerous if your bootloader does not
  24  * reset the UART configuration, only enable if you really need this!
  25  */
  26 //#define S3C24XX_DEBUG_RESUME
  27 
  28         .text
  29 
  30         /* sleep magic, to allow the bootloader to check for an valid
  31          * image to resume to. Must be the first word before the
  32          * s3c_cpu_resume entry.
  33         */
  34 
  35         .word   0x2bedf00d
  36 
  37         /* s3c_cpu_resume
  38          *
  39          * resume code entry for bootloader to call
  40         */
  41 
  42 ENTRY(s3c_cpu_resume)
  43         mov     r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
  44         msr     cpsr_c, r0
  45 
  46         @@ load UART to allow us to print the two characters for
  47         @@ resume debug
  48 
  49         mov     r2, #S3C24XX_PA_UART & 0xff000000
  50         orr     r2, r2, #S3C24XX_PA_UART & 0xff000
  51 
  52 #if 0
  53         /* SMDK2440 LED set */
  54         mov     r14, #S3C24XX_PA_GPIO
  55         ldr     r12, [ r14, #0x54 ]
  56         bic     r12, r12, #3<<4
  57         orr     r12, r12, #1<<7
  58         str     r12, [ r14, #0x54 ]
  59 #endif
  60 
  61 #ifdef S3C24XX_DEBUG_RESUME
  62         mov     r3, #'L'
  63         strb    r3, [ r2, #S3C2410_UTXH ]
  64 1001:
  65         ldrb    r14, [ r3, #S3C2410_UTRSTAT ]
  66         tst     r14, #S3C2410_UTRSTAT_TXE
  67         beq     1001b
  68 #endif /* S3C24XX_DEBUG_RESUME */
  69 
  70         b       cpu_resume