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7 #ifndef __ARCH_ARM_MACH_S3C24XX_S3C2412_POWER_H
8 #define __ARCH_ARM_MACH_S3C24XX_S3C2412_POWER_H __FILE__
9
10 #define S3C24XX_PWRREG(x) ((x) + S3C24XX_VA_CLKPWR)
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12 #define S3C2412_PWRMODECON S3C24XX_PWRREG(0x20)
13 #define S3C2412_PWRCFG S3C24XX_PWRREG(0x24)
14
15 #define S3C2412_INFORM0 S3C24XX_PWRREG(0x70)
16 #define S3C2412_INFORM1 S3C24XX_PWRREG(0x74)
17 #define S3C2412_INFORM2 S3C24XX_PWRREG(0x78)
18 #define S3C2412_INFORM3 S3C24XX_PWRREG(0x7C)
19
20 #define S3C2412_PWRCFG_BATF_IRQ (1 << 0)
21 #define S3C2412_PWRCFG_BATF_IGNORE (2 << 0)
22 #define S3C2412_PWRCFG_BATF_SLEEP (3 << 0)
23 #define S3C2412_PWRCFG_BATF_MASK (3 << 0)
24
25 #define S3C2412_PWRCFG_STANDBYWFI_IGNORE (0 << 6)
26 #define S3C2412_PWRCFG_STANDBYWFI_IDLE (1 << 6)
27 #define S3C2412_PWRCFG_STANDBYWFI_STOP (2 << 6)
28 #define S3C2412_PWRCFG_STANDBYWFI_SLEEP (3 << 6)
29 #define S3C2412_PWRCFG_STANDBYWFI_MASK (3 << 6)
30
31 #define S3C2412_PWRCFG_RTC_MASKIRQ (1 << 8)
32 #define S3C2412_PWRCFG_NAND_NORST (1 << 9)
33
34 #endif