This source file includes following definitions.
- pcibios_init_resource
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11 #ifndef _XTENSA_PCI_BRIDGE_H
12 #define _XTENSA_PCI_BRIDGE_H
13
14 struct device_node;
15 struct pci_controller;
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21 extern int pciauto_bus_scan(struct pci_controller *, int);
22
23 struct pci_space {
24 unsigned long start;
25 unsigned long end;
26 unsigned long base;
27 };
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33 struct pci_controller {
34 int index;
35 struct pci_controller *next;
36 struct pci_bus *bus;
37 void *arch_data;
38
39 int first_busno;
40 int last_busno;
41
42 struct pci_ops *ops;
43 volatile unsigned int *cfg_addr;
44 volatile unsigned char *cfg_data;
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49 struct resource io_resource;
50 struct resource mem_resources[3];
51 int mem_resource_count;
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56 struct pci_space io_space;
57 struct pci_space mem_space;
58
59
60 int (*map_irq)(struct pci_dev*, u8, u8);
61
62 };
63
64 static inline void pcibios_init_resource(struct resource *res,
65 unsigned long start, unsigned long end, int flags, char *name)
66 {
67 res->start = start;
68 res->end = end;
69 res->flags = flags;
70 res->name = name;
71 res->parent = NULL;
72 res->sibling = NULL;
73 res->child = NULL;
74 }
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78 int early_read_config_byte(struct pci_controller*, int, int, int, u8*);
79 int early_read_config_word(struct pci_controller*, int, int, int, u16*);
80 int early_read_config_dword(struct pci_controller*, int, int, int, u32*);
81 int early_write_config_byte(struct pci_controller*, int, int, int, u8);
82 int early_write_config_word(struct pci_controller*, int, int, int, u16);
83 int early_write_config_dword(struct pci_controller*, int, int, int, u32);
84
85 #endif