This source file includes following definitions.
- jive_mtdset
- jive_lcm_reset
- jive_pm_suspend
- jive_pm_resume
- jive_map_io
- jive_init_time
- jive_power_off
- jive_machine_init
1
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7
8 #include <linux/kernel.h>
9 #include <linux/types.h>
10 #include <linux/interrupt.h>
11 #include <linux/list.h>
12 #include <linux/timer.h>
13 #include <linux/init.h>
14 #include <linux/gpio.h>
15 #include <linux/gpio/machine.h>
16 #include <linux/syscore_ops.h>
17 #include <linux/serial_core.h>
18 #include <linux/serial_s3c.h>
19 #include <linux/platform_device.h>
20 #include <linux/i2c.h>
21
22 #include <video/ili9320.h>
23
24 #include <linux/spi/spi.h>
25 #include <linux/spi/spi_gpio.h>
26
27 #include <asm/mach/arch.h>
28 #include <asm/mach/map.h>
29 #include <asm/mach/irq.h>
30
31 #include <linux/platform_data/mtd-nand-s3c2410.h>
32 #include <linux/platform_data/i2c-s3c2410.h>
33
34 #include <mach/regs-gpio.h>
35 #include <mach/regs-lcd.h>
36 #include <mach/fb.h>
37 #include <mach/gpio-samsung.h>
38
39 #include <asm/mach-types.h>
40
41 #include <linux/mtd/mtd.h>
42 #include <linux/mtd/rawnand.h>
43 #include <linux/mtd/nand_ecc.h>
44 #include <linux/mtd/partitions.h>
45
46 #include <plat/gpio-cfg.h>
47 #include <plat/devs.h>
48 #include <plat/cpu.h>
49 #include <plat/pm.h>
50 #include <linux/platform_data/usb-s3c2410_udc.h>
51 #include <plat/samsung-time.h>
52
53 #include "common.h"
54 #include "s3c2412-power.h"
55
56 static struct map_desc jive_iodesc[] __initdata = {
57 };
58
59 #define UCON S3C2410_UCON_DEFAULT
60 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
61 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
62
63 static struct s3c2410_uartcfg jive_uartcfgs[] = {
64 [0] = {
65 .hwport = 0,
66 .flags = 0,
67 .ucon = UCON,
68 .ulcon = ULCON,
69 .ufcon = UFCON,
70 },
71 [1] = {
72 .hwport = 1,
73 .flags = 0,
74 .ucon = UCON,
75 .ulcon = ULCON,
76 .ufcon = UFCON,
77 },
78 [2] = {
79 .hwport = 2,
80 .flags = 0,
81 .ucon = UCON,
82 .ulcon = ULCON,
83 .ufcon = UFCON,
84 }
85 };
86
87
88
89
90
91
92
93
94
95
96
97
98 static struct mtd_partition __initdata jive_imageA_nand_part[] = {
99
100 #ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
101
102 {
103 .name = "uboot",
104 .offset = 0,
105 .size = (160 * SZ_1K),
106 .mask_flags = MTD_WRITEABLE,
107 },
108
109
110 {
111 .name = "spare",
112 .offset = (176 * SZ_1K),
113 .size = (16 * SZ_1K),
114 },
115 #endif
116
117
118 {
119 .name = "kernel (ro)",
120 .offset = (192 * SZ_1K),
121 .size = (SZ_2M) - (192 * SZ_1K),
122 .mask_flags = MTD_WRITEABLE,
123 }, {
124 .name = "root (ro)",
125 .offset = (SZ_2M),
126 .size = (20 * SZ_1M),
127 .mask_flags = MTD_WRITEABLE,
128 },
129
130
131 {
132 .name = "yaffs",
133 .offset = (44 * SZ_1M),
134 .size = (20 * SZ_1M),
135 },
136
137
138 {
139 .name = "env",
140 .offset = (160 * SZ_1K),
141 .size = (16 * SZ_1K),
142 },
143
144
145 {
146 .name = "zimage",
147 .offset = (22 * SZ_1M),
148 .size = (2 * SZ_1M) - (192 * SZ_1K),
149 }, {
150 .name = "cramfs",
151 .offset = (24 * SZ_1M) - (192*SZ_1K),
152 .size = (20 * SZ_1M),
153 },
154 };
155
156 static struct mtd_partition __initdata jive_imageB_nand_part[] = {
157
158 #ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
159
160 {
161 .name = "uboot",
162 .offset = 0,
163 .size = (160 * SZ_1K),
164 .mask_flags = MTD_WRITEABLE,
165 },
166
167
168 {
169 .name = "spare",
170 .offset = (176 * SZ_1K),
171 .size = (16 * SZ_1K),
172 },
173 #endif
174
175
176 {
177 .name = "kernel (ro)",
178 .offset = (22 * SZ_1M),
179 .size = (2 * SZ_1M) - (192 * SZ_1K),
180 .mask_flags = MTD_WRITEABLE,
181 },
182 {
183 .name = "root (ro)",
184 .offset = (24 * SZ_1M) - (192 * SZ_1K),
185 .size = (20 * SZ_1M),
186 .mask_flags = MTD_WRITEABLE,
187 },
188
189
190 {
191 .name = "yaffs",
192 .offset = (44 * SZ_1M),
193 .size = (20 * SZ_1M),
194 },
195
196
197 {
198 .name = "env",
199 .offset = (160 * SZ_1K),
200 .size = (16 * SZ_1K),
201 },
202
203
204 {
205 .name = "zimage",
206 .offset = (192 * SZ_1K),
207 .size = (2 * SZ_1M) - (192 * SZ_1K),
208 }, {
209 .name = "cramfs",
210 .offset = (2 * SZ_1M),
211 .size = (20 * SZ_1M),
212 },
213 };
214
215 static struct s3c2410_nand_set __initdata jive_nand_sets[] = {
216 [0] = {
217 .name = "flash",
218 .nr_chips = 1,
219 .nr_partitions = ARRAY_SIZE(jive_imageA_nand_part),
220 .partitions = jive_imageA_nand_part,
221 },
222 };
223
224 static struct s3c2410_platform_nand __initdata jive_nand_info = {
225
226 .tacls = 30,
227 .twrph0 = 55,
228 .twrph1 = 40,
229 .sets = jive_nand_sets,
230 .nr_sets = ARRAY_SIZE(jive_nand_sets),
231 .ecc_mode = NAND_ECC_SOFT,
232 };
233
234 static int __init jive_mtdset(char *options)
235 {
236 struct s3c2410_nand_set *nand = &jive_nand_sets[0];
237 unsigned long set;
238
239 if (options == NULL || options[0] == '\0')
240 return 0;
241
242 if (kstrtoul(options, 10, &set)) {
243 printk(KERN_ERR "failed to parse mtdset=%s\n", options);
244 return 0;
245 }
246
247 switch (set) {
248 case 1:
249 nand->nr_partitions = ARRAY_SIZE(jive_imageB_nand_part);
250 nand->partitions = jive_imageB_nand_part;
251 case 0:
252
253 break;
254 default:
255 printk(KERN_ERR "Unknown mtd set %ld specified,"
256 "using default.", set);
257 }
258
259 return 0;
260 }
261
262
263 __setup("mtdset=", jive_mtdset);
264
265
266
267 #define LCD_XRES (240)
268 #define LCD_YRES (320)
269 #define LCD_LEFT_MARGIN (12)
270 #define LCD_RIGHT_MARGIN (12)
271 #define LCD_LOWER_MARGIN (12)
272 #define LCD_UPPER_MARGIN (12)
273 #define LCD_VSYNC (2)
274 #define LCD_HSYNC (2)
275
276 #define LCD_REFRESH (60)
277
278 #define LCD_HTOT (LCD_HSYNC + LCD_LEFT_MARGIN + LCD_XRES + LCD_RIGHT_MARGIN)
279 #define LCD_VTOT (LCD_VSYNC + LCD_LOWER_MARGIN + LCD_YRES + LCD_UPPER_MARGIN)
280
281 static struct s3c2410fb_display jive_vgg2432a4_display[] = {
282 [0] = {
283 .width = LCD_XRES,
284 .height = LCD_YRES,
285 .xres = LCD_XRES,
286 .yres = LCD_YRES,
287 .left_margin = LCD_LEFT_MARGIN,
288 .right_margin = LCD_RIGHT_MARGIN,
289 .upper_margin = LCD_UPPER_MARGIN,
290 .lower_margin = LCD_LOWER_MARGIN,
291 .hsync_len = LCD_HSYNC,
292 .vsync_len = LCD_VSYNC,
293
294 .pixclock = (1000000000000LL /
295 (LCD_REFRESH * LCD_HTOT * LCD_VTOT)),
296
297 .bpp = 16,
298 .type = (S3C2410_LCDCON1_TFT16BPP |
299 S3C2410_LCDCON1_TFT),
300
301 .lcdcon5 = (S3C2410_LCDCON5_FRM565 |
302 S3C2410_LCDCON5_INVVLINE |
303 S3C2410_LCDCON5_INVVFRAME |
304 S3C2410_LCDCON5_INVVDEN |
305 S3C2410_LCDCON5_PWREN),
306 },
307 };
308
309
310
311 #define S3C2410_GPCCON_MASK(x) (3 << ((x) * 2))
312 #define S3C2410_GPDCON_MASK(x) (3 << ((x) * 2))
313
314 static struct s3c2410fb_mach_info jive_lcd_config = {
315 .displays = jive_vgg2432a4_display,
316 .num_displays = ARRAY_SIZE(jive_vgg2432a4_display),
317 .default_display = 0,
318
319
320
321
322
323 .gpcup = (0xf << 1) | (0x3f << 10),
324
325 .gpccon = (S3C2410_GPC1_VCLK | S3C2410_GPC2_VLINE |
326 S3C2410_GPC3_VFRAME | S3C2410_GPC4_VM |
327 S3C2410_GPC10_VD2 | S3C2410_GPC11_VD3 |
328 S3C2410_GPC12_VD4 | S3C2410_GPC13_VD5 |
329 S3C2410_GPC14_VD6 | S3C2410_GPC15_VD7),
330
331 .gpccon_mask = (S3C2410_GPCCON_MASK(1) | S3C2410_GPCCON_MASK(2) |
332 S3C2410_GPCCON_MASK(3) | S3C2410_GPCCON_MASK(4) |
333 S3C2410_GPCCON_MASK(10) | S3C2410_GPCCON_MASK(11) |
334 S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) |
335 S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)),
336
337 .gpdup = (0x3f << 2) | (0x3f << 10),
338
339 .gpdcon = (S3C2410_GPD2_VD10 | S3C2410_GPD3_VD11 |
340 S3C2410_GPD4_VD12 | S3C2410_GPD5_VD13 |
341 S3C2410_GPD6_VD14 | S3C2410_GPD7_VD15 |
342 S3C2410_GPD10_VD18 | S3C2410_GPD11_VD19 |
343 S3C2410_GPD12_VD20 | S3C2410_GPD13_VD21 |
344 S3C2410_GPD14_VD22 | S3C2410_GPD15_VD23),
345
346 .gpdcon_mask = (S3C2410_GPDCON_MASK(2) | S3C2410_GPDCON_MASK(3) |
347 S3C2410_GPDCON_MASK(4) | S3C2410_GPDCON_MASK(5) |
348 S3C2410_GPDCON_MASK(6) | S3C2410_GPDCON_MASK(7) |
349 S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)|
350 S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)|
351 S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)),
352 };
353
354
355
356 static void jive_lcm_reset(unsigned int set)
357 {
358 printk(KERN_DEBUG "%s(%d)\n", __func__, set);
359
360 gpio_set_value(S3C2410_GPG(13), set);
361 }
362
363 #undef LCD_UPPER_MARGIN
364 #define LCD_UPPER_MARGIN 2
365
366 static struct ili9320_platdata jive_lcm_config = {
367 .hsize = LCD_XRES,
368 .vsize = LCD_YRES,
369
370 .reset = jive_lcm_reset,
371 .suspend = ILI9320_SUSPEND_DEEP,
372
373 .entry_mode = ILI9320_ENTRYMODE_ID(3) | ILI9320_ENTRYMODE_BGR,
374 .display2 = (ILI9320_DISPLAY2_FP(LCD_UPPER_MARGIN) |
375 ILI9320_DISPLAY2_BP(LCD_LOWER_MARGIN)),
376 .display3 = 0x0,
377 .display4 = 0x0,
378 .rgb_if1 = (ILI9320_RGBIF1_RIM_RGB18 |
379 ILI9320_RGBIF1_RM | ILI9320_RGBIF1_CLK_RGBIF),
380 .rgb_if2 = ILI9320_RGBIF2_DPL,
381 .interface2 = 0x0,
382 .interface3 = 0x3,
383 .interface4 = (ILI9320_INTERFACE4_RTNE(16) |
384 ILI9320_INTERFACE4_DIVE(1)),
385 .interface5 = 0x0,
386 .interface6 = 0x0,
387 };
388
389
390
391 static struct spi_gpio_platform_data jive_lcd_spi = {
392 .num_chipselect = 1,
393 };
394
395 static struct platform_device jive_device_lcdspi = {
396 .name = "spi_gpio",
397 .id = 1,
398 .dev.platform_data = &jive_lcd_spi,
399 };
400
401 static struct gpiod_lookup_table jive_lcdspi_gpiod_table = {
402 .dev_id = "spi_gpio",
403 .table = {
404 GPIO_LOOKUP("GPIOG", 8,
405 "sck", GPIO_ACTIVE_HIGH),
406 GPIO_LOOKUP("GPIOB", 8,
407 "mosi", GPIO_ACTIVE_HIGH),
408 GPIO_LOOKUP("GPIOB", 7,
409 "cs", GPIO_ACTIVE_HIGH),
410 { },
411 },
412 };
413
414
415
416 static struct spi_gpio_platform_data jive_wm8750_spi = {
417 .num_chipselect = 1,
418 };
419
420 static struct platform_device jive_device_wm8750 = {
421 .name = "spi_gpio",
422 .id = 2,
423 .dev.platform_data = &jive_wm8750_spi,
424 };
425
426 static struct gpiod_lookup_table jive_wm8750_gpiod_table = {
427 .dev_id = "spi_gpio",
428 .table = {
429 GPIO_LOOKUP("GPIOB", 4,
430 "sck", GPIO_ACTIVE_HIGH),
431 GPIO_LOOKUP("GPIOB", 9,
432 "mosi", GPIO_ACTIVE_HIGH),
433 GPIO_LOOKUP("GPIOH", 10,
434 "cs", GPIO_ACTIVE_HIGH),
435 { },
436 },
437 };
438
439
440
441 static struct spi_board_info __initdata jive_spi_devs[] = {
442 [0] = {
443 .modalias = "VGG2432A4",
444 .bus_num = 1,
445 .chip_select = 0,
446 .mode = SPI_MODE_3,
447 .max_speed_hz = 100000,
448 .platform_data = &jive_lcm_config,
449 }, {
450 .modalias = "WM8750",
451 .bus_num = 2,
452 .chip_select = 0,
453 .mode = SPI_MODE_0,
454 .max_speed_hz = 100000,
455 },
456 };
457
458
459
460 static struct s3c2410_platform_i2c jive_i2c_cfg __initdata = {
461 .frequency = 80 * 1000,
462 .flags = S3C_IICFLG_FILTER,
463 .sda_delay = 2,
464 };
465
466 static struct i2c_board_info jive_i2c_devs[] __initdata = {
467 [0] = {
468 I2C_BOARD_INFO("lis302dl", 0x1c),
469 .irq = IRQ_EINT14,
470 },
471 };
472
473
474
475 static struct platform_device *jive_devices[] __initdata = {
476 &s3c_device_ohci,
477 &s3c_device_rtc,
478 &s3c_device_wdt,
479 &s3c_device_i2c0,
480 &s3c_device_lcd,
481 &jive_device_lcdspi,
482 &jive_device_wm8750,
483 &s3c_device_nand,
484 &s3c_device_usbgadget,
485 &s3c2412_device_dma,
486 };
487
488 static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = {
489 .vbus_pin = S3C2410_GPG(1),
490 };
491
492
493
494 #ifdef CONFIG_PM
495 static int jive_pm_suspend(void)
496 {
497
498
499
500
501 __raw_writel(0x2BED, S3C2412_INFORM0);
502 __raw_writel(__pa_symbol(s3c_cpu_resume), S3C2412_INFORM1);
503
504 return 0;
505 }
506
507 static void jive_pm_resume(void)
508 {
509 __raw_writel(0x0, S3C2412_INFORM0);
510 }
511
512 #else
513 #define jive_pm_suspend NULL
514 #define jive_pm_resume NULL
515 #endif
516
517 static struct syscore_ops jive_pm_syscore_ops = {
518 .suspend = jive_pm_suspend,
519 .resume = jive_pm_resume,
520 };
521
522 static void __init jive_map_io(void)
523 {
524 s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
525 s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
526 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
527 }
528
529 static void __init jive_init_time(void)
530 {
531 s3c2412_init_clocks(12000000);
532 samsung_timer_init();
533 }
534
535 static void jive_power_off(void)
536 {
537 printk(KERN_INFO "powering system down...\n");
538
539 gpio_request_one(S3C2410_GPC(5), GPIOF_OUT_INIT_HIGH, NULL);
540 gpio_free(S3C2410_GPC(5));
541 }
542
543 static void __init jive_machine_init(void)
544 {
545
546
547 register_syscore_ops(&jive_pm_syscore_ops);
548
549
550
551
552
553
554
555 __raw_writel(S3C2412_SLPCON_IN(0) |
556 S3C2412_SLPCON_PULL(1) |
557 S3C2412_SLPCON_HIGH(2) |
558 S3C2412_SLPCON_PULL(3) |
559 S3C2412_SLPCON_PULL(4) |
560 S3C2412_SLPCON_PULL(5) |
561 S3C2412_SLPCON_PULL(6) |
562 S3C2412_SLPCON_HIGH(7) |
563 S3C2412_SLPCON_PULL(8) |
564 S3C2412_SLPCON_PULL(9) |
565 S3C2412_SLPCON_PULL(10), S3C2412_GPBSLPCON);
566
567
568
569 __raw_writel(S3C2412_SLPCON_PULL(0) |
570 S3C2412_SLPCON_PULL(1) |
571 S3C2412_SLPCON_PULL(2) |
572 S3C2412_SLPCON_PULL(3) |
573 S3C2412_SLPCON_PULL(4) |
574 S3C2412_SLPCON_PULL(5) |
575 S3C2412_SLPCON_LOW(6) |
576 S3C2412_SLPCON_PULL(6) |
577 S3C2412_SLPCON_PULL(7) |
578 S3C2412_SLPCON_PULL(8) |
579 S3C2412_SLPCON_PULL(9) |
580 S3C2412_SLPCON_PULL(10) |
581 S3C2412_SLPCON_PULL(11) |
582 S3C2412_SLPCON_PULL(12) |
583 S3C2412_SLPCON_PULL(13) |
584 S3C2412_SLPCON_PULL(14) |
585 S3C2412_SLPCON_PULL(15), S3C2412_GPCSLPCON);
586
587
588
589 __raw_writel(S3C2412_SLPCON_ALL_PULL, S3C2412_GPDSLPCON);
590
591
592
593 __raw_writel(S3C2412_SLPCON_LOW(0) |
594 S3C2412_SLPCON_LOW(1) |
595 S3C2412_SLPCON_LOW(2) |
596 S3C2412_SLPCON_EINT(3) |
597 S3C2412_SLPCON_EINT(4) |
598 S3C2412_SLPCON_EINT(5) |
599 S3C2412_SLPCON_EINT(6) |
600 S3C2412_SLPCON_EINT(7), S3C2412_GPFSLPCON);
601
602
603
604 __raw_writel(S3C2412_SLPCON_IN(0) |
605 S3C2412_SLPCON_IN(1) |
606 S3C2412_SLPCON_IN(2) |
607 S3C2412_SLPCON_IN(3) |
608 S3C2412_SLPCON_IN(4) |
609 S3C2412_SLPCON_IN(5) |
610 S3C2412_SLPCON_IN(6) |
611 S3C2412_SLPCON_IN(7) |
612 S3C2412_SLPCON_PULL(8) |
613 S3C2412_SLPCON_PULL(9) |
614 S3C2412_SLPCON_IN(10) |
615 S3C2412_SLPCON_PULL(11) |
616 S3C2412_SLPCON_PULL(12) |
617 S3C2412_SLPCON_PULL(13) |
618 S3C2412_SLPCON_IN(14) |
619 S3C2412_SLPCON_PULL(15), S3C2412_GPGSLPCON);
620
621
622
623 __raw_writel(S3C2412_SLPCON_PULL(0) |
624 S3C2412_SLPCON_PULL(1) |
625 S3C2412_SLPCON_PULL(2) |
626 S3C2412_SLPCON_PULL(3) |
627 S3C2412_SLPCON_PULL(4) |
628 S3C2412_SLPCON_PULL(5) |
629 S3C2412_SLPCON_PULL(6) |
630 S3C2412_SLPCON_IN(7) |
631 S3C2412_SLPCON_IN(8) |
632 S3C2412_SLPCON_PULL(9) |
633 S3C2412_SLPCON_IN(10), S3C2412_GPHSLPCON);
634
635
636
637 s3c_pm_init();
638
639
640 s3c_nand_set_platdata(&jive_nand_info);
641
642 gpio_request(S3C2410_GPG(13), "lcm reset");
643 gpio_direction_output(S3C2410_GPG(13), 0);
644
645 gpio_request_one(S3C2410_GPB(6), GPIOF_OUT_INIT_LOW, NULL);
646 gpio_free(S3C2410_GPB(6));
647
648
649
650
651 s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
652 S3C2410_MISCCR_USBSUSPND0 |
653 S3C2410_MISCCR_USBSUSPND1, 0x0);
654
655 s3c24xx_udc_set_platdata(&jive_udc_cfg);
656 s3c24xx_fb_set_platdata(&jive_lcd_config);
657
658 spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs));
659
660 s3c_i2c0_set_platdata(&jive_i2c_cfg);
661 i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs));
662
663 pm_power_off = jive_power_off;
664
665 gpiod_add_lookup_table(&jive_lcdspi_gpiod_table);
666 gpiod_add_lookup_table(&jive_wm8750_gpiod_table);
667 platform_add_devices(jive_devices, ARRAY_SIZE(jive_devices));
668 }
669
670 MACHINE_START(JIVE, "JIVE")
671
672 .atag_offset = 0x100,
673
674 .init_irq = s3c2412_init_irq,
675 .map_io = jive_map_io,
676 .init_machine = jive_machine_init,
677 .init_time = jive_init_time,
678 MACHINE_END