root/arch/arm/mach-sunxi/headsmp.S

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright (c) 2018 Chen-Yu Tsai
   4  * Copyright (c) 2018 Bootlin
   5  *
   6  * Chen-Yu Tsai <wens@csie.org>
   7  * Mylène Josserand <mylene.josserand@bootlin.com>
   8  *
   9  * SMP support for sunxi based systems with Cortex A7/A15
  10  *
  11  */
  12 
  13 #include <linux/linkage.h>
  14 #include <asm/assembler.h>
  15 #include <asm/cputype.h>
  16 
  17 ENTRY(sunxi_mc_smp_cluster_cache_enable)
  18         .arch   armv7-a
  19         /*
  20          * Enable cluster-level coherency, in preparation for turning on the MMU.
  21          *
  22          * Also enable regional clock gating and L2 data latency settings for
  23          * Cortex-A15. These settings are from the vendor kernel.
  24          */
  25         mrc     p15, 0, r1, c0, c0, 0
  26         movw    r2, #(ARM_CPU_PART_MASK & 0xffff)
  27         movt    r2, #(ARM_CPU_PART_MASK >> 16)
  28         and     r1, r1, r2
  29         movw    r2, #(ARM_CPU_PART_CORTEX_A15 & 0xffff)
  30         movt    r2, #(ARM_CPU_PART_CORTEX_A15 >> 16)
  31         cmp     r1, r2
  32         bne     not_a15
  33 
  34         /* The following is Cortex-A15 specific */
  35 
  36         /* ACTLR2: Enable CPU regional clock gates */
  37         mrc p15, 1, r1, c15, c0, 4
  38         orr r1, r1, #(0x1 << 31)
  39         mcr p15, 1, r1, c15, c0, 4
  40 
  41         /* L2ACTLR */
  42         mrc p15, 1, r1, c15, c0, 0
  43         /* Enable L2, GIC, and Timer regional clock gates */
  44         orr r1, r1, #(0x1 << 26)
  45         /* Disable clean/evict from being pushed to external */
  46         orr r1, r1, #(0x1<<3)
  47         mcr p15, 1, r1, c15, c0, 0
  48 
  49         /* L2CTRL: L2 data RAM latency */
  50         mrc p15, 1, r1, c9, c0, 2
  51         bic r1, r1, #(0x7 << 0)
  52         orr r1, r1, #(0x3 << 0)
  53         mcr p15, 1, r1, c9, c0, 2
  54 
  55         /* End of Cortex-A15 specific setup */
  56         not_a15:
  57 
  58         /* Get value of sunxi_mc_smp_first_comer */
  59         adr     r1, first
  60         ldr     r0, [r1]
  61         ldr     r0, [r1, r0]
  62 
  63         /* Skip cci_enable_port_for_self if not first comer */
  64         cmp     r0, #0
  65         bxeq    lr
  66         b       cci_enable_port_for_self
  67 
  68         .align 2
  69         first: .word sunxi_mc_smp_first_comer - .
  70 ENDPROC(sunxi_mc_smp_cluster_cache_enable)
  71 
  72 ENTRY(sunxi_mc_smp_secondary_startup)
  73         bl      sunxi_mc_smp_cluster_cache_enable
  74         bl      secure_cntvoff_init
  75         b       secondary_startup
  76 ENDPROC(sunxi_mc_smp_secondary_startup)
  77 
  78 ENTRY(sunxi_mc_smp_resume)
  79         bl      sunxi_mc_smp_cluster_cache_enable
  80         b       cpu_resume
  81 ENDPROC(sunxi_mc_smp_resume)