root/arch/arm/mach-s3c64xx/include/mach/irqs.h

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   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* linux/arch/arm/mach-s3c64xx/include/mach/irqs.h
   3  *
   4  * Copyright 2008 Openmoko, Inc.
   5  * Copyright 2008 Simtec Electronics
   6  *      Ben Dooks <ben@simtec.co.uk>
   7  *      http://armlinux.simtec.co.uk/
   8  *
   9  * S3C64XX - IRQ support
  10  */
  11 
  12 #ifndef __ASM_MACH_S3C64XX_IRQS_H
  13 #define __ASM_MACH_S3C64XX_IRQS_H __FILE__
  14 
  15 /* we keep the first set of CPU IRQs out of the range of
  16  * the ISA space, so that the PC104 has them to itself
  17  * and we don't end up having to do horrible things to the
  18  * standard ISA drivers....
  19  *
  20  * note, since we're using the VICs, our start must be a
  21  * mulitple of 32 to allow the common code to work
  22  */
  23 
  24 #define S3C_IRQ_OFFSET  (32)
  25 
  26 #define S3C_IRQ(x)      ((x) + S3C_IRQ_OFFSET)
  27 
  28 #define IRQ_VIC0_BASE   S3C_IRQ(0)
  29 #define IRQ_VIC1_BASE   S3C_IRQ(32)
  30 
  31 /* VIC based IRQs */
  32 
  33 #define S3C64XX_IRQ_VIC0(x)     (IRQ_VIC0_BASE + (x))
  34 #define S3C64XX_IRQ_VIC1(x)     (IRQ_VIC1_BASE + (x))
  35 
  36 /* VIC0 */
  37 
  38 #define IRQ_EINT0_3             S3C64XX_IRQ_VIC0(0)
  39 #define IRQ_EINT4_11            S3C64XX_IRQ_VIC0(1)
  40 #define IRQ_RTC_TIC             S3C64XX_IRQ_VIC0(2)
  41 #define IRQ_CAMIF_C             S3C64XX_IRQ_VIC0(3)
  42 #define IRQ_CAMIF_P             S3C64XX_IRQ_VIC0(4)
  43 #define IRQ_CAMIF_MC            S3C64XX_IRQ_VIC0(5)
  44 #define IRQ_S3C6410_IIC1        S3C64XX_IRQ_VIC0(5)
  45 #define IRQ_S3C6410_IIS         S3C64XX_IRQ_VIC0(6)
  46 #define IRQ_S3C6400_CAMIF_MP    S3C64XX_IRQ_VIC0(6)
  47 #define IRQ_CAMIF_WE_C          S3C64XX_IRQ_VIC0(7)
  48 #define IRQ_S3C6410_G3D         S3C64XX_IRQ_VIC0(8)
  49 #define IRQ_S3C6400_CAMIF_WE_P  S3C64XX_IRQ_VIC0(8)
  50 #define IRQ_POST0               S3C64XX_IRQ_VIC0(9)
  51 #define IRQ_ROTATOR             S3C64XX_IRQ_VIC0(10)
  52 #define IRQ_2D                  S3C64XX_IRQ_VIC0(11)
  53 #define IRQ_TVENC               S3C64XX_IRQ_VIC0(12)
  54 #define IRQ_SCALER              S3C64XX_IRQ_VIC0(13)
  55 #define IRQ_BATF                S3C64XX_IRQ_VIC0(14)
  56 #define IRQ_JPEG                S3C64XX_IRQ_VIC0(15)
  57 #define IRQ_MFC                 S3C64XX_IRQ_VIC0(16)
  58 #define IRQ_SDMA0               S3C64XX_IRQ_VIC0(17)
  59 #define IRQ_SDMA1               S3C64XX_IRQ_VIC0(18)
  60 #define IRQ_ARM_DMAERR          S3C64XX_IRQ_VIC0(19)
  61 #define IRQ_ARM_DMA             S3C64XX_IRQ_VIC0(20)
  62 #define IRQ_ARM_DMAS            S3C64XX_IRQ_VIC0(21)
  63 #define IRQ_KEYPAD              S3C64XX_IRQ_VIC0(22)
  64 #define IRQ_TIMER0_VIC          S3C64XX_IRQ_VIC0(23)
  65 #define IRQ_TIMER1_VIC          S3C64XX_IRQ_VIC0(24)
  66 #define IRQ_TIMER2_VIC          S3C64XX_IRQ_VIC0(25)
  67 #define IRQ_WDT                 S3C64XX_IRQ_VIC0(26)
  68 #define IRQ_TIMER3_VIC          S3C64XX_IRQ_VIC0(27)
  69 #define IRQ_TIMER4_VIC          S3C64XX_IRQ_VIC0(28)
  70 #define IRQ_LCD_FIFO            S3C64XX_IRQ_VIC0(29)
  71 #define IRQ_LCD_VSYNC           S3C64XX_IRQ_VIC0(30)
  72 #define IRQ_LCD_SYSTEM          S3C64XX_IRQ_VIC0(31)
  73 
  74 /* VIC1 */
  75 
  76 #define IRQ_EINT12_19           S3C64XX_IRQ_VIC1(0)
  77 #define IRQ_EINT20_27           S3C64XX_IRQ_VIC1(1)
  78 #define IRQ_PCM0                S3C64XX_IRQ_VIC1(2)
  79 #define IRQ_PCM1                S3C64XX_IRQ_VIC1(3)
  80 #define IRQ_AC97                S3C64XX_IRQ_VIC1(4)
  81 #define IRQ_UART0               S3C64XX_IRQ_VIC1(5)
  82 #define IRQ_UART1               S3C64XX_IRQ_VIC1(6)
  83 #define IRQ_UART2               S3C64XX_IRQ_VIC1(7)
  84 #define IRQ_UART3               S3C64XX_IRQ_VIC1(8)
  85 #define IRQ_DMA0                S3C64XX_IRQ_VIC1(9)
  86 #define IRQ_DMA1                S3C64XX_IRQ_VIC1(10)
  87 #define IRQ_ONENAND0            S3C64XX_IRQ_VIC1(11)
  88 #define IRQ_ONENAND1            S3C64XX_IRQ_VIC1(12)
  89 #define IRQ_NFC                 S3C64XX_IRQ_VIC1(13)
  90 #define IRQ_CFCON               S3C64XX_IRQ_VIC1(14)
  91 #define IRQ_USBH                S3C64XX_IRQ_VIC1(15)
  92 #define IRQ_SPI0                S3C64XX_IRQ_VIC1(16)
  93 #define IRQ_SPI1                S3C64XX_IRQ_VIC1(17)
  94 #define IRQ_IIC                 S3C64XX_IRQ_VIC1(18)
  95 #define IRQ_HSItx               S3C64XX_IRQ_VIC1(19)
  96 #define IRQ_HSIrx               S3C64XX_IRQ_VIC1(20)
  97 #define IRQ_RESERVED            S3C64XX_IRQ_VIC1(21)
  98 #define IRQ_MSM                 S3C64XX_IRQ_VIC1(22)
  99 #define IRQ_HOSTIF              S3C64XX_IRQ_VIC1(23)
 100 #define IRQ_HSMMC0              S3C64XX_IRQ_VIC1(24)
 101 #define IRQ_HSMMC1              S3C64XX_IRQ_VIC1(25)
 102 #define IRQ_HSMMC2              IRQ_SPI1        /* shared with SPI1 */
 103 #define IRQ_OTG                 S3C64XX_IRQ_VIC1(26)
 104 #define IRQ_IRDA                S3C64XX_IRQ_VIC1(27)
 105 #define IRQ_RTC_ALARM           S3C64XX_IRQ_VIC1(28)
 106 #define IRQ_SEC                 S3C64XX_IRQ_VIC1(29)
 107 #define IRQ_PENDN               S3C64XX_IRQ_VIC1(30)
 108 #define IRQ_TC                  IRQ_PENDN
 109 #define IRQ_ADC                 S3C64XX_IRQ_VIC1(31)
 110 
 111 /* compatibility for device defines */
 112 
 113 #define IRQ_IIC1                IRQ_S3C6410_IIC1
 114 
 115 /* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series
 116  * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE
 117  * which we place after the pair of VICs. */
 118 
 119 #define S3C_IRQ_EINT_BASE       S3C_IRQ(64+5)
 120 
 121 #define S3C_EINT(x)             ((x) + S3C_IRQ_EINT_BASE)
 122 #define IRQ_EINT(x)             S3C_EINT(x)
 123 #define IRQ_EINT_BIT(x)         ((x) - S3C_EINT(0))
 124 
 125 /* Next the external interrupt groups. These are similar to the IRQ_EINT(x)
 126  * that they are sourced from the GPIO pins but with a different scheme for
 127  * priority and source indication.
 128  *
 129  * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO
 130  * interrupts, but for historical reasons they are kept apart from these
 131  * next interrupts.
 132  *
 133  * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the
 134  * machine specific support files.
 135  */
 136 
 137 #define IRQ_EINT_GROUP1_NR      (15)
 138 #define IRQ_EINT_GROUP2_NR      (8)
 139 #define IRQ_EINT_GROUP3_NR      (5)
 140 #define IRQ_EINT_GROUP4_NR      (14)
 141 #define IRQ_EINT_GROUP5_NR      (7)
 142 #define IRQ_EINT_GROUP6_NR      (10)
 143 #define IRQ_EINT_GROUP7_NR      (16)
 144 #define IRQ_EINT_GROUP8_NR      (15)
 145 #define IRQ_EINT_GROUP9_NR      (9)
 146 
 147 #define IRQ_EINT_GROUP_BASE     S3C_EINT(28)
 148 #define IRQ_EINT_GROUP1_BASE    (IRQ_EINT_GROUP_BASE + 0x00)
 149 #define IRQ_EINT_GROUP2_BASE    (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR)
 150 #define IRQ_EINT_GROUP3_BASE    (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR)
 151 #define IRQ_EINT_GROUP4_BASE    (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR)
 152 #define IRQ_EINT_GROUP5_BASE    (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR)
 153 #define IRQ_EINT_GROUP6_BASE    (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR)
 154 #define IRQ_EINT_GROUP7_BASE    (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR)
 155 #define IRQ_EINT_GROUP8_BASE    (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR)
 156 #define IRQ_EINT_GROUP9_BASE    (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR)
 157 
 158 #define IRQ_EINT_GROUP(group, no)       (IRQ_EINT_GROUP##group##_BASE + (no))
 159 
 160 /* Some boards have their own IRQs behind this */
 161 #define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1)
 162 
 163 /* Set the default nr_irqs, boards can override if necessary */
 164 #define S3C64XX_NR_IRQS IRQ_BOARD_START
 165 
 166 /* Compatibility */
 167 
 168 #define IRQ_ONENAND     IRQ_ONENAND0
 169 #define IRQ_I2S0        IRQ_S3C6410_IIS
 170 
 171 #endif /* __ASM_MACH_S3C64XX_IRQS_H */
 172
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