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   8 #define AT91_DBGU_SR            (0x14)  
   9 #define AT91_DBGU_THR           (0x1c)  
  10 #define AT91_DBGU_TXRDY         (1 << 1)        
  11 #define AT91_DBGU_TXEMPTY       (1 << 9)        
  12 
  13         .macro  addruart, rp, rv, tmp
  14         ldr     \rp, =CONFIG_DEBUG_UART_PHYS            @ System peripherals (phys address)
  15         ldr     \rv, =CONFIG_DEBUG_UART_VIRT            @ System peripherals (virt address)
  16         .endm
  17 
  18         .macro  senduart,rd,rx
  19         strb    \rd, [\rx, #(AT91_DBGU_THR)]            @ Write to Transmitter Holding Register
  20         .endm
  21 
  22         .macro  waituart,rd,rx
  23 1001:   ldr     \rd, [\rx, #(AT91_DBGU_SR)]             @ Read Status Register
  24         tst     \rd, #AT91_DBGU_TXRDY                   @ DBGU_TXRDY = 1 when ready to transmit
  25         beq     1001b
  26         .endm
  27 
  28         .macro  busyuart,rd,rx
  29 1001:   ldr     \rd, [\rx, #(AT91_DBGU_SR)]             @ Read Status Register
  30         tst     \rd, #AT91_DBGU_TXEMPTY                 @ DBGU_TXEMPTY = 1 when transmission complete
  31         beq     1001b
  32         .endm
  33