root/arch/arm/include/debug/renesas-scif.S

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Renesas SCIF(A) debugging macro include header
   4  *
   5  * Based on r8a7790.S
   6  *
   7  * Copyright (C) 2012-2013 Renesas Electronics Corporation
   8  * Copyright (C) 1994-1999 Russell King
   9  */
  10 
  11 #define SCIF_PHYS       CONFIG_DEBUG_UART_PHYS
  12 #define SCIF_VIRT       ((SCIF_PHYS & 0x00ffffff) | 0xfd000000)
  13 
  14 #if defined(CONFIG_DEBUG_R7S9210_SCIF2) || defined(CONFIG_DEBUG_R7S9210_SCIF4)
  15 /* RZ/A2 SCIFA */
  16 #define FTDR            0x06
  17 #define FSR             0x08
  18 #elif CONFIG_DEBUG_UART_PHYS < 0xe6e00000
  19 /* SCIFA */
  20 #define FTDR            0x20
  21 #define FSR             0x14
  22 #else
  23 /* SCIF */
  24 #define FTDR            0x0c
  25 #define FSR             0x10
  26 #endif
  27 
  28 #define TDFE    (1 << 5)
  29 #define TEND    (1 << 6)
  30 
  31         .macro  addruart, rp, rv, tmp
  32         ldr     \rp, =SCIF_PHYS
  33         ldr     \rv, =SCIF_VIRT
  34         .endm
  35 
  36         .macro  waituart, rd, rx
  37 1001:   ldrh    \rd, [\rx, #FSR]
  38         tst     \rd, #TDFE
  39         beq     1001b
  40         .endm
  41 
  42         .macro  senduart, rd, rx
  43         strb    \rd, [\rx, #FTDR]
  44         ldrh    \rd, [\rx, #FSR]
  45         bic     \rd, \rd, #TEND
  46         strh    \rd, [\rx, #FSR]
  47         .endm
  48 
  49         .macro  busyuart, rd, rx
  50 1001:   ldrh    \rd, [\rx, #FSR]
  51         tst     \rd, #TEND
  52         beq     1001b
  53         .endm