1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * arch/arm/include/asm/pgtable-2level.h
4 *
5 * Copyright (C) 1995-2002 Russell King
6 */
7 #ifndef _ASM_PGTABLE_2LEVEL_H
8 #define _ASM_PGTABLE_2LEVEL_H
9
10 #define __PAGETABLE_PMD_FOLDED 1
11
12 /*
13 * Hardware-wise, we have a two level page table structure, where the first
14 * level has 4096 entries, and the second level has 256 entries. Each entry
15 * is one 32-bit word. Most of the bits in the second level entry are used
16 * by hardware, and there aren't any "accessed" and "dirty" bits.
17 *
18 * Linux on the other hand has a three level page table structure, which can
19 * be wrapped to fit a two level page table structure easily - using the PGD
20 * and PTE only. However, Linux also expects one "PTE" table per page, and
21 * at least a "dirty" bit.
22 *
23 * Therefore, we tweak the implementation slightly - we tell Linux that we
24 * have 2048 entries in the first level, each of which is 8 bytes (iow, two
25 * hardware pointers to the second level.) The second level contains two
26 * hardware PTE tables arranged contiguously, preceded by Linux versions
27 * which contain the state information Linux needs. We, therefore, end up
28 * with 512 entries in the "PTE" level.
29 *
30 * This leads to the page tables having the following layout:
31 *
32 * pgd pte
33 * | |
34 * +--------+
35 * | | +------------+ +0
36 * +- - - - + | Linux pt 0 |
37 * | | +------------+ +1024
38 * +--------+ +0 | Linux pt 1 |
39 * | |-----> +------------+ +2048
40 * +- - - - + +4 | h/w pt 0 |
41 * | |-----> +------------+ +3072
42 * +--------+ +8 | h/w pt 1 |
43 * | | +------------+ +4096
44 *
45 * See L_PTE_xxx below for definitions of bits in the "Linux pt", and
46 * PTE_xxx for definitions of bits appearing in the "h/w pt".
47 *
48 * PMD_xxx definitions refer to bits in the first level page table.
49 *
50 * The "dirty" bit is emulated by only granting hardware write permission
51 * iff the page is marked "writable" and "dirty" in the Linux PTE. This
52 * means that a write to a clean page will cause a permission fault, and
53 * the Linux MM layer will mark the page dirty via handle_pte_fault().
54 * For the hardware to notice the permission change, the TLB entry must
55 * be flushed, and ptep_set_access_flags() does that for us.
56 *
57 * The "accessed" or "young" bit is emulated by a similar method; we only
58 * allow accesses to the page if the "young" bit is set. Accesses to the
59 * page will cause a fault, and handle_pte_fault() will set the young bit
60 * for us as long as the page is marked present in the corresponding Linux
61 * PTE entry. Again, ptep_set_access_flags() will ensure that the TLB is
62 * up to date.
63 *
64 * However, when the "young" bit is cleared, we deny access to the page
65 * by clearing the hardware PTE. Currently Linux does not flush the TLB
66 * for us in this case, which means the TLB will retain the transation
67 * until either the TLB entry is evicted under pressure, or a context
68 * switch which changes the user space mapping occurs.
69 */
70 #define PTRS_PER_PTE 512
71 #define PTRS_PER_PMD 1
72 #define PTRS_PER_PGD 2048
73
74 #define PTE_HWTABLE_PTRS (PTRS_PER_PTE)
75 #define PTE_HWTABLE_OFF (PTE_HWTABLE_PTRS * sizeof(pte_t))
76 #define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u32))
77
78 /*
79 * PMD_SHIFT determines the size of the area a second-level page table can map
80 * PGDIR_SHIFT determines what a third-level page table entry can map
81 */
82 #define PMD_SHIFT 21
83 #define PGDIR_SHIFT 21
84
85 #define PMD_SIZE (1UL << PMD_SHIFT)
86 #define PMD_MASK (~(PMD_SIZE-1))
87 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
88 #define PGDIR_MASK (~(PGDIR_SIZE-1))
89
90 /*
91 * section address mask and size definitions.
92 */
93 #define SECTION_SHIFT 20
94 #define SECTION_SIZE (1UL << SECTION_SHIFT)
95 #define SECTION_MASK (~(SECTION_SIZE-1))
96
97 /*
98 * ARMv6 supersection address mask and size definitions.
99 */
100 #define SUPERSECTION_SHIFT 24
101 #define SUPERSECTION_SIZE (1UL << SUPERSECTION_SHIFT)
102 #define SUPERSECTION_MASK (~(SUPERSECTION_SIZE-1))
103
104 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
105
106 /*
107 * "Linux" PTE definitions.
108 *
109 * We keep two sets of PTEs - the hardware and the linux version.
110 * This allows greater flexibility in the way we map the Linux bits
111 * onto the hardware tables, and allows us to have YOUNG and DIRTY
112 * bits.
113 *
114 * The PTE table pointer refers to the hardware entries; the "Linux"
115 * entries are stored 1024 bytes below.
116 */
117 #define L_PTE_VALID (_AT(pteval_t, 1) << 0) /* Valid */
118 #define L_PTE_PRESENT (_AT(pteval_t, 1) << 0)
119 #define L_PTE_YOUNG (_AT(pteval_t, 1) << 1)
120 #define L_PTE_DIRTY (_AT(pteval_t, 1) << 6)
121 #define L_PTE_RDONLY (_AT(pteval_t, 1) << 7)
122 #define L_PTE_USER (_AT(pteval_t, 1) << 8)
123 #define L_PTE_XN (_AT(pteval_t, 1) << 9)
124 #define L_PTE_SHARED (_AT(pteval_t, 1) << 10) /* shared(v6), coherent(xsc3) */
125 #define L_PTE_NONE (_AT(pteval_t, 1) << 11)
126
127 /*
128 * These are the memory types, defined to be compatible with
129 * pre-ARMv6 CPUs cacheable and bufferable bits: n/a,n/a,C,B
130 * ARMv6+ without TEX remapping, they are a table index.
131 * ARMv6+ with TEX remapping, they correspond to n/a,TEX(0),C,B
132 *
133 * MT type Pre-ARMv6 ARMv6+ type / cacheable status
134 * UNCACHED Uncached Strongly ordered
135 * BUFFERABLE Bufferable Normal memory / non-cacheable
136 * WRITETHROUGH Writethrough Normal memory / write through
137 * WRITEBACK Writeback Normal memory / write back, read alloc
138 * MINICACHE Minicache N/A
139 * WRITEALLOC Writeback Normal memory / write back, write alloc
140 * DEV_SHARED Uncached Device memory (shared)
141 * DEV_NONSHARED Uncached Device memory (non-shared)
142 * DEV_WC Bufferable Normal memory / non-cacheable
143 * DEV_CACHED Writeback Normal memory / write back, read alloc
144 * VECTORS Variable Normal memory / variable
145 *
146 * All normal memory mappings have the following properties:
147 * - reads can be repeated with no side effects
148 * - repeated reads return the last value written
149 * - reads can fetch additional locations without side effects
150 * - writes can be repeated (in certain cases) with no side effects
151 * - writes can be merged before accessing the target
152 * - unaligned accesses can be supported
153 *
154 * All device mappings have the following properties:
155 * - no access speculation
156 * - no repetition (eg, on return from an exception)
157 * - number, order and size of accesses are maintained
158 * - unaligned accesses are "unpredictable"
159 */
160 #define L_PTE_MT_UNCACHED (_AT(pteval_t, 0x00) << 2) /* 0000 */
161 #define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 0x01) << 2) /* 0001 */
162 #define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 0x02) << 2) /* 0010 */
163 #define L_PTE_MT_WRITEBACK (_AT(pteval_t, 0x03) << 2) /* 0011 */
164 #define L_PTE_MT_MINICACHE (_AT(pteval_t, 0x06) << 2) /* 0110 (sa1100, xscale) */
165 #define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 0x07) << 2) /* 0111 */
166 #define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */
167 #define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */
168 #define L_PTE_MT_DEV_WC (_AT(pteval_t, 0x09) << 2) /* 1001 */
169 #define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 0x0b) << 2) /* 1011 */
170 #define L_PTE_MT_VECTORS (_AT(pteval_t, 0x0f) << 2) /* 1111 */
171 #define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2)
172
173 #ifndef __ASSEMBLY__
174
175 /*
176 * The "pud_xxx()" functions here are trivial when the pmd is folded into
177 * the pud: the pud entry is never bad, always exists, and can't be set or
178 * cleared.
179 */
180 #define pud_none(pud) (0)
181 #define pud_bad(pud) (0)
182 #define pud_present(pud) (1)
183 #define pud_clear(pudp) do { } while (0)
184 #define set_pud(pud,pudp) do { } while (0)
185
186 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
187 {
188 return (pmd_t *)pud;
189 }
190
191 #define pmd_large(pmd) (pmd_val(pmd) & 2)
192 #define pmd_bad(pmd) (pmd_val(pmd) & 2)
193 #define pmd_present(pmd) (pmd_val(pmd))
194
195 #define copy_pmd(pmdpd,pmdps) \
196 do { \
197 pmdpd[0] = pmdps[0]; \
198 pmdpd[1] = pmdps[1]; \
199 flush_pmd_entry(pmdpd); \
200 } while (0)
201
202 #define pmd_clear(pmdp) \
203 do { \
204 pmdp[0] = __pmd(0); \
205 pmdp[1] = __pmd(0); \
206 clean_pmd_entry(pmdp); \
207 } while (0)
208
209 /* we don't need complex calculations here as the pmd is folded into the pgd */
210 #define pmd_addr_end(addr,end) (end)
211
212 #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext)
213 #define pte_special(pte) (0)
214 static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
215
216 /*
217 * We don't have huge page support for short descriptors, for the moment
218 * define empty stubs for use by pin_page_for_write.
219 */
220 #define pmd_hugewillfault(pmd) (0)
221 #define pmd_thp_or_huge(pmd) (0)
222
223 #endif /* __ASSEMBLY__ */
224
225 #endif /* _ASM_PGTABLE_2LEVEL_H */