root/arch/arm/include/asm/cti.h

DEFINITIONS

1. cti_init
2. cti_map_trigger
3. cti_enable
4. cti_disable
5. cti_irq_ack
6. cti_unlock
7. cti_lock

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __ASMARM_CTI_H
   3 #define __ASMARM_CTI_H
   4 
   5 #include        <asm/io.h>
   6 #include        <asm/hardware/coresight.h>
   7 
   8 /* The registers' definition is from section 3.2 of
   9  * Embedded Cross Trigger Revision: r0p0
  10  */
  11 #define         CTICONTROL              0x000
  12 #define         CTISTATUS               0x004
  13 #define         CTILOCK                 0x008
  14 #define         CTIPROTECTION           0x00C
  15 #define         CTIINTACK               0x010
  16 #define         CTIAPPSET               0x014
  17 #define         CTIAPPCLEAR             0x018
  18 #define         CTIAPPPULSE             0x01c
  19 #define         CTIINEN                 0x020
  20 #define         CTIOUTEN                0x0A0
  21 #define         CTITRIGINSTATUS         0x130
  22 #define         CTITRIGOUTSTATUS        0x134
  23 #define         CTICHINSTATUS           0x138
  24 #define         CTICHOUTSTATUS          0x13c
  25 #define         CTIPERIPHID0            0xFE0
  26 #define         CTIPERIPHID1            0xFE4
  27 #define         CTIPERIPHID2            0xFE8
  28 #define         CTIPERIPHID3            0xFEC
  29 #define         CTIPCELLID0             0xFF0
  30 #define         CTIPCELLID1             0xFF4
  31 #define         CTIPCELLID2             0xFF8
  32 #define         CTIPCELLID3             0xFFC
  33 
  34 /* The below are from section 3.6.4 of
  35  * CoreSight v1.0 Architecture Specification
  36  */
  37 #define         LOCKACCESS              0xFB0
  38 #define         LOCKSTATUS              0xFB4
  39 
  40 /**
  41  * struct cti - cross trigger interface struct
  42  * @base: mapped virtual address for the cti base
  43  * @irq: irq number for the cti
  44  * @trig_out_for_irq: triger out number which will cause
  45  *      the @irq happen
  46  *
  47  * cti struct used to operate cti registers.
  48  */
  49 struct cti {
  50         void __iomem *base;
  51         int irq;
  52         int trig_out_for_irq;
  53 };
  54 
  55 /**
  56  * cti_init - initialize the cti instance
  57  * @cti: cti instance
  58  * @base: mapped virtual address for the cti base
  59  * @irq: irq number for the cti
  60  * @trig_out: triger out number which will cause
  61  *      the @irq happen
  62  *
  63  * called by machine code to pass the board dependent
  64  * @base, @irq and @trig_out to cti.
  65  */
  66 static inline void cti_init(struct cti *cti,
  67         void __iomem *base, int irq, int trig_out)
  68 {
  69         cti->base = base;
  70         cti->irq  = irq;
  71         cti->trig_out_for_irq = trig_out;
  72 }
  73 
  74 /**
  75  * cti_map_trigger - use the @chan to map @trig_in to @trig_out
  76  * @cti: cti instance
  77  * @trig_in: trigger in number
  78  * @trig_out: trigger out number
  79  * @channel: channel number
  80  *
  81  * This function maps one trigger in of @trig_in to one trigger
  82  * out of @trig_out using the channel @chan.
  83  */
  84 static inline void cti_map_trigger(struct cti *cti,
  85         int trig_in, int trig_out, int chan)
  86 {
  87         void __iomem *base = cti->base;
  88         unsigned long val;
  89 
  90         val = __raw_readl(base + CTIINEN + trig_in * 4);
  91         val |= BIT(chan);
  92         __raw_writel(val, base + CTIINEN + trig_in * 4);
  93 
  94         val = __raw_readl(base + CTIOUTEN + trig_out * 4);
  95         val |= BIT(chan);
  96         __raw_writel(val, base + CTIOUTEN + trig_out * 4);
  97 }
  98 
  99 /**
 100  * cti_enable - enable the cti module
 101  * @cti: cti instance
 102  *
 103  * enable the cti module
 104  */
 105 static inline void cti_enable(struct cti *cti)
 106 {
 107         __raw_writel(0x1, cti->base + CTICONTROL);
 108 }
 109 
 110 /**
 111  * cti_disable - disable the cti module
 112  * @cti: cti instance
 113  *
 114  * enable the cti module
 115  */
 116 static inline void cti_disable(struct cti *cti)
 117 {
 118         __raw_writel(0, cti->base + CTICONTROL);
 119 }
 120 
 121 /**
 122  * cti_irq_ack - clear the cti irq
 123  * @cti: cti instance
 124  *
 125  * clear the cti irq
 126  */
 127 static inline void cti_irq_ack(struct cti *cti)
 128 {
 129         void __iomem *base = cti->base;
 130         unsigned long val;
 131 
 132         val = __raw_readl(base + CTIINTACK);
 133         val |= BIT(cti->trig_out_for_irq);
 134         __raw_writel(val, base + CTIINTACK);
 135 }
 136 
 137 /**
 138  * cti_unlock - unlock cti module
 139  * @cti: cti instance
 140  *
 141  * unlock the cti module, or else any writes to the cti
 142  * module is not allowed.
 143  */
 144 static inline void cti_unlock(struct cti *cti)
 145 {
 146         __raw_writel(CS_LAR_KEY, cti->base + LOCKACCESS);
 147 }
 148 
 149 /**
 150  * cti_lock - lock cti module
 151  * @cti: cti instance
 152  *
 153  * lock the cti module, so any writes to the cti
 154  * module will be not allowed.
 155  */
 156 static inline void cti_lock(struct cti *cti)
 157 {
 158         __raw_writel(~CS_LAR_KEY, cti->base + LOCKACCESS);
 159 }
 160 #endif