root/arch/arm/include/asm/pgtable-3level-hwdef.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * arch/arm/include/asm/pgtable-3level-hwdef.h
   4  *
   5  * Copyright (C) 2011 ARM Ltd.
   6  * Author: Catalin Marinas <catalin.marinas@arm.com>
   7  */
   8 #ifndef _ASM_PGTABLE_3LEVEL_HWDEF_H
   9 #define _ASM_PGTABLE_3LEVEL_HWDEF_H
  10 
  11 /*
  12  * Hardware page table definitions.
  13  *
  14  * + Level 1/2 descriptor
  15  *   - common
  16  */
  17 #define PMD_TYPE_MASK           (_AT(pmdval_t, 3) << 0)
  18 #define PMD_TYPE_FAULT          (_AT(pmdval_t, 0) << 0)
  19 #define PMD_TYPE_TABLE          (_AT(pmdval_t, 3) << 0)
  20 #define PMD_TYPE_SECT           (_AT(pmdval_t, 1) << 0)
  21 #define PMD_TABLE_BIT           (_AT(pmdval_t, 1) << 1)
  22 #define PMD_BIT4                (_AT(pmdval_t, 0))
  23 #define PMD_DOMAIN(x)           (_AT(pmdval_t, 0))
  24 #define PMD_APTABLE_SHIFT       (61)
  25 #define PMD_APTABLE             (_AT(pgdval_t, 3) << PGD_APTABLE_SHIFT)
  26 #define PMD_PXNTABLE            (_AT(pgdval_t, 1) << 59)
  27 
  28 /*
  29  *   - section
  30  */
  31 #define PMD_SECT_BUFFERABLE     (_AT(pmdval_t, 1) << 2)
  32 #define PMD_SECT_CACHEABLE      (_AT(pmdval_t, 1) << 3)
  33 #define PMD_SECT_USER           (_AT(pmdval_t, 1) << 6)         /* AP[1] */
  34 #define PMD_SECT_AP2            (_AT(pmdval_t, 1) << 7)         /* read only */
  35 #define PMD_SECT_S              (_AT(pmdval_t, 3) << 8)
  36 #define PMD_SECT_AF             (_AT(pmdval_t, 1) << 10)
  37 #define PMD_SECT_nG             (_AT(pmdval_t, 1) << 11)
  38 #define PMD_SECT_PXN            (_AT(pmdval_t, 1) << 53)
  39 #define PMD_SECT_XN             (_AT(pmdval_t, 1) << 54)
  40 #define PMD_SECT_AP_WRITE       (_AT(pmdval_t, 0))
  41 #define PMD_SECT_AP_READ        (_AT(pmdval_t, 0))
  42 #define PMD_SECT_AP1            (_AT(pmdval_t, 1) << 6)
  43 #define PMD_SECT_TEX(x)         (_AT(pmdval_t, 0))
  44 
  45 /*
  46  * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
  47  */
  48 #define PMD_SECT_UNCACHED       (_AT(pmdval_t, 0) << 2) /* strongly ordered */
  49 #define PMD_SECT_BUFFERED       (_AT(pmdval_t, 1) << 2) /* normal non-cacheable */
  50 #define PMD_SECT_WT             (_AT(pmdval_t, 2) << 2) /* normal inner write-through */
  51 #define PMD_SECT_WB             (_AT(pmdval_t, 3) << 2) /* normal inner write-back */
  52 #define PMD_SECT_WBWA           (_AT(pmdval_t, 7) << 2) /* normal inner write-alloc */
  53 #define PMD_SECT_CACHE_MASK     (_AT(pmdval_t, 7) << 2)
  54 
  55 /*
  56  * + Level 3 descriptor (PTE)
  57  */
  58 #define PTE_TYPE_MASK           (_AT(pteval_t, 3) << 0)
  59 #define PTE_TYPE_FAULT          (_AT(pteval_t, 0) << 0)
  60 #define PTE_TYPE_PAGE           (_AT(pteval_t, 3) << 0)
  61 #define PTE_TABLE_BIT           (_AT(pteval_t, 1) << 1)
  62 #define PTE_BUFFERABLE          (_AT(pteval_t, 1) << 2)         /* AttrIndx[0] */
  63 #define PTE_CACHEABLE           (_AT(pteval_t, 1) << 3)         /* AttrIndx[1] */
  64 #define PTE_AP2                 (_AT(pteval_t, 1) << 7)         /* AP[2] */
  65 #define PTE_EXT_SHARED          (_AT(pteval_t, 3) << 8)         /* SH[1:0], inner shareable */
  66 #define PTE_EXT_AF              (_AT(pteval_t, 1) << 10)        /* Access Flag */
  67 #define PTE_EXT_NG              (_AT(pteval_t, 1) << 11)        /* nG */
  68 #define PTE_EXT_PXN             (_AT(pteval_t, 1) << 53)        /* PXN */
  69 #define PTE_EXT_XN              (_AT(pteval_t, 1) << 54)        /* XN */
  70 
  71 /*
  72  * 40-bit physical address supported.
  73  */
  74 #define PHYS_MASK_SHIFT         (40)
  75 #define PHYS_MASK               ((1ULL << PHYS_MASK_SHIFT) - 1)
  76 
  77 /*
  78  * TTBR0/TTBR1 split (PAGE_OFFSET):
  79  *   0x40000000: T0SZ = 2, T1SZ = 0 (not used)
  80  *   0x80000000: T0SZ = 0, T1SZ = 1
  81  *   0xc0000000: T0SZ = 0, T1SZ = 2
  82  *
  83  * Only use this feature if PHYS_OFFSET <= PAGE_OFFSET, otherwise
  84  * booting secondary CPUs would end up using TTBR1 for the identity
  85  * mapping set up in TTBR0.
  86  */
  87 #if defined CONFIG_VMSPLIT_2G
  88 #define TTBR1_OFFSET    16                      /* skip two L1 entries */
  89 #elif defined CONFIG_VMSPLIT_3G
  90 #define TTBR1_OFFSET    (4096 * (1 + 3))        /* only L2, skip pgd + 3*pmd */
  91 #else
  92 #define TTBR1_OFFSET    0
  93 #endif
  94 
  95 #define TTBR1_SIZE      (((PAGE_OFFSET >> 30) - 1) << 16)
  96 
  97 #endif