root/arch/xtensa/variants/test_mmuhifi_c3/include/variant/core.h

INCLUDED FROM

   1 /*
   2  * Xtensa processor core configuration information.
   3  *
   4  * This file is subject to the terms and conditions of version 2.1 of the GNU
   5  * Lesser General Public License as published by the Free Software Foundation.
   6  *
   7  * Copyright (c) 1999-2009 Tensilica Inc.
   8  */
   9 
  10 #ifndef _XTENSA_CORE_CONFIGURATION_H
  11 #define _XTENSA_CORE_CONFIGURATION_H
  12 
  13 
  14 /****************************************************************************
  15             Parameters Useful for Any Code, USER or PRIVILEGED
  16  ****************************************************************************/
  17 
  18 /*
  19  *  Note:  Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
  20  *  configured, and a value of 0 otherwise.  These macros are always defined.
  21  */
  22 
  23 
  24 /*----------------------------------------------------------------------
  25                                 ISA
  26   ----------------------------------------------------------------------*/
  27 
  28 #define XCHAL_HAVE_BE                   0       /* big-endian byte ordering */
  29 #define XCHAL_HAVE_WINDOWED             1       /* windowed registers option */
  30 #define XCHAL_NUM_AREGS                 32      /* num of physical addr regs */
  31 #define XCHAL_NUM_AREGS_LOG2            5       /* log2(XCHAL_NUM_AREGS) */
  32 #define XCHAL_MAX_INSTRUCTION_SIZE      8       /* max instr bytes (3..8) */
  33 #define XCHAL_HAVE_DEBUG                1       /* debug option */
  34 #define XCHAL_HAVE_DENSITY              1       /* 16-bit instructions */
  35 #define XCHAL_HAVE_LOOPS                1       /* zero-overhead loops */
  36 #define XCHAL_HAVE_NSA                  1       /* NSA/NSAU instructions */
  37 #define XCHAL_HAVE_MINMAX               1       /* MIN/MAX instructions */
  38 #define XCHAL_HAVE_SEXT                 1       /* SEXT instruction */
  39 #define XCHAL_HAVE_CLAMPS               1       /* CLAMPS instruction */
  40 #define XCHAL_HAVE_MUL16                1       /* MUL16S/MUL16U instructions */
  41 #define XCHAL_HAVE_MUL32                1       /* MULL instruction */
  42 #define XCHAL_HAVE_MUL32_HIGH           0       /* MULUH/MULSH instructions */
  43 #define XCHAL_HAVE_DIV32                0       /* QUOS/QUOU/REMS/REMU instructions */
  44 #define XCHAL_HAVE_L32R                 1       /* L32R instruction */
  45 #define XCHAL_HAVE_ABSOLUTE_LITERALS    1       /* non-PC-rel (extended) L32R */
  46 #define XCHAL_HAVE_CONST16              0       /* CONST16 instruction */
  47 #define XCHAL_HAVE_ADDX                 1       /* ADDX#/SUBX# instructions */
  48 #define XCHAL_HAVE_WIDE_BRANCHES        0       /* B*.W18 or B*.W15 instr's */
  49 #define XCHAL_HAVE_PREDICTED_BRANCHES   0       /* B[EQ/EQZ/NE/NEZ]T instr's */
  50 #define XCHAL_HAVE_CALL4AND12           1       /* (obsolete option) */
  51 #define XCHAL_HAVE_ABS                  1       /* ABS instruction */
  52 /*#define XCHAL_HAVE_POPC               0*/     /* POPC instruction */
  53 /*#define XCHAL_HAVE_CRC                0*/     /* CRC instruction */
  54 #define XCHAL_HAVE_RELEASE_SYNC         1       /* L32AI/S32RI instructions */
  55 #define XCHAL_HAVE_S32C1I               1       /* S32C1I instruction */
  56 #define XCHAL_HAVE_SPECULATION          0       /* speculation */
  57 #define XCHAL_HAVE_FULL_RESET           1       /* all regs/state reset */
  58 #define XCHAL_NUM_CONTEXTS              1       /* */
  59 #define XCHAL_NUM_MISC_REGS             2       /* num of scratch regs (0..4) */
  60 #define XCHAL_HAVE_TAP_MASTER           0       /* JTAG TAP control instr's */
  61 #define XCHAL_HAVE_PRID                 1       /* processor ID register */
  62 #define XCHAL_HAVE_EXTERN_REGS          1       /* WER/RER instructions */
  63 #define XCHAL_HAVE_MP_INTERRUPTS        1       /* interrupt distributor port */
  64 #define XCHAL_HAVE_MP_RUNSTALL          1       /* core RunStall control port */
  65 #define XCHAL_HAVE_THREADPTR            1       /* THREADPTR register */
  66 #define XCHAL_HAVE_BOOLEANS             1       /* boolean registers */
  67 #define XCHAL_HAVE_CP                   1       /* CPENABLE reg (coprocessor) */
  68 #define XCHAL_CP_MAXCFG                 2       /* max allowed cp id plus one */
  69 #define XCHAL_HAVE_MAC16                0       /* MAC16 package */
  70 #define XCHAL_HAVE_VECTORFPU2005        0       /* vector floating-point pkg */
  71 #define XCHAL_HAVE_FP                   0       /* floating point pkg */
  72 #define XCHAL_HAVE_DFP                  0       /* double precision FP pkg */
  73 #define XCHAL_HAVE_DFP_accel            0       /* double precision FP acceleration pkg */
  74 #define XCHAL_HAVE_VECTRA1              0       /* Vectra I  pkg */
  75 #define XCHAL_HAVE_VECTRALX             0       /* Vectra LX pkg */
  76 #define XCHAL_HAVE_HIFIPRO              0       /* HiFiPro Audio Engine pkg */
  77 #define XCHAL_HAVE_HIFI2                1       /* HiFi2 Audio Engine pkg */
  78 #define XCHAL_HAVE_CONNXD2              0       /* ConnX D2 pkg */
  79 
  80 
  81 /*----------------------------------------------------------------------
  82                                 MISC
  83   ----------------------------------------------------------------------*/
  84 
  85 #define XCHAL_NUM_WRITEBUFFER_ENTRIES   8       /* size of write buffer */
  86 #define XCHAL_INST_FETCH_WIDTH          8       /* instr-fetch width in bytes */
  87 #define XCHAL_DATA_WIDTH                8       /* data width in bytes */
  88 /*  In T1050, applies to selected core load and store instructions (see ISA): */
  89 #define XCHAL_UNALIGNED_LOAD_EXCEPTION  1       /* unaligned loads cause exc. */
  90 #define XCHAL_UNALIGNED_STORE_EXCEPTION 1       /* unaligned stores cause exc.*/
  91 #define XCHAL_UNALIGNED_LOAD_HW         0       /* unaligned loads work in hw */
  92 #define XCHAL_UNALIGNED_STORE_HW        0       /* unaligned stores work in hw*/
  93 
  94 #define XCHAL_SW_VERSION                800000  /* sw version of this header */
  95 
  96 #define XCHAL_CORE_ID                   "test_mmuhifi_c3"       /* alphanum core name
  97                                                    (CoreID) set in the Xtensa
  98                                                    Processor Generator */
  99 
 100 #define XCHAL_CORE_DESCRIPTION          "test_mmuhifi_c3"
 101 #define XCHAL_BUILD_UNIQUE_ID           0x00005A6A      /* 22-bit sw build ID */
 102 
 103 /*
 104  *  These definitions describe the hardware targeted by this software.
 105  */
 106 #define XCHAL_HW_CONFIGID0              0xC1B3CBFE      /* ConfigID hi 32 bits*/
 107 #define XCHAL_HW_CONFIGID1              0x10405A6A      /* ConfigID lo 32 bits*/
 108 #define XCHAL_HW_VERSION_NAME           "LX3.0.0"       /* full version name */
 109 #define XCHAL_HW_VERSION_MAJOR          2300    /* major ver# of targeted hw */
 110 #define XCHAL_HW_VERSION_MINOR          0       /* minor ver# of targeted hw */
 111 #define XCHAL_HW_VERSION                230000  /* major*100+minor */
 112 #define XCHAL_HW_REL_LX3                1
 113 #define XCHAL_HW_REL_LX3_0              1
 114 #define XCHAL_HW_REL_LX3_0_0            1
 115 #define XCHAL_HW_CONFIGID_RELIABLE      1
 116 /*  If software targets a *range* of hardware versions, these are the bounds: */
 117 #define XCHAL_HW_MIN_VERSION_MAJOR      2300    /* major v of earliest tgt hw */
 118 #define XCHAL_HW_MIN_VERSION_MINOR      0       /* minor v of earliest tgt hw */
 119 #define XCHAL_HW_MIN_VERSION            230000  /* earliest targeted hw */
 120 #define XCHAL_HW_MAX_VERSION_MAJOR      2300    /* major v of latest tgt hw */
 121 #define XCHAL_HW_MAX_VERSION_MINOR      0       /* minor v of latest tgt hw */
 122 #define XCHAL_HW_MAX_VERSION            230000  /* latest targeted hw */
 123 
 124 
 125 /*----------------------------------------------------------------------
 126                                 CACHE
 127   ----------------------------------------------------------------------*/
 128 
 129 #define XCHAL_ICACHE_LINESIZE           32      /* I-cache line size in bytes */
 130 #define XCHAL_DCACHE_LINESIZE           32      /* D-cache line size in bytes */
 131 #define XCHAL_ICACHE_LINEWIDTH          5       /* log2(I line size in bytes) */
 132 #define XCHAL_DCACHE_LINEWIDTH          5       /* log2(D line size in bytes) */
 133 
 134 #define XCHAL_ICACHE_SIZE               16384   /* I-cache size in bytes or 0 */
 135 #define XCHAL_DCACHE_SIZE               16384   /* D-cache size in bytes or 0 */
 136 
 137 #define XCHAL_DCACHE_IS_WRITEBACK       1       /* writeback feature */
 138 #define XCHAL_DCACHE_IS_COHERENT        1       /* MP coherence feature */
 139 
 140 
 141 
 142 
 143 /****************************************************************************
 144     Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
 145  ****************************************************************************/
 146 
 147 
 148 #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
 149 
 150 /*----------------------------------------------------------------------
 151                                 CACHE
 152   ----------------------------------------------------------------------*/
 153 
 154 #define XCHAL_HAVE_PIF                  1       /* any outbound PIF present */
 155 
 156 /*  If present, cache size in bytes == (ways * 2^(linewidth + setwidth)).  */
 157 
 158 /*  Number of cache sets in log2(lines per way):  */
 159 #define XCHAL_ICACHE_SETWIDTH           8
 160 #define XCHAL_DCACHE_SETWIDTH           8
 161 
 162 /*  Cache set associativity (number of ways):  */
 163 #define XCHAL_ICACHE_WAYS               2
 164 #define XCHAL_DCACHE_WAYS               2
 165 
 166 /*  Cache features:  */
 167 #define XCHAL_ICACHE_LINE_LOCKABLE      0
 168 #define XCHAL_DCACHE_LINE_LOCKABLE      0
 169 #define XCHAL_ICACHE_ECC_PARITY         0
 170 #define XCHAL_DCACHE_ECC_PARITY         0
 171 
 172 /*  Cache access size in bytes (affects operation of SICW instruction):  */
 173 #define XCHAL_ICACHE_ACCESS_SIZE        8
 174 #define XCHAL_DCACHE_ACCESS_SIZE        8
 175 
 176 /*  Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits):  */
 177 #define XCHAL_CA_BITS                   4
 178 
 179 
 180 /*----------------------------------------------------------------------
 181                         INTERNAL I/D RAM/ROMs and XLMI
 182   ----------------------------------------------------------------------*/
 183 
 184 #define XCHAL_NUM_INSTROM               0       /* number of core instr. ROMs */
 185 #define XCHAL_NUM_INSTRAM               0       /* number of core instr. RAMs */
 186 #define XCHAL_NUM_DATAROM               0       /* number of core data ROMs */
 187 #define XCHAL_NUM_DATARAM               0       /* number of core data RAMs */
 188 #define XCHAL_NUM_URAM                  0       /* number of core unified RAMs*/
 189 #define XCHAL_NUM_XLMI                  0       /* number of core XLMI ports */
 190 
 191 
 192 /*----------------------------------------------------------------------
 193                         INTERRUPTS and TIMERS
 194   ----------------------------------------------------------------------*/
 195 
 196 #define XCHAL_HAVE_INTERRUPTS           1       /* interrupt option */
 197 #define XCHAL_HAVE_HIGHPRI_INTERRUPTS   1       /* med/high-pri. interrupts */
 198 #define XCHAL_HAVE_NMI                  0       /* non-maskable interrupt */
 199 #define XCHAL_HAVE_CCOUNT               1       /* CCOUNT reg. (timer option) */
 200 #define XCHAL_NUM_TIMERS                2       /* number of CCOMPAREn regs */
 201 #define XCHAL_NUM_INTERRUPTS            12      /* number of interrupts */
 202 #define XCHAL_NUM_INTERRUPTS_LOG2       4       /* ceil(log2(NUM_INTERRUPTS)) */
 203 #define XCHAL_NUM_EXTINTERRUPTS         9       /* num of external interrupts */
 204 #define XCHAL_NUM_INTLEVELS             2       /* number of interrupt levels
 205                                                    (not including level zero) */
 206 #define XCHAL_EXCM_LEVEL                1       /* level masked by PS.EXCM */
 207         /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
 208 
 209 /*  Masks of interrupts at each interrupt level:  */
 210 #define XCHAL_INTLEVEL1_MASK            0x00000FFF
 211 #define XCHAL_INTLEVEL2_MASK            0x00000000
 212 #define XCHAL_INTLEVEL3_MASK            0x00000000
 213 #define XCHAL_INTLEVEL4_MASK            0x00000000
 214 #define XCHAL_INTLEVEL5_MASK            0x00000000
 215 #define XCHAL_INTLEVEL6_MASK            0x00000000
 216 #define XCHAL_INTLEVEL7_MASK            0x00000000
 217 
 218 /*  Masks of interrupts at each range 1..n of interrupt levels:  */
 219 #define XCHAL_INTLEVEL1_ANDBELOW_MASK   0x00000FFF
 220 #define XCHAL_INTLEVEL2_ANDBELOW_MASK   0x00000FFF
 221 #define XCHAL_INTLEVEL3_ANDBELOW_MASK   0x00000FFF
 222 #define XCHAL_INTLEVEL4_ANDBELOW_MASK   0x00000FFF
 223 #define XCHAL_INTLEVEL5_ANDBELOW_MASK   0x00000FFF
 224 #define XCHAL_INTLEVEL6_ANDBELOW_MASK   0x00000FFF
 225 #define XCHAL_INTLEVEL7_ANDBELOW_MASK   0x00000FFF
 226 
 227 /*  Level of each interrupt:  */
 228 #define XCHAL_INT0_LEVEL                1
 229 #define XCHAL_INT1_LEVEL                1
 230 #define XCHAL_INT2_LEVEL                1
 231 #define XCHAL_INT3_LEVEL                1
 232 #define XCHAL_INT4_LEVEL                1
 233 #define XCHAL_INT5_LEVEL                1
 234 #define XCHAL_INT6_LEVEL                1
 235 #define XCHAL_INT7_LEVEL                1
 236 #define XCHAL_INT8_LEVEL                1
 237 #define XCHAL_INT9_LEVEL                1
 238 #define XCHAL_INT10_LEVEL               1
 239 #define XCHAL_INT11_LEVEL               1
 240 #define XCHAL_DEBUGLEVEL                2       /* debug interrupt level */
 241 #define XCHAL_HAVE_DEBUG_EXTERN_INT     1       /* OCD external db interrupt */
 242 
 243 /*  Type of each interrupt:  */
 244 #define XCHAL_INT0_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
 245 #define XCHAL_INT1_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
 246 #define XCHAL_INT2_TYPE         XTHAL_INTTYPE_EXTERN_EDGE
 247 #define XCHAL_INT3_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
 248 #define XCHAL_INT4_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
 249 #define XCHAL_INT5_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
 250 #define XCHAL_INT6_TYPE         XTHAL_INTTYPE_TIMER
 251 #define XCHAL_INT7_TYPE         XTHAL_INTTYPE_SOFTWARE
 252 #define XCHAL_INT8_TYPE         XTHAL_INTTYPE_TIMER
 253 #define XCHAL_INT9_TYPE         XTHAL_INTTYPE_EXTERN_LEVEL
 254 #define XCHAL_INT10_TYPE        XTHAL_INTTYPE_EXTERN_LEVEL
 255 #define XCHAL_INT11_TYPE        XTHAL_INTTYPE_EXTERN_LEVEL
 256 
 257 /*  Masks of interrupts for each type of interrupt:  */
 258 #define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFFFF000
 259 #define XCHAL_INTTYPE_MASK_SOFTWARE     0x00000080
 260 #define XCHAL_INTTYPE_MASK_EXTERN_EDGE  0x00000004
 261 #define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x00000E3B
 262 #define XCHAL_INTTYPE_MASK_TIMER        0x00000140
 263 #define XCHAL_INTTYPE_MASK_NMI          0x00000000
 264 #define XCHAL_INTTYPE_MASK_WRITE_ERROR  0x00000000
 265 
 266 /*  Interrupt numbers assigned to specific interrupt sources:  */
 267 #define XCHAL_TIMER0_INTERRUPT          6       /* CCOMPARE0 */
 268 #define XCHAL_TIMER1_INTERRUPT          8       /* CCOMPARE1 */
 269 #define XCHAL_TIMER2_INTERRUPT          XTHAL_TIMER_UNCONFIGURED
 270 #define XCHAL_TIMER3_INTERRUPT          XTHAL_TIMER_UNCONFIGURED
 271 
 272 /*  Interrupt numbers for levels at which only one interrupt is configured:  */
 273 /*  (There are many interrupts each at level(s) 1.)  */
 274 
 275 
 276 /*
 277  *  External interrupt vectors/levels.
 278  *  These macros describe how Xtensa processor interrupt numbers
 279  *  (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
 280  *  map to external BInterrupt<n> pins, for those interrupts
 281  *  configured as external (level-triggered, edge-triggered, or NMI).
 282  *  See the Xtensa processor databook for more details.
 283  */
 284 
 285 /*  Core interrupt numbers mapped to each EXTERNAL interrupt number:  */
 286 #define XCHAL_EXTINT0_NUM               0       /* (intlevel 1) */
 287 #define XCHAL_EXTINT1_NUM               1       /* (intlevel 1) */
 288 #define XCHAL_EXTINT2_NUM               2       /* (intlevel 1) */
 289 #define XCHAL_EXTINT3_NUM               3       /* (intlevel 1) */
 290 #define XCHAL_EXTINT4_NUM               4       /* (intlevel 1) */
 291 #define XCHAL_EXTINT5_NUM               5       /* (intlevel 1) */
 292 #define XCHAL_EXTINT6_NUM               9       /* (intlevel 1) */
 293 #define XCHAL_EXTINT7_NUM               10      /* (intlevel 1) */
 294 #define XCHAL_EXTINT8_NUM               11      /* (intlevel 1) */
 295 
 296 
 297 /*----------------------------------------------------------------------
 298                         EXCEPTIONS and VECTORS
 299   ----------------------------------------------------------------------*/
 300 
 301 #define XCHAL_XEA_VERSION               2       /* Xtensa Exception Architecture
 302                                                    number: 1 == XEA1 (old)
 303                                                            2 == XEA2 (new)
 304                                                            0 == XEAX (extern) */
 305 #define XCHAL_HAVE_XEA1                 0       /* Exception Architecture 1 */
 306 #define XCHAL_HAVE_XEA2                 1       /* Exception Architecture 2 */
 307 #define XCHAL_HAVE_XEAX                 0       /* External Exception Arch. */
 308 #define XCHAL_HAVE_EXCEPTIONS           1       /* exception option */
 309 #define XCHAL_HAVE_MEM_ECC_PARITY       0       /* local memory ECC/parity */
 310 #define XCHAL_HAVE_VECTOR_SELECT        1       /* relocatable vectors */
 311 #define XCHAL_HAVE_VECBASE              1       /* relocatable vectors */
 312 #define XCHAL_VECBASE_RESET_VADDR       0xD0000000  /* VECBASE reset value */
 313 #define XCHAL_VECBASE_RESET_PADDR       0x00000000
 314 #define XCHAL_RESET_VECBASE_OVERLAP     0
 315 
 316 #define XCHAL_RESET_VECTOR0_VADDR       0xFE000000
 317 #define XCHAL_RESET_VECTOR0_PADDR       0xFE000000
 318 #define XCHAL_RESET_VECTOR1_VADDR       0xD8000500
 319 #define XCHAL_RESET_VECTOR1_PADDR       0x00000500
 320 #define XCHAL_RESET_VECTOR_VADDR        0xFE000000
 321 #define XCHAL_RESET_VECTOR_PADDR        0xFE000000
 322 #define XCHAL_USER_VECOFS               0x00000340
 323 #define XCHAL_USER_VECTOR_VADDR         0xD0000340
 324 #define XCHAL_USER_VECTOR_PADDR         0x00000340
 325 #define XCHAL_KERNEL_VECOFS             0x00000300
 326 #define XCHAL_KERNEL_VECTOR_VADDR       0xD0000300
 327 #define XCHAL_KERNEL_VECTOR_PADDR       0x00000300
 328 #define XCHAL_DOUBLEEXC_VECOFS          0x000003C0
 329 #define XCHAL_DOUBLEEXC_VECTOR_VADDR    0xD00003C0
 330 #define XCHAL_DOUBLEEXC_VECTOR_PADDR    0x000003C0
 331 #define XCHAL_WINDOW_OF4_VECOFS         0x00000000
 332 #define XCHAL_WINDOW_UF4_VECOFS         0x00000040
 333 #define XCHAL_WINDOW_OF8_VECOFS         0x00000080
 334 #define XCHAL_WINDOW_UF8_VECOFS         0x000000C0
 335 #define XCHAL_WINDOW_OF12_VECOFS        0x00000100
 336 #define XCHAL_WINDOW_UF12_VECOFS        0x00000140
 337 #define XCHAL_WINDOW_VECTORS_VADDR      0xD0000000
 338 #define XCHAL_WINDOW_VECTORS_PADDR      0x00000000
 339 #define XCHAL_INTLEVEL2_VECOFS          0x00000280
 340 #define XCHAL_INTLEVEL2_VECTOR_VADDR    0xD0000280
 341 #define XCHAL_INTLEVEL2_VECTOR_PADDR    0x00000280
 342 #define XCHAL_DEBUG_VECOFS              XCHAL_INTLEVEL2_VECOFS
 343 #define XCHAL_DEBUG_VECTOR_VADDR        XCHAL_INTLEVEL2_VECTOR_VADDR
 344 #define XCHAL_DEBUG_VECTOR_PADDR        XCHAL_INTLEVEL2_VECTOR_PADDR
 345 
 346 
 347 /*----------------------------------------------------------------------
 348                                 DEBUG
 349   ----------------------------------------------------------------------*/
 350 
 351 #define XCHAL_HAVE_OCD                  1       /* OnChipDebug option */
 352 #define XCHAL_NUM_IBREAK                0       /* number of IBREAKn regs */
 353 #define XCHAL_NUM_DBREAK                0       /* number of DBREAKn regs */
 354 #define XCHAL_HAVE_OCD_DIR_ARRAY        0       /* faster OCD option */
 355 
 356 
 357 /*----------------------------------------------------------------------
 358                                 MMU
 359   ----------------------------------------------------------------------*/
 360 
 361 /*  See core-matmap.h header file for more details.  */
 362 
 363 #define XCHAL_HAVE_TLBS                 1       /* inverse of HAVE_CACHEATTR */
 364 #define XCHAL_HAVE_SPANNING_WAY         0       /* one way maps I+D 4GB vaddr */
 365 #define XCHAL_HAVE_IDENTITY_MAP         0       /* vaddr == paddr always */
 366 #define XCHAL_HAVE_CACHEATTR            0       /* CACHEATTR register present */
 367 #define XCHAL_HAVE_MIMIC_CACHEATTR      0       /* region protection */
 368 #define XCHAL_HAVE_XLT_CACHEATTR        0       /* region prot. w/translation */
 369 #define XCHAL_HAVE_PTP_MMU              1       /* full MMU (with page table
 370                                                    [autorefill] and protection)
 371                                                    usable for an MMU-based OS */
 372 /*  If none of the above last 4 are set, it's a custom TLB configuration.  */
 373 #define XCHAL_ITLB_ARF_ENTRIES_LOG2     2       /* log2(autorefill way size) */
 374 #define XCHAL_DTLB_ARF_ENTRIES_LOG2     2       /* log2(autorefill way size) */
 375 
 376 #define XCHAL_MMU_ASID_BITS             8       /* number of bits in ASIDs */
 377 #define XCHAL_MMU_RINGS                 4       /* number of rings (1..4) */
 378 #define XCHAL_MMU_RING_BITS             2       /* num of bits in RING field */
 379 
 380 #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
 381 
 382 
 383 #endif /* _XTENSA_CORE_CONFIGURATION_H */