root/arch/arm/plat-samsung/include/plat/regs-spi.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (c) 2004 Fetron GmbH
   4  *
   5  * S3C2410 SPI register definition
   6  */
   7 
   8 #ifndef __ASM_ARCH_REGS_SPI_H
   9 #define __ASM_ARCH_REGS_SPI_H
  10 
  11 #define S3C2410_SPI1            (0x20)
  12 #define S3C2412_SPI1            (0x100)
  13 
  14 #define S3C2410_SPCON           (0x00)
  15 
  16 #define S3C2410_SPCON_SMOD_DMA  (2 << 5)        /* DMA mode */
  17 #define S3C2410_SPCON_SMOD_INT  (1 << 5)        /* interrupt mode */
  18 #define S3C2410_SPCON_SMOD_POLL (0 << 5)        /* polling mode */
  19 #define S3C2410_SPCON_ENSCK     (1 << 4)        /* Enable SCK */
  20 #define S3C2410_SPCON_MSTR      (1 << 3)        /* Master:1, Slave:0 select */
  21 #define S3C2410_SPCON_CPOL_HIGH (1 << 2)        /* Clock polarity select */
  22 #define S3C2410_SPCON_CPOL_LOW  (0 << 2)        /* Clock polarity select */
  23 
  24 #define S3C2410_SPCON_CPHA_FMTB (1 << 1)        /* Clock Phase Select */
  25 #define S3C2410_SPCON_CPHA_FMTA (0 << 1)        /* Clock Phase Select */
  26 
  27 #define S3C2410_SPSTA           (0x04)
  28 
  29 #define S3C2410_SPSTA_DCOL      (1 << 2)        /* Data Collision Error */
  30 #define S3C2410_SPSTA_MULD      (1 << 1)        /* Multi Master Error */
  31 #define S3C2410_SPSTA_READY     (1 << 0)        /* Data Tx/Rx ready */
  32 #define S3C2412_SPSTA_READY_ORG (1 << 3)
  33 
  34 #define S3C2410_SPPIN           (0x08)
  35 
  36 #define S3C2410_SPPIN_ENMUL     (1 << 2)        /* Multi Master Error detect */
  37 #define S3C2410_SPPIN_RESERVED  (1 << 1)
  38 #define S3C2410_SPPIN_KEEP      (1 << 0)        /* Master Out keep */
  39 
  40 #define S3C2410_SPPRE           (0x0C)
  41 #define S3C2410_SPTDAT          (0x10)
  42 #define S3C2410_SPRDAT          (0x14)
  43 
  44 #endif /* __ASM_ARCH_REGS_SPI_H */