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6 #ifndef __MACH_BOARD_CNS3XXXH
7 #define __MACH_BOARD_CNS3XXXH
8
9
10
11
12 #define CNS3XXX_FLASH_BASE 0x10000000
13 #define CNS3XXX_FLASH_SIZE SZ_256M
14
15 #define CNS3XXX_DDR2SDRAM_BASE 0x20000000
16
17 #define CNS3XXX_SPI_FLASH_BASE 0x60000000
18
19 #define CNS3XXX_SWITCH_BASE 0x70000000
20
21 #define CNS3XXX_PPE_BASE 0x70001000
22
23 #define CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000
24
25 #define CNS3XXX_SSP_BASE 0x71000000
26
27 #define CNS3XXX_DMC_BASE 0x72000000
28
29 #define CNS3XXX_SMC_BASE 0x73000000
30
31 #define SMC_MEMC_STATUS_OFFSET 0x000
32 #define SMC_MEMIF_CFG_OFFSET 0x004
33 #define SMC_MEMC_CFG_SET_OFFSET 0x008
34 #define SMC_MEMC_CFG_CLR_OFFSET 0x00C
35 #define SMC_DIRECT_CMD_OFFSET 0x010
36 #define SMC_SET_CYCLES_OFFSET 0x014
37 #define SMC_SET_OPMODE_OFFSET 0x018
38 #define SMC_REFRESH_PERIOD_0_OFFSET 0x020
39 #define SMC_REFRESH_PERIOD_1_OFFSET 0x024
40 #define SMC_SRAM_CYCLES0_0_OFFSET 0x100
41 #define SMC_NAND_CYCLES0_0_OFFSET 0x100
42 #define SMC_OPMODE0_0_OFFSET 0x104
43 #define SMC_SRAM_CYCLES0_1_OFFSET 0x120
44 #define SMC_NAND_CYCLES0_1_OFFSET 0x120
45 #define SMC_OPMODE0_1_OFFSET 0x124
46 #define SMC_USER_STATUS_OFFSET 0x200
47 #define SMC_USER_CONFIG_OFFSET 0x204
48 #define SMC_ECC_STATUS_OFFSET 0x300
49 #define SMC_ECC_MEMCFG_OFFSET 0x304
50 #define SMC_ECC_MEMCOMMAND1_OFFSET 0x308
51 #define SMC_ECC_MEMCOMMAND2_OFFSET 0x30C
52 #define SMC_ECC_ADDR0_OFFSET 0x310
53 #define SMC_ECC_ADDR1_OFFSET 0x314
54 #define SMC_ECC_VALUE0_OFFSET 0x318
55 #define SMC_ECC_VALUE1_OFFSET 0x31C
56 #define SMC_ECC_VALUE2_OFFSET 0x320
57 #define SMC_ECC_VALUE3_OFFSET 0x324
58 #define SMC_PERIPH_ID_0_OFFSET 0xFE0
59 #define SMC_PERIPH_ID_1_OFFSET 0xFE4
60 #define SMC_PERIPH_ID_2_OFFSET 0xFE8
61 #define SMC_PERIPH_ID_3_OFFSET 0xFEC
62 #define SMC_PCELL_ID_0_OFFSET 0xFF0
63 #define SMC_PCELL_ID_1_OFFSET 0xFF4
64 #define SMC_PCELL_ID_2_OFFSET 0xFF8
65 #define SMC_PCELL_ID_3_OFFSET 0xFFC
66
67 #define CNS3XXX_GPIOA_BASE 0x74000000
68
69 #define CNS3XXX_GPIOB_BASE 0x74800000
70
71 #define CNS3XXX_RTC_BASE 0x75000000
72
73 #define RTC_SEC_OFFSET 0x00
74 #define RTC_MIN_OFFSET 0x04
75 #define RTC_HOUR_OFFSET 0x08
76 #define RTC_DAY_OFFSET 0x0C
77 #define RTC_SEC_ALM_OFFSET 0x10
78 #define RTC_MIN_ALM_OFFSET 0x14
79 #define RTC_HOUR_ALM_OFFSET 0x18
80 #define RTC_REC_OFFSET 0x1C
81 #define RTC_CTRL_OFFSET 0x20
82 #define RTC_INTR_STS_OFFSET 0x34
83
84 #define CNS3XXX_MISC_BASE 0x76000000
85 #define CNS3XXX_MISC_BASE_VIRT 0xFB000000
86
87 #define CNS3XXX_PM_BASE 0x77000000
88 #define CNS3XXX_PM_BASE_VIRT 0xFB001000
89
90 #define PM_CLK_GATE_OFFSET 0x00
91 #define PM_SOFT_RST_OFFSET 0x04
92 #define PM_HS_CFG_OFFSET 0x08
93 #define PM_CACTIVE_STA_OFFSET 0x0C
94 #define PM_PWR_STA_OFFSET 0x10
95 #define PM_SYS_CLK_CTRL_OFFSET 0x14
96 #define PM_PLL_LCD_I2S_CTRL_OFFSET 0x18
97 #define PM_PLL_HM_PD_OFFSET 0x1C
98
99 #define CNS3XXX_UART0_BASE 0x78000000
100 #define CNS3XXX_UART0_BASE_VIRT 0xFB002000
101
102 #define CNS3XXX_UART1_BASE 0x78400000
103
104 #define CNS3XXX_UART2_BASE 0x78800000
105
106 #define CNS3XXX_DMAC_BASE 0x79000000
107
108 #define CNS3XXX_CORESIGHT_BASE 0x7A000000
109
110 #define CNS3XXX_CRYPTO_BASE 0x7B000000
111
112 #define CNS3XXX_I2S_BASE 0x7C000000
113
114 #define CNS3XXX_TIMER1_2_3_BASE 0x7C800000
115 #define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFB003000
116
117 #define TIMER1_COUNTER_OFFSET 0x00
118 #define TIMER1_AUTO_RELOAD_OFFSET 0x04
119 #define TIMER1_MATCH_V1_OFFSET 0x08
120 #define TIMER1_MATCH_V2_OFFSET 0x0C
121
122 #define TIMER2_COUNTER_OFFSET 0x10
123 #define TIMER2_AUTO_RELOAD_OFFSET 0x14
124 #define TIMER2_MATCH_V1_OFFSET 0x18
125 #define TIMER2_MATCH_V2_OFFSET 0x1C
126
127 #define TIMER1_2_CONTROL_OFFSET 0x30
128 #define TIMER1_2_INTERRUPT_STATUS_OFFSET 0x34
129 #define TIMER1_2_INTERRUPT_MASK_OFFSET 0x38
130
131 #define TIMER_FREERUN_OFFSET 0x40
132 #define TIMER_FREERUN_CONTROL_OFFSET 0x44
133
134 #define CNS3XXX_HCIE_BASE 0x7D000000
135
136 #define CNS3XXX_RAID_BASE 0x7E000000
137
138 #define CNS3XXX_AXI_IXC_BASE 0x7F000000
139
140 #define CNS3XXX_CLCD_BASE 0x80000000
141
142 #define CNS3XXX_USBOTG_BASE 0x81000000
143
144 #define CNS3XXX_USB_BASE 0x82000000
145
146 #define CNS3XXX_SATA2_BASE 0x83000000
147 #define CNS3XXX_SATA2_SIZE SZ_16M
148
149 #define CNS3XXX_CAMERA_BASE 0x84000000
150
151 #define CNS3XXX_SDIO_BASE 0x85000000
152
153 #define CNS3XXX_I2S_TDM_BASE 0x86000000
154
155 #define CNS3XXX_2DG_BASE 0x87000000
156
157 #define CNS3XXX_USB_OHCI_BASE 0x88000000
158
159 #define CNS3XXX_L2C_BASE 0x92000000
160
161 #define CNS3XXX_PCIE0_MEM_BASE 0xA0000000
162
163 #define CNS3XXX_PCIE0_HOST_BASE 0xAB000000
164 #define CNS3XXX_PCIE0_HOST_BASE_VIRT 0xE1000000
165
166 #define CNS3XXX_PCIE0_IO_BASE 0xAC000000
167
168 #define CNS3XXX_PCIE0_CFG0_BASE 0xAD000000
169 #define CNS3XXX_PCIE0_CFG0_BASE_VIRT 0xE3000000
170
171 #define CNS3XXX_PCIE0_CFG1_BASE 0xAE000000
172 #define CNS3XXX_PCIE0_CFG1_BASE_VIRT 0xE4000000
173
174 #define CNS3XXX_PCIE0_MSG_BASE 0xAF000000
175
176 #define CNS3XXX_PCIE1_MEM_BASE 0xB0000000
177
178 #define CNS3XXX_PCIE1_HOST_BASE 0xBB000000
179 #define CNS3XXX_PCIE1_HOST_BASE_VIRT 0xE9000000
180
181 #define CNS3XXX_PCIE1_IO_BASE 0xBC000000
182
183 #define CNS3XXX_PCIE1_CFG0_BASE 0xBD000000
184 #define CNS3XXX_PCIE1_CFG0_BASE_VIRT 0xEB000000
185
186 #define CNS3XXX_PCIE1_CFG1_BASE 0xBE000000
187 #define CNS3XXX_PCIE1_CFG1_BASE_VIRT 0xEC000000
188
189 #define CNS3XXX_PCIE1_MSG_BASE 0xBF000000
190
191
192
193
194 #define CNS3XXX_TC11MP_SCU_BASE 0x90000000
195 #define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFB004000
196
197 #define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100
198 #define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x100)
199
200 #define CNS3XXX_TC11MP_TWD_BASE 0x90000600
201 #define CNS3XXX_TC11MP_TWD_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x600)
202
203 #define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000
204 #define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000)
205
206 #define CNS3XXX_TC11MP_L220_BASE 0x92002000
207
208
209
210
211 #define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs))
212
213 #define MISC_MEMORY_REMAP_REG MISC_MEM_MAP(0x00)
214 #define MISC_CHIP_CONFIG_REG MISC_MEM_MAP(0x04)
215 #define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP(0x08)
216 #define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP(0x0C)
217 #define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP(0x10)
218 #define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP(0x14)
219 #define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP(0x18)
220 #define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP(0x1C)
221 #define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP(0x20)
222 #define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x24)
223 #define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x28)
224 #define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x2C)
225 #define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x30)
226 #define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP(0x34)
227 #define MISC_E_FUSE_31_0_REG MISC_MEM_MAP(0x40)
228 #define MISC_E_FUSE_63_32_REG MISC_MEM_MAP(0x44)
229 #define MISC_E_FUSE_95_64_REG MISC_MEM_MAP(0x48)
230 #define MISC_E_FUSE_127_96_REG MISC_MEM_MAP(0x4C)
231 #define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP(0x50)
232 #define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP(0x54)
233
234 #define MISC_SATA_POWER_MODE MISC_MEM_MAP(0x310)
235
236 #define MISC_USB_CFG_REG MISC_MEM_MAP(0x800)
237 #define MISC_USB_STS_REG MISC_MEM_MAP(0x804)
238 #define MISC_USBPHY00_CFG_REG MISC_MEM_MAP(0x808)
239 #define MISC_USBPHY01_CFG_REG MISC_MEM_MAP(0x80c)
240 #define MISC_USBPHY10_CFG_REG MISC_MEM_MAP(0x810)
241 #define MISC_USBPHY11_CFG_REG MISC_MEM_MAP(0x814)
242
243 #define MISC_PCIEPHY_CMCTL(x) MISC_MEM_MAP(0x900 + (x) * 0x004)
244 #define MISC_PCIEPHY_CTL(x) MISC_MEM_MAP(0x940 + (x) * 0x100)
245 #define MISC_PCIE_AXIS_AWMISC(x) MISC_MEM_MAP(0x944 + (x) * 0x100)
246 #define MISC_PCIE_AXIS_ARMISC(x) MISC_MEM_MAP(0x948 + (x) * 0x100)
247 #define MISC_PCIE_AXIS_RMISC(x) MISC_MEM_MAP(0x94C + (x) * 0x100)
248 #define MISC_PCIE_AXIS_BMISC(x) MISC_MEM_MAP(0x950 + (x) * 0x100)
249 #define MISC_PCIE_AXIM_RMISC(x) MISC_MEM_MAP(0x954 + (x) * 0x100)
250 #define MISC_PCIE_AXIM_BMISC(x) MISC_MEM_MAP(0x958 + (x) * 0x100)
251 #define MISC_PCIE_CTRL(x) MISC_MEM_MAP(0x95C + (x) * 0x100)
252 #define MISC_PCIE_PM_DEBUG(x) MISC_MEM_MAP(0x960 + (x) * 0x100)
253 #define MISC_PCIE_RFC_DEBUG(x) MISC_MEM_MAP(0x964 + (x) * 0x100)
254 #define MISC_PCIE_CXPL_DEBUGL(x) MISC_MEM_MAP(0x968 + (x) * 0x100)
255 #define MISC_PCIE_CXPL_DEBUGH(x) MISC_MEM_MAP(0x96C + (x) * 0x100)
256 #define MISC_PCIE_DIAG_DEBUGH(x) MISC_MEM_MAP(0x970 + (x) * 0x100)
257 #define MISC_PCIE_W1CLR(x) MISC_MEM_MAP(0x974 + (x) * 0x100)
258 #define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100)
259 #define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100)
260
261
262
263
264 #define PMU_MEM_MAP(offs) (void __iomem *)(CNS3XXX_PM_BASE_VIRT + (offs))
265
266 #define PM_CLK_GATE_REG PMU_MEM_MAP(0x000)
267 #define PM_SOFT_RST_REG PMU_MEM_MAP(0x004)
268 #define PM_HS_CFG_REG PMU_MEM_MAP(0x008)
269 #define PM_CACTIVE_STA_REG PMU_MEM_MAP(0x00C)
270 #define PM_PWR_STA_REG PMU_MEM_MAP(0x010)
271 #define PM_CLK_CTRL_REG PMU_MEM_MAP(0x014)
272 #define PM_PLL_LCD_I2S_CTRL_REG PMU_MEM_MAP(0x018)
273 #define PM_PLL_HM_PD_CTRL_REG PMU_MEM_MAP(0x01C)
274 #define PM_REGULAT_CTRL_REG PMU_MEM_MAP(0x020)
275 #define PM_WDT_CTRL_REG PMU_MEM_MAP(0x024)
276 #define PM_WU_CTRL0_REG PMU_MEM_MAP(0x028)
277 #define PM_WU_CTRL1_REG PMU_MEM_MAP(0x02C)
278 #define PM_CSR_REG PMU_MEM_MAP(0x030)
279
280
281 #define PM_CLK_GATE_REG_OFFSET_SDIO (25)
282 #define PM_CLK_GATE_REG_OFFSET_GPU (24)
283 #define PM_CLK_GATE_REG_OFFSET_CIM (23)
284 #define PM_CLK_GATE_REG_OFFSET_LCDC (22)
285 #define PM_CLK_GATE_REG_OFFSET_I2S (21)
286 #define PM_CLK_GATE_REG_OFFSET_RAID (20)
287 #define PM_CLK_GATE_REG_OFFSET_SATA (19)
288 #define PM_CLK_GATE_REG_OFFSET_PCIE(x) (17 + (x))
289 #define PM_CLK_GATE_REG_OFFSET_USB_HOST (16)
290 #define PM_CLK_GATE_REG_OFFSET_USB_OTG (15)
291 #define PM_CLK_GATE_REG_OFFSET_TIMER (14)
292 #define PM_CLK_GATE_REG_OFFSET_CRYPTO (13)
293 #define PM_CLK_GATE_REG_OFFSET_HCIE (12)
294 #define PM_CLK_GATE_REG_OFFSET_SWITCH (11)
295 #define PM_CLK_GATE_REG_OFFSET_GPIO (10)
296 #define PM_CLK_GATE_REG_OFFSET_UART3 (9)
297 #define PM_CLK_GATE_REG_OFFSET_UART2 (8)
298 #define PM_CLK_GATE_REG_OFFSET_UART1 (7)
299 #define PM_CLK_GATE_REG_OFFSET_RTC (5)
300 #define PM_CLK_GATE_REG_OFFSET_GDMA (4)
301 #define PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C (3)
302 #define PM_CLK_GATE_REG_OFFSET_SMC_NFI (1)
303 #define PM_CLK_GATE_REG_MASK (0x03FFFFBA)
304
305
306 #define PM_SOFT_RST_REG_OFFST_WARM_RST_FLAG (31)
307 #define PM_SOFT_RST_REG_OFFST_CPU1 (29)
308 #define PM_SOFT_RST_REG_OFFST_CPU0 (28)
309 #define PM_SOFT_RST_REG_OFFST_SDIO (25)
310 #define PM_SOFT_RST_REG_OFFST_GPU (24)
311 #define PM_SOFT_RST_REG_OFFST_CIM (23)
312 #define PM_SOFT_RST_REG_OFFST_LCDC (22)
313 #define PM_SOFT_RST_REG_OFFST_I2S (21)
314 #define PM_SOFT_RST_REG_OFFST_RAID (20)
315 #define PM_SOFT_RST_REG_OFFST_SATA (19)
316 #define PM_SOFT_RST_REG_OFFST_PCIE(x) (17 + (x))
317 #define PM_SOFT_RST_REG_OFFST_USB_HOST (16)
318 #define PM_SOFT_RST_REG_OFFST_USB_OTG (15)
319 #define PM_SOFT_RST_REG_OFFST_TIMER (14)
320 #define PM_SOFT_RST_REG_OFFST_CRYPTO (13)
321 #define PM_SOFT_RST_REG_OFFST_HCIE (12)
322 #define PM_SOFT_RST_REG_OFFST_SWITCH (11)
323 #define PM_SOFT_RST_REG_OFFST_GPIO (10)
324 #define PM_SOFT_RST_REG_OFFST_UART3 (9)
325 #define PM_SOFT_RST_REG_OFFST_UART2 (8)
326 #define PM_SOFT_RST_REG_OFFST_UART1 (7)
327 #define PM_SOFT_RST_REG_OFFST_RTC (5)
328 #define PM_SOFT_RST_REG_OFFST_GDMA (4)
329 #define PM_SOFT_RST_REG_OFFST_SPI_PCM_I2C (3)
330 #define PM_SOFT_RST_REG_OFFST_DMC (2)
331 #define PM_SOFT_RST_REG_OFFST_SMC_NFI (1)
332 #define PM_SOFT_RST_REG_OFFST_GLOBAL (0)
333 #define PM_SOFT_RST_REG_MASK (0xF3FFFFBF)
334
335
336 #define PM_HS_CFG_REG_OFFSET_SDIO (25)
337 #define PM_HS_CFG_REG_OFFSET_GPU (24)
338 #define PM_HS_CFG_REG_OFFSET_CIM (23)
339 #define PM_HS_CFG_REG_OFFSET_LCDC (22)
340 #define PM_HS_CFG_REG_OFFSET_I2S (21)
341 #define PM_HS_CFG_REG_OFFSET_RAID (20)
342 #define PM_HS_CFG_REG_OFFSET_SATA (19)
343 #define PM_HS_CFG_REG_OFFSET_PCIE1 (18)
344 #define PM_HS_CFG_REG_OFFSET_PCIE0 (17)
345 #define PM_HS_CFG_REG_OFFSET_USB_HOST (16)
346 #define PM_HS_CFG_REG_OFFSET_USB_OTG (15)
347 #define PM_HS_CFG_REG_OFFSET_TIMER (14)
348 #define PM_HS_CFG_REG_OFFSET_CRYPTO (13)
349 #define PM_HS_CFG_REG_OFFSET_HCIE (12)
350 #define PM_HS_CFG_REG_OFFSET_SWITCH (11)
351 #define PM_HS_CFG_REG_OFFSET_GPIO (10)
352 #define PM_HS_CFG_REG_OFFSET_UART3 (9)
353 #define PM_HS_CFG_REG_OFFSET_UART2 (8)
354 #define PM_HS_CFG_REG_OFFSET_UART1 (7)
355 #define PM_HS_CFG_REG_OFFSET_RTC (5)
356 #define PM_HS_CFG_REG_OFFSET_GDMA (4)
357 #define PM_HS_CFG_REG_OFFSET_SPI_PCM_I2S (3)
358 #define PM_HS_CFG_REG_OFFSET_DMC (2)
359 #define PM_HS_CFG_REG_OFFSET_SMC_NFI (1)
360 #define PM_HS_CFG_REG_MASK (0x03FFFFBE)
361 #define PM_HS_CFG_REG_MASK_SUPPORT (0x01100806)
362
363
364 #define PM_CACTIVE_STA_REG_OFFSET_SDIO (25)
365 #define PM_CACTIVE_STA_REG_OFFSET_GPU (24)
366 #define PM_CACTIVE_STA_REG_OFFSET_CIM (23)
367 #define PM_CACTIVE_STA_REG_OFFSET_LCDC (22)
368 #define PM_CACTIVE_STA_REG_OFFSET_I2S (21)
369 #define PM_CACTIVE_STA_REG_OFFSET_RAID (20)
370 #define PM_CACTIVE_STA_REG_OFFSET_SATA (19)
371 #define PM_CACTIVE_STA_REG_OFFSET_PCIE1 (18)
372 #define PM_CACTIVE_STA_REG_OFFSET_PCIE0 (17)
373 #define PM_CACTIVE_STA_REG_OFFSET_USB_HOST (16)
374 #define PM_CACTIVE_STA_REG_OFFSET_USB_OTG (15)
375 #define PM_CACTIVE_STA_REG_OFFSET_TIMER (14)
376 #define PM_CACTIVE_STA_REG_OFFSET_CRYPTO (13)
377 #define PM_CACTIVE_STA_REG_OFFSET_HCIE (12)
378 #define PM_CACTIVE_STA_REG_OFFSET_SWITCH (11)
379 #define PM_CACTIVE_STA_REG_OFFSET_GPIO (10)
380 #define PM_CACTIVE_STA_REG_OFFSET_UART3 (9)
381 #define PM_CACTIVE_STA_REG_OFFSET_UART2 (8)
382 #define PM_CACTIVE_STA_REG_OFFSET_UART1 (7)
383 #define PM_CACTIVE_STA_REG_OFFSET_RTC (5)
384 #define PM_CACTIVE_STA_REG_OFFSET_GDMA (4)
385 #define PM_CACTIVE_STA_REG_OFFSET_SPI_PCM_I2S (3)
386 #define PM_CACTIVE_STA_REG_OFFSET_DMC (2)
387 #define PM_CACTIVE_STA_REG_OFFSET_SMC_NFI (1)
388 #define PM_CACTIVE_STA_REG_MASK (0x03FFFFBE)
389
390
391 #define PM_PWR_STA_REG_REG_OFFSET_SDIO (25)
392 #define PM_PWR_STA_REG_REG_OFFSET_GPU (24)
393 #define PM_PWR_STA_REG_REG_OFFSET_CIM (23)
394 #define PM_PWR_STA_REG_REG_OFFSET_LCDC (22)
395 #define PM_PWR_STA_REG_REG_OFFSET_I2S (21)
396 #define PM_PWR_STA_REG_REG_OFFSET_RAID (20)
397 #define PM_PWR_STA_REG_REG_OFFSET_SATA (19)
398 #define PM_PWR_STA_REG_REG_OFFSET_PCIE1 (18)
399 #define PM_PWR_STA_REG_REG_OFFSET_PCIE0 (17)
400 #define PM_PWR_STA_REG_REG_OFFSET_USB_HOST (16)
401 #define PM_PWR_STA_REG_REG_OFFSET_USB_OTG (15)
402 #define PM_PWR_STA_REG_REG_OFFSET_TIMER (14)
403 #define PM_PWR_STA_REG_REG_OFFSET_CRYPTO (13)
404 #define PM_PWR_STA_REG_REG_OFFSET_HCIE (12)
405 #define PM_PWR_STA_REG_REG_OFFSET_SWITCH (11)
406 #define PM_PWR_STA_REG_REG_OFFSET_GPIO (10)
407 #define PM_PWR_STA_REG_REG_OFFSET_UART3 (9)
408 #define PM_PWR_STA_REG_REG_OFFSET_UART2 (8)
409 #define PM_PWR_STA_REG_REG_OFFSET_UART1 (7)
410 #define PM_PWR_STA_REG_REG_OFFSET_RTC (5)
411 #define PM_PWR_STA_REG_REG_OFFSET_GDMA (4)
412 #define PM_PWR_STA_REG_REG_OFFSET_SPI_PCM_I2S (3)
413 #define PM_PWR_STA_REG_REG_OFFSET_DMC (2)
414 #define PM_PWR_STA_REG_REG_OFFSET_SMC_NFI (1)
415 #define PM_PWR_STA_REG_REG_MASK (0x03FFFFBE)
416
417
418 #define PM_CLK_CTRL_REG_OFFSET_I2S_MCLK (31)
419 #define PM_CLK_CTRL_REG_OFFSET_DDR2_CHG_EN (30)
420 #define PM_CLK_CTRL_REG_OFFSET_PCIE_REF1_EN (29)
421 #define PM_CLK_CTRL_REG_OFFSET_PCIE_REF0_EN (28)
422 #define PM_CLK_CTRL_REG_OFFSET_TIMER_SIM_MODE (27)
423 #define PM_CLK_CTRL_REG_OFFSET_I2SCLK_DIV (24)
424 #define PM_CLK_CTRL_REG_OFFSET_I2SCLK_SEL (22)
425 #define PM_CLK_CTRL_REG_OFFSET_CLKOUT_DIV (20)
426 #define PM_CLK_CTRL_REG_OFFSET_CLKOUT_SEL (16)
427 #define PM_CLK_CTRL_REG_OFFSET_MDC_DIV (14)
428 #define PM_CLK_CTRL_REG_OFFSET_CRYPTO_CLK_SEL (12)
429 #define PM_CLK_CTRL_REG_OFFSET_CPU_PWR_MODE (9)
430 #define PM_CLK_CTRL_REG_OFFSET_PLL_DDR2_SEL (7)
431 #define PM_CLK_CTRL_REG_OFFSET_DIV_IMMEDIATE (6)
432 #define PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV (4)
433 #define PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL (0)
434
435 #define PM_CPU_CLK_DIV(DIV) { \
436 PM_CLK_CTRL_REG &= ~((0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \
437 PM_CLK_CTRL_REG |= (((DIV)&0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \
438 }
439
440 #define PM_PLL_CPU_SEL(CPU) { \
441 PM_CLK_CTRL_REG &= ~((0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \
442 PM_CLK_CTRL_REG |= (((CPU)&0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \
443 }
444
445
446 #define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_MCLK_SMC_DIV (22)
447 #define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_R_SEL (17)
448 #define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_P (11)
449 #define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_M (3)
450 #define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_S (0)
451
452
453 #define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1 (11)
454 #define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0 (10)
455 #define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2SCD (6)
456 #define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2S (5)
457 #define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_LCD (4)
458 #define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB (3)
459 #define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_RGMII (2)
460 #define PM_PLL_HM_PD_CTRL_REG_MASK (0x00000C7C)
461
462
463 #define PM_WDT_CTRL_REG_OFFSET_RESET_CPU_ONLY (0)
464
465
466 #define PM_CSR_REG_OFFSET_CSR_EN (30)
467 #define PM_CSR_REG_OFFSET_CSR_NUM (0)
468
469 #define CNS3XXX_PWR_CLK_EN(BLOCK) (0x1<<PM_CLK_GATE_REG_OFFSET_##BLOCK)
470
471
472 #define CNS3XXX_PWR_SOFTWARE_RST(BLOCK) (0x1<<PM_SOFT_RST_REG_OFFST_##BLOCK)
473
474
475
476
477
478 #define CNS3XXX_PWR_CPU_MODE_DFS (0)
479 #define CNS3XXX_PWR_CPU_MODE_IDLE (1)
480 #define CNS3XXX_PWR_CPU_MODE_HALT (2)
481 #define CNS3XXX_PWR_CPU_MODE_DOZE (3)
482 #define CNS3XXX_PWR_CPU_MODE_SLEEP (4)
483 #define CNS3XXX_PWR_CPU_MODE_HIBERNATE (5)
484
485 #define CNS3XXX_PWR_PLL(BLOCK) (0x1<<PM_PLL_HM_PD_CTRL_REG_OFFSET_##BLOCK)
486 #define CNS3XXX_PWR_PLL_ALL PM_PLL_HM_PD_CTRL_REG_MASK
487
488
489 #define CNS3XXX_PWR_PLL_CPU_300MHZ (0)
490 #define CNS3XXX_PWR_PLL_CPU_333MHZ (1)
491 #define CNS3XXX_PWR_PLL_CPU_366MHZ (2)
492 #define CNS3XXX_PWR_PLL_CPU_400MHZ (3)
493 #define CNS3XXX_PWR_PLL_CPU_433MHZ (4)
494 #define CNS3XXX_PWR_PLL_CPU_466MHZ (5)
495 #define CNS3XXX_PWR_PLL_CPU_500MHZ (6)
496 #define CNS3XXX_PWR_PLL_CPU_533MHZ (7)
497 #define CNS3XXX_PWR_PLL_CPU_566MHZ (8)
498 #define CNS3XXX_PWR_PLL_CPU_600MHZ (9)
499 #define CNS3XXX_PWR_PLL_CPU_633MHZ (10)
500 #define CNS3XXX_PWR_PLL_CPU_666MHZ (11)
501 #define CNS3XXX_PWR_PLL_CPU_700MHZ (12)
502
503 #define CNS3XXX_PWR_CPU_CLK_DIV_BY1 (0)
504 #define CNS3XXX_PWR_CPU_CLK_DIV_BY2 (1)
505 #define CNS3XXX_PWR_CPU_CLK_DIV_BY4 (2)
506
507
508 #define CNS3XXX_PWR_PLL_DDR2_200MHZ (0)
509 #define CNS3XXX_PWR_PLL_DDR2_266MHZ (1)
510 #define CNS3XXX_PWR_PLL_DDR2_333MHZ (2)
511 #define CNS3XXX_PWR_PLL_DDR2_400MHZ (3)
512
513 void cns3xxx_pwr_soft_rst(unsigned int block);
514 void cns3xxx_pwr_clk_en(unsigned int block);
515 int cns3xxx_cpu_clock(void);
516
517
518
519
520 #define IRQ_TC11MP_GIC_START 32
521
522 #define IRQ_CNS3XXX_PMU (IRQ_TC11MP_GIC_START + 0)
523 #define IRQ_CNS3XXX_SDIO (IRQ_TC11MP_GIC_START + 1)
524 #define IRQ_CNS3XXX_L2CC (IRQ_TC11MP_GIC_START + 2)
525 #define IRQ_CNS3XXX_RTC (IRQ_TC11MP_GIC_START + 3)
526 #define IRQ_CNS3XXX_I2S (IRQ_TC11MP_GIC_START + 4)
527 #define IRQ_CNS3XXX_PCM (IRQ_TC11MP_GIC_START + 5)
528 #define IRQ_CNS3XXX_SPI (IRQ_TC11MP_GIC_START + 6)
529 #define IRQ_CNS3XXX_I2C (IRQ_TC11MP_GIC_START + 7)
530 #define IRQ_CNS3XXX_CIM (IRQ_TC11MP_GIC_START + 8)
531 #define IRQ_CNS3XXX_GPU (IRQ_TC11MP_GIC_START + 9)
532 #define IRQ_CNS3XXX_LCD (IRQ_TC11MP_GIC_START + 10)
533 #define IRQ_CNS3XXX_GPIOA (IRQ_TC11MP_GIC_START + 11)
534 #define IRQ_CNS3XXX_GPIOB (IRQ_TC11MP_GIC_START + 12)
535 #define IRQ_CNS3XXX_UART0 (IRQ_TC11MP_GIC_START + 13)
536 #define IRQ_CNS3XXX_UART1 (IRQ_TC11MP_GIC_START + 14)
537 #define IRQ_CNS3XXX_UART2 (IRQ_TC11MP_GIC_START + 15)
538 #define IRQ_CNS3XXX_ARM11 (IRQ_TC11MP_GIC_START + 16)
539
540 #define IRQ_CNS3XXX_SW_STATUS (IRQ_TC11MP_GIC_START + 17)
541 #define IRQ_CNS3XXX_SW_R0TXC (IRQ_TC11MP_GIC_START + 18)
542 #define IRQ_CNS3XXX_SW_R0RXC (IRQ_TC11MP_GIC_START + 19)
543 #define IRQ_CNS3XXX_SW_R0QE (IRQ_TC11MP_GIC_START + 20)
544 #define IRQ_CNS3XXX_SW_R0QF (IRQ_TC11MP_GIC_START + 21)
545 #define IRQ_CNS3XXX_SW_R1TXC (IRQ_TC11MP_GIC_START + 22)
546 #define IRQ_CNS3XXX_SW_R1RXC (IRQ_TC11MP_GIC_START + 23)
547 #define IRQ_CNS3XXX_SW_R1QE (IRQ_TC11MP_GIC_START + 24)
548 #define IRQ_CNS3XXX_SW_R1QF (IRQ_TC11MP_GIC_START + 25)
549 #define IRQ_CNS3XXX_SW_PPE (IRQ_TC11MP_GIC_START + 26)
550
551 #define IRQ_CNS3XXX_CRYPTO (IRQ_TC11MP_GIC_START + 27)
552 #define IRQ_CNS3XXX_HCIE (IRQ_TC11MP_GIC_START + 28)
553 #define IRQ_CNS3XXX_PCIE0_DEVICE (IRQ_TC11MP_GIC_START + 29)
554 #define IRQ_CNS3XXX_PCIE1_DEVICE (IRQ_TC11MP_GIC_START + 30)
555 #define IRQ_CNS3XXX_USB_OTG (IRQ_TC11MP_GIC_START + 31)
556 #define IRQ_CNS3XXX_USB_EHCI (IRQ_TC11MP_GIC_START + 32)
557 #define IRQ_CNS3XXX_SATA (IRQ_TC11MP_GIC_START + 33)
558 #define IRQ_CNS3XXX_RAID (IRQ_TC11MP_GIC_START + 34)
559 #define IRQ_CNS3XXX_SMC (IRQ_TC11MP_GIC_START + 35)
560
561 #define IRQ_CNS3XXX_DMAC_ABORT (IRQ_TC11MP_GIC_START + 36)
562 #define IRQ_CNS3XXX_DMAC0 (IRQ_TC11MP_GIC_START + 37)
563 #define IRQ_CNS3XXX_DMAC1 (IRQ_TC11MP_GIC_START + 38)
564 #define IRQ_CNS3XXX_DMAC2 (IRQ_TC11MP_GIC_START + 39)
565 #define IRQ_CNS3XXX_DMAC3 (IRQ_TC11MP_GIC_START + 40)
566 #define IRQ_CNS3XXX_DMAC4 (IRQ_TC11MP_GIC_START + 41)
567 #define IRQ_CNS3XXX_DMAC5 (IRQ_TC11MP_GIC_START + 42)
568 #define IRQ_CNS3XXX_DMAC6 (IRQ_TC11MP_GIC_START + 43)
569 #define IRQ_CNS3XXX_DMAC7 (IRQ_TC11MP_GIC_START + 44)
570 #define IRQ_CNS3XXX_DMAC8 (IRQ_TC11MP_GIC_START + 45)
571 #define IRQ_CNS3XXX_DMAC9 (IRQ_TC11MP_GIC_START + 46)
572 #define IRQ_CNS3XXX_DMAC10 (IRQ_TC11MP_GIC_START + 47)
573 #define IRQ_CNS3XXX_DMAC11 (IRQ_TC11MP_GIC_START + 48)
574 #define IRQ_CNS3XXX_DMAC12 (IRQ_TC11MP_GIC_START + 49)
575 #define IRQ_CNS3XXX_DMAC13 (IRQ_TC11MP_GIC_START + 50)
576 #define IRQ_CNS3XXX_DMAC14 (IRQ_TC11MP_GIC_START + 51)
577 #define IRQ_CNS3XXX_DMAC15 (IRQ_TC11MP_GIC_START + 52)
578 #define IRQ_CNS3XXX_DMAC16 (IRQ_TC11MP_GIC_START + 53)
579 #define IRQ_CNS3XXX_DMAC17 (IRQ_TC11MP_GIC_START + 54)
580
581 #define IRQ_CNS3XXX_PCIE0_RC (IRQ_TC11MP_GIC_START + 55)
582 #define IRQ_CNS3XXX_PCIE1_RC (IRQ_TC11MP_GIC_START + 56)
583 #define IRQ_CNS3XXX_TIMER0 (IRQ_TC11MP_GIC_START + 57)
584 #define IRQ_CNS3XXX_TIMER1 (IRQ_TC11MP_GIC_START + 58)
585 #define IRQ_CNS3XXX_USB_OHCI (IRQ_TC11MP_GIC_START + 59)
586 #define IRQ_CNS3XXX_TIMER2 (IRQ_TC11MP_GIC_START + 60)
587 #define IRQ_CNS3XXX_EXTERNAL_PIN0 (IRQ_TC11MP_GIC_START + 61)
588 #define IRQ_CNS3XXX_EXTERNAL_PIN1 (IRQ_TC11MP_GIC_START + 62)
589 #define IRQ_CNS3XXX_EXTERNAL_PIN2 (IRQ_TC11MP_GIC_START + 63)
590
591 #define NR_IRQS_CNS3XXX (IRQ_TC11MP_GIC_START + 64)
592
593 #endif