root/arch/arm/mach-iop32x/adma.c

DEFINITIONS

1. iop3xx_adma_cap_init

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * platform device definitions for the iop3xx dma/xor engines
   4  * Copyright © 2006, Intel Corporation.
   5  */
   6 #include <linux/platform_device.h>
   7 #include <linux/dma-mapping.h>
   8 #include <linux/platform_data/dma-iop32x.h>
   9 
  10 #include "iop3xx.h"
  11 #include "irqs.h"
  12 
  13 #define IRQ_DMA0_EOT IRQ_IOP32X_DMA0_EOT
  14 #define IRQ_DMA0_EOC IRQ_IOP32X_DMA0_EOC
  15 #define IRQ_DMA0_ERR IRQ_IOP32X_DMA0_ERR
  16 
  17 #define IRQ_DMA1_EOT IRQ_IOP32X_DMA1_EOT
  18 #define IRQ_DMA1_EOC IRQ_IOP32X_DMA1_EOC
  19 #define IRQ_DMA1_ERR IRQ_IOP32X_DMA1_ERR
  20 
  21 #define IRQ_AA_EOT IRQ_IOP32X_AA_EOT
  22 #define IRQ_AA_EOC IRQ_IOP32X_AA_EOC
  23 #define IRQ_AA_ERR IRQ_IOP32X_AA_ERR
  24 
  25 /* AAU and DMA Channels */
  26 static struct resource iop3xx_dma_0_resources[] = {
  27         [0] = {
  28                 .start = IOP3XX_DMA_PHYS_BASE(0),
  29                 .end = IOP3XX_DMA_UPPER_PA(0),
  30                 .flags = IORESOURCE_MEM,
  31         },
  32         [1] = {
  33                 .start = IRQ_DMA0_EOT,
  34                 .end = IRQ_DMA0_EOT,
  35                 .flags = IORESOURCE_IRQ
  36         },
  37         [2] = {
  38                 .start = IRQ_DMA0_EOC,
  39                 .end = IRQ_DMA0_EOC,
  40                 .flags = IORESOURCE_IRQ
  41         },
  42         [3] = {
  43                 .start = IRQ_DMA0_ERR,
  44                 .end = IRQ_DMA0_ERR,
  45                 .flags = IORESOURCE_IRQ
  46         }
  47 };
  48 
  49 static struct resource iop3xx_dma_1_resources[] = {
  50         [0] = {
  51                 .start = IOP3XX_DMA_PHYS_BASE(1),
  52                 .end = IOP3XX_DMA_UPPER_PA(1),
  53                 .flags = IORESOURCE_MEM,
  54         },
  55         [1] = {
  56                 .start = IRQ_DMA1_EOT,
  57                 .end = IRQ_DMA1_EOT,
  58                 .flags = IORESOURCE_IRQ
  59         },
  60         [2] = {
  61                 .start = IRQ_DMA1_EOC,
  62                 .end = IRQ_DMA1_EOC,
  63                 .flags = IORESOURCE_IRQ
  64         },
  65         [3] = {
  66                 .start = IRQ_DMA1_ERR,
  67                 .end = IRQ_DMA1_ERR,
  68                 .flags = IORESOURCE_IRQ
  69         }
  70 };
  71 
  72 
  73 static struct resource iop3xx_aau_resources[] = {
  74         [0] = {
  75                 .start = IOP3XX_AAU_PHYS_BASE,
  76                 .end = IOP3XX_AAU_UPPER_PA,
  77                 .flags = IORESOURCE_MEM,
  78         },
  79         [1] = {
  80                 .start = IRQ_AA_EOT,
  81                 .end = IRQ_AA_EOT,
  82                 .flags = IORESOURCE_IRQ
  83         },
  84         [2] = {
  85                 .start = IRQ_AA_EOC,
  86                 .end = IRQ_AA_EOC,
  87                 .flags = IORESOURCE_IRQ
  88         },
  89         [3] = {
  90                 .start = IRQ_AA_ERR,
  91                 .end = IRQ_AA_ERR,
  92                 .flags = IORESOURCE_IRQ
  93         }
  94 };
  95 
  96 static u64 iop3xx_adma_dmamask = DMA_BIT_MASK(32);
  97 
  98 static struct iop_adma_platform_data iop3xx_dma_0_data = {
  99         .hw_id = DMA0_ID,
 100         .pool_size = PAGE_SIZE,
 101 };
 102 
 103 static struct iop_adma_platform_data iop3xx_dma_1_data = {
 104         .hw_id = DMA1_ID,
 105         .pool_size = PAGE_SIZE,
 106 };
 107 
 108 static struct iop_adma_platform_data iop3xx_aau_data = {
 109         .hw_id = AAU_ID,
 110         .pool_size = 3 * PAGE_SIZE,
 111 };
 112 
 113 struct platform_device iop3xx_dma_0_channel = {
 114         .name = "iop-adma",
 115         .id = 0,
 116         .num_resources = 4,
 117         .resource = iop3xx_dma_0_resources,
 118         .dev = {
 119                 .dma_mask = &iop3xx_adma_dmamask,
 120                 .coherent_dma_mask = DMA_BIT_MASK(32),
 121                 .platform_data = (void *) &iop3xx_dma_0_data,
 122         },
 123 };
 124 
 125 struct platform_device iop3xx_dma_1_channel = {
 126         .name = "iop-adma",
 127         .id = 1,
 128         .num_resources = 4,
 129         .resource = iop3xx_dma_1_resources,
 130         .dev = {
 131                 .dma_mask = &iop3xx_adma_dmamask,
 132                 .coherent_dma_mask = DMA_BIT_MASK(32),
 133                 .platform_data = (void *) &iop3xx_dma_1_data,
 134         },
 135 };
 136 
 137 struct platform_device iop3xx_aau_channel = {
 138         .name = "iop-adma",
 139         .id = 2,
 140         .num_resources = 4,
 141         .resource = iop3xx_aau_resources,
 142         .dev = {
 143                 .dma_mask = &iop3xx_adma_dmamask,
 144                 .coherent_dma_mask = DMA_BIT_MASK(32),
 145                 .platform_data = (void *) &iop3xx_aau_data,
 146         },
 147 };
 148 
 149 static int __init iop3xx_adma_cap_init(void)
 150 {
 151         dma_cap_set(DMA_MEMCPY, iop3xx_dma_0_data.cap_mask);
 152         dma_cap_set(DMA_INTERRUPT, iop3xx_dma_0_data.cap_mask);
 153 
 154         dma_cap_set(DMA_MEMCPY, iop3xx_dma_1_data.cap_mask);
 155         dma_cap_set(DMA_INTERRUPT, iop3xx_dma_1_data.cap_mask);
 156 
 157         dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask);
 158         dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask);
 159 
 160         return 0;
 161 }
 162 
 163 arch_initcall(iop3xx_adma_cap_init);