This source file includes following definitions.
- intctl_write
- intstr_write
- iop32x_irq_mask
- iop32x_irq_unmask
- iop32x_init_irq
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11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/list.h>
14 #include <asm/mach/irq.h>
15 #include <asm/irq.h>
16 #include <asm/mach-types.h>
17
18 #include "hardware.h"
19
20 static u32 iop32x_mask;
21
22 static void intctl_write(u32 val)
23 {
24 asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
25 }
26
27 static void intstr_write(u32 val)
28 {
29 asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val));
30 }
31
32 static void
33 iop32x_irq_mask(struct irq_data *d)
34 {
35 iop32x_mask &= ~(1 << d->irq);
36 intctl_write(iop32x_mask);
37 }
38
39 static void
40 iop32x_irq_unmask(struct irq_data *d)
41 {
42 iop32x_mask |= 1 << d->irq;
43 intctl_write(iop32x_mask);
44 }
45
46 struct irq_chip ext_chip = {
47 .name = "IOP32x",
48 .irq_ack = iop32x_irq_mask,
49 .irq_mask = iop32x_irq_mask,
50 .irq_unmask = iop32x_irq_unmask,
51 };
52
53 void __init iop32x_init_irq(void)
54 {
55 int i;
56
57 iop_init_cp6_handler();
58
59 intctl_write(0);
60 intstr_write(0);
61 if (machine_is_glantank() ||
62 machine_is_iq80321() ||
63 machine_is_iq31244() ||
64 machine_is_n2100() ||
65 machine_is_em7210())
66 *IOP3XX_PCIIRSR = 0x0f;
67
68 for (i = 0; i < NR_IRQS; i++) {
69 irq_set_chip_and_handler(i, &ext_chip, handle_level_irq);
70 irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);
71 }
72 }