1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * linux/arch/arm/mach-sa1100/pci-nanoengine.c
4 *
5 * PCI functions for BSE nanoEngine PCI
6 *
7 * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
8 */
9 #include <linux/kernel.h>
10 #include <linux/irq.h>
11 #include <linux/pci.h>
12
13 #include <asm/mach/pci.h>
14 #include <asm/mach-types.h>
15
16 #include <mach/nanoengine.h>
17 #include <mach/hardware.h>
18
19 static void __iomem *nanoengine_pci_map_bus(struct pci_bus *bus,
20 unsigned int devfn, int where)
21 {
22 if (bus->number != 0 || (devfn >> 3) != 0)
23 return NULL;
24
25 return (void __iomem *)NANO_PCI_CONFIG_SPACE_VIRT +
26 ((bus->number << 16) | (devfn << 8) | (where & ~3));
27 }
28
29 static struct pci_ops pci_nano_ops = {
30 .map_bus = nanoengine_pci_map_bus,
31 .read = pci_generic_config_read32,
32 .write = pci_generic_config_write32,
33 };
34
35 static int __init pci_nanoengine_map_irq(const struct pci_dev *dev, u8 slot,
36 u8 pin)
37 {
38 return NANOENGINE_IRQ_GPIO_PCI;
39 }
40
41 static struct resource pci_io_ports =
42 DEFINE_RES_IO_NAMED(0x400, 0x400, "PCI IO");
43
44 static struct resource pci_non_prefetchable_memory = {
45 .name = "PCI non-prefetchable",
46 .start = NANO_PCI_MEM_RW_PHYS,
47 /* nanoEngine documentation says there is a 1 Megabyte window here,
48 * but PCI reports just 128 + 8 kbytes. */
49 .end = NANO_PCI_MEM_RW_PHYS + NANO_PCI_MEM_RW_SIZE - 1,
50 /* .end = NANO_PCI_MEM_RW_PHYS + SZ_128K + SZ_8K - 1,*/
51 .flags = IORESOURCE_MEM,
52 };
53
54 /*
55 * nanoEngine PCI reports 1 Megabyte of prefetchable memory, but it
56 * overlaps with previously defined memory.
57 *
58 * Here is what happens:
59 *
60 # dmesg
61 ...
62 pci 0000:00:00.0: [8086:1209] type 0 class 0x000200
63 pci 0000:00:00.0: reg 10: [mem 0x00021000-0x00021fff]
64 pci 0000:00:00.0: reg 14: [io 0x0000-0x003f]
65 pci 0000:00:00.0: reg 18: [mem 0x00000000-0x0001ffff]
66 pci 0000:00:00.0: reg 30: [mem 0x00000000-0x000fffff pref]
67 pci 0000:00:00.0: supports D1 D2
68 pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot
69 pci 0000:00:00.0: PME# disabled
70 PCI: bus0: Fast back to back transfers enabled
71 pci 0000:00:00.0: BAR 6: can't assign mem pref (size 0x100000)
72 pci 0000:00:00.0: BAR 2: assigned [mem 0x18600000-0x1861ffff]
73 pci 0000:00:00.0: BAR 2: set to [mem 0x18600000-0x1861ffff] (PCI address [0x0-0x1ffff])
74 pci 0000:00:00.0: BAR 0: assigned [mem 0x18620000-0x18620fff]
75 pci 0000:00:00.0: BAR 0: set to [mem 0x18620000-0x18620fff] (PCI address [0x20000-0x20fff])
76 pci 0000:00:00.0: BAR 1: assigned [io 0x0400-0x043f]
77 pci 0000:00:00.0: BAR 1: set to [io 0x0400-0x043f] (PCI address [0x0-0x3f])
78 *
79 * On the other hand, if we do not request the prefetchable memory resource,
80 * linux will alloc it first and the two non-prefetchable memory areas that
81 * are our real interest will not be mapped. So we choose to map it to an
82 * unused area. It gets recognized as expansion ROM, but becomes disabled.
83 *
84 * Here is what happens then:
85 *
86 # dmesg
87 ...
88 pci 0000:00:00.0: [8086:1209] type 0 class 0x000200
89 pci 0000:00:00.0: reg 10: [mem 0x00021000-0x00021fff]
90 pci 0000:00:00.0: reg 14: [io 0x0000-0x003f]
91 pci 0000:00:00.0: reg 18: [mem 0x00000000-0x0001ffff]
92 pci 0000:00:00.0: reg 30: [mem 0x00000000-0x000fffff pref]
93 pci 0000:00:00.0: supports D1 D2
94 pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot
95 pci 0000:00:00.0: PME# disabled
96 PCI: bus0: Fast back to back transfers enabled
97 pci 0000:00:00.0: BAR 6: assigned [mem 0x78000000-0x780fffff pref]
98 pci 0000:00:00.0: BAR 2: assigned [mem 0x18600000-0x1861ffff]
99 pci 0000:00:00.0: BAR 2: set to [mem 0x18600000-0x1861ffff] (PCI address [0x0-0x1ffff])
100 pci 0000:00:00.0: BAR 0: assigned [mem 0x18620000-0x18620fff]
101 pci 0000:00:00.0: BAR 0: set to [mem 0x18620000-0x18620fff] (PCI address [0x20000-0x20fff])
102 pci 0000:00:00.0: BAR 1: assigned [io 0x0400-0x043f]
103 pci 0000:00:00.0: BAR 1: set to [io 0x0400-0x043f] (PCI address [0x0-0x3f])
104
105 # lspci -vv -s 0000:00:00.0
106 00:00.0 Class 0200: Device 8086:1209 (rev 09)
107 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
108 Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR+ <PERR+ INTx-
109 Latency: 0 (2000ns min, 14000ns max), Cache Line Size: 32 bytes
110 Interrupt: pin A routed to IRQ 0
111 Region 0: Memory at 18620000 (32-bit, non-prefetchable) [size=4K]
112 Region 1: I/O ports at 0400 [size=64]
113 Region 2: [virtual] Memory at 18600000 (32-bit, non-prefetchable) [size=128K]
114 [virtual] Expansion ROM at 78000000 [disabled] [size=1M]
115 Capabilities: [dc] Power Management version 2
116 Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
117 Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=2 PME-
118 Kernel driver in use: e100
119 Kernel modules: e100
120 *
121 */
122 static struct resource pci_prefetchable_memory = {
123 .name = "PCI prefetchable",
124 .start = 0x78000000,
125 .end = 0x78000000 + NANO_PCI_MEM_RW_SIZE - 1,
126 .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
127 };
128
129 static int __init pci_nanoengine_setup_resources(struct pci_sys_data *sys)
130 {
131 if (request_resource(&ioport_resource, &pci_io_ports)) {
132 printk(KERN_ERR "PCI: unable to allocate io port region\n");
133 return -EBUSY;
134 }
135 if (request_resource(&iomem_resource, &pci_non_prefetchable_memory)) {
136 release_resource(&pci_io_ports);
137 printk(KERN_ERR "PCI: unable to allocate non prefetchable\n");
138 return -EBUSY;
139 }
140 if (request_resource(&iomem_resource, &pci_prefetchable_memory)) {
141 release_resource(&pci_io_ports);
142 release_resource(&pci_non_prefetchable_memory);
143 printk(KERN_ERR "PCI: unable to allocate prefetchable\n");
144 return -EBUSY;
145 }
146 pci_add_resource_offset(&sys->resources, &pci_io_ports, sys->io_offset);
147 pci_add_resource_offset(&sys->resources,
148 &pci_non_prefetchable_memory, sys->mem_offset);
149 pci_add_resource_offset(&sys->resources,
150 &pci_prefetchable_memory, sys->mem_offset);
151
152 return 1;
153 }
154
155 int __init pci_nanoengine_setup(int nr, struct pci_sys_data *sys)
156 {
157 int ret = 0;
158
159 pcibios_min_io = 0;
160 pcibios_min_mem = 0;
161
162 if (nr == 0) {
163 sys->mem_offset = NANO_PCI_MEM_RW_PHYS;
164 sys->io_offset = 0x400;
165 ret = pci_nanoengine_setup_resources(sys);
166 /* Enable alternate memory bus master mode, see
167 * "Intel StrongARM SA1110 Developer's Manual",
168 * section 10.8, "Alternate Memory Bus Master Mode". */
169 GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
170 GAFR |= GPIO_MBGNT | GPIO_MBREQ;
171 TUCR |= TUCR_MBGPIO;
172 }
173
174 return ret;
175 }
176
177 static struct hw_pci nanoengine_pci __initdata = {
178 .map_irq = pci_nanoengine_map_irq,
179 .nr_controllers = 1,
180 .ops = &pci_nano_ops,
181 .setup = pci_nanoengine_setup,
182 };
183
184 static int __init nanoengine_pci_init(void)
185 {
186 if (machine_is_nanoengine())
187 pci_common_init(&nanoengine_pci);
188 return 0;
189 }
190
191 subsys_initcall(nanoengine_pci_init);