root/arch/arm/mach-omap1/include/mach/omap1510.h

INCLUDED FROM

   1 /*
   2  * Hardware definitions for TI OMAP1510 processor.
   3  *
   4  * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License as published by the
   8  * Free Software Foundation; either version 2 of the License, or (at your
   9  * option) any later version.
  10  *
  11  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  12  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  13  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  14  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  15  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  16  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  17  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  18  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  19  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  20  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  21  *
  22  * You should have received a copy of the  GNU General Public License along
  23  * with this program; if not, write  to the Free Software Foundation, Inc.,
  24  * 675 Mass Ave, Cambridge, MA 02139, USA.
  25  */
  26 
  27 #ifndef __ASM_ARCH_OMAP15XX_H
  28 #define __ASM_ARCH_OMAP15XX_H
  29 
  30 /*
  31  * ----------------------------------------------------------------------------
  32  * Base addresses
  33  * ----------------------------------------------------------------------------
  34  */
  35 
  36 /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
  37 
  38 #define OMAP1510_DSP_BASE       0xE0000000
  39 #define OMAP1510_DSP_SIZE       0x28000
  40 #define OMAP1510_DSP_START      0xE0000000
  41 
  42 #define OMAP1510_DSPREG_BASE    0xE1000000
  43 #define OMAP1510_DSPREG_SIZE    SZ_128K
  44 #define OMAP1510_DSPREG_START   0xE1000000
  45 
  46 #define OMAP1510_DSP_MMU_BASE   (0xfffed200)
  47 
  48 /*
  49  * ---------------------------------------------------------------------------
  50  *  OMAP-1510 FPGA
  51  * ---------------------------------------------------------------------------
  52  */
  53 #define OMAP1510_FPGA_BASE              0xE8000000              /* VA */
  54 #define OMAP1510_FPGA_SIZE              SZ_4K
  55 #define OMAP1510_FPGA_START             0x08000000              /* PA */
  56 
  57 /* Revision */
  58 #define OMAP1510_FPGA_REV_LOW                   IOMEM(OMAP1510_FPGA_BASE + 0x0)
  59 #define OMAP1510_FPGA_REV_HIGH                  IOMEM(OMAP1510_FPGA_BASE + 0x1)
  60 #define OMAP1510_FPGA_LCD_PANEL_CONTROL         IOMEM(OMAP1510_FPGA_BASE + 0x2)
  61 #define OMAP1510_FPGA_LED_DIGIT                 IOMEM(OMAP1510_FPGA_BASE + 0x3)
  62 #define INNOVATOR_FPGA_HID_SPI                  IOMEM(OMAP1510_FPGA_BASE + 0x4)
  63 #define OMAP1510_FPGA_POWER                     IOMEM(OMAP1510_FPGA_BASE + 0x5)
  64 
  65 /* Interrupt status */
  66 #define OMAP1510_FPGA_ISR_LO                    IOMEM(OMAP1510_FPGA_BASE + 0x6)
  67 #define OMAP1510_FPGA_ISR_HI                    IOMEM(OMAP1510_FPGA_BASE + 0x7)
  68 
  69 /* Interrupt mask */
  70 #define OMAP1510_FPGA_IMR_LO                    IOMEM(OMAP1510_FPGA_BASE + 0x8)
  71 #define OMAP1510_FPGA_IMR_HI                    IOMEM(OMAP1510_FPGA_BASE + 0x9)
  72 
  73 /* Reset registers */
  74 #define OMAP1510_FPGA_HOST_RESET                IOMEM(OMAP1510_FPGA_BASE + 0xa)
  75 #define OMAP1510_FPGA_RST                       IOMEM(OMAP1510_FPGA_BASE + 0xb)
  76 
  77 #define OMAP1510_FPGA_AUDIO                     IOMEM(OMAP1510_FPGA_BASE + 0xc)
  78 #define OMAP1510_FPGA_DIP                       IOMEM(OMAP1510_FPGA_BASE + 0xe)
  79 #define OMAP1510_FPGA_FPGA_IO                   IOMEM(OMAP1510_FPGA_BASE + 0xf)
  80 #define OMAP1510_FPGA_UART1                     IOMEM(OMAP1510_FPGA_BASE + 0x14)
  81 #define OMAP1510_FPGA_UART2                     IOMEM(OMAP1510_FPGA_BASE + 0x15)
  82 #define OMAP1510_FPGA_OMAP1510_STATUS           IOMEM(OMAP1510_FPGA_BASE + 0x16)
  83 #define OMAP1510_FPGA_BOARD_REV                 IOMEM(OMAP1510_FPGA_BASE + 0x18)
  84 #define INNOVATOR_FPGA_CAM_USB_CONTROL          IOMEM(OMAP1510_FPGA_BASE + 0x20c)
  85 #define OMAP1510P1_PPT_DATA                     IOMEM(OMAP1510_FPGA_BASE + 0x100)
  86 #define OMAP1510P1_PPT_STATUS                   IOMEM(OMAP1510_FPGA_BASE + 0x101)
  87 #define OMAP1510P1_PPT_CONTROL                  IOMEM(OMAP1510_FPGA_BASE + 0x102)
  88 
  89 #define OMAP1510_FPGA_TOUCHSCREEN               IOMEM(OMAP1510_FPGA_BASE + 0x204)
  90 
  91 #define INNOVATOR_FPGA_INFO                     IOMEM(OMAP1510_FPGA_BASE + 0x205)
  92 #define INNOVATOR_FPGA_LCD_BRIGHT_LO            IOMEM(OMAP1510_FPGA_BASE + 0x206)
  93 #define INNOVATOR_FPGA_LCD_BRIGHT_HI            IOMEM(OMAP1510_FPGA_BASE + 0x207)
  94 #define INNOVATOR_FPGA_LED_GRN_LO               IOMEM(OMAP1510_FPGA_BASE + 0x208)
  95 #define INNOVATOR_FPGA_LED_GRN_HI               IOMEM(OMAP1510_FPGA_BASE + 0x209)
  96 #define INNOVATOR_FPGA_LED_RED_LO               IOMEM(OMAP1510_FPGA_BASE + 0x20a)
  97 #define INNOVATOR_FPGA_LED_RED_HI               IOMEM(OMAP1510_FPGA_BASE + 0x20b)
  98 #define INNOVATOR_FPGA_EXP_CONTROL              IOMEM(OMAP1510_FPGA_BASE + 0x20d)
  99 #define INNOVATOR_FPGA_ISR2                     IOMEM(OMAP1510_FPGA_BASE + 0x20e)
 100 #define INNOVATOR_FPGA_IMR2                     IOMEM(OMAP1510_FPGA_BASE + 0x210)
 101 
 102 #define OMAP1510_FPGA_ETHR_START                (OMAP1510_FPGA_START + 0x300)
 103 
 104 /*
 105  * Power up Giga UART driver, turn on HID clock.
 106  * Turn off BT power, since we're not using it and it
 107  * draws power.
 108  */
 109 #define OMAP1510_FPGA_RESET_VALUE               0x42
 110 
 111 #define OMAP1510_FPGA_PCR_IF_PD0                (1 << 7)
 112 #define OMAP1510_FPGA_PCR_COM2_EN               (1 << 6)
 113 #define OMAP1510_FPGA_PCR_COM1_EN               (1 << 5)
 114 #define OMAP1510_FPGA_PCR_EXP_PD0               (1 << 4)
 115 #define OMAP1510_FPGA_PCR_EXP_PD1               (1 << 3)
 116 #define OMAP1510_FPGA_PCR_48MHZ_CLK             (1 << 2)
 117 #define OMAP1510_FPGA_PCR_4MHZ_CLK              (1 << 1)
 118 #define OMAP1510_FPGA_PCR_RSRVD_BIT0            (1 << 0)
 119 
 120 /*
 121  * Innovator/OMAP1510 FPGA HID register bit definitions
 122  */
 123 #define OMAP1510_FPGA_HID_SCLK  (1<<0)  /* output */
 124 #define OMAP1510_FPGA_HID_MOSI  (1<<1)  /* output */
 125 #define OMAP1510_FPGA_HID_nSS   (1<<2)  /* output 0/1 chip idle/select */
 126 #define OMAP1510_FPGA_HID_nHSUS (1<<3)  /* output 0/1 host active/suspended */
 127 #define OMAP1510_FPGA_HID_MISO  (1<<4)  /* input */
 128 #define OMAP1510_FPGA_HID_ATN   (1<<5)  /* input  0/1 chip idle/ATN */
 129 #define OMAP1510_FPGA_HID_rsrvd (1<<6)
 130 #define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */
 131 
 132 /* The FPGA IRQ is cascaded through GPIO_13 */
 133 #define OMAP1510_INT_FPGA               (IH_GPIO_BASE + 13)
 134 
 135 /* IRQ Numbers for interrupts muxed through the FPGA */
 136 #define OMAP1510_INT_FPGA_ATN           (OMAP_FPGA_IRQ_BASE + 0)
 137 #define OMAP1510_INT_FPGA_ACK           (OMAP_FPGA_IRQ_BASE + 1)
 138 #define OMAP1510_INT_FPGA2              (OMAP_FPGA_IRQ_BASE + 2)
 139 #define OMAP1510_INT_FPGA3              (OMAP_FPGA_IRQ_BASE + 3)
 140 #define OMAP1510_INT_FPGA4              (OMAP_FPGA_IRQ_BASE + 4)
 141 #define OMAP1510_INT_FPGA5              (OMAP_FPGA_IRQ_BASE + 5)
 142 #define OMAP1510_INT_FPGA6              (OMAP_FPGA_IRQ_BASE + 6)
 143 #define OMAP1510_INT_FPGA7              (OMAP_FPGA_IRQ_BASE + 7)
 144 #define OMAP1510_INT_FPGA8              (OMAP_FPGA_IRQ_BASE + 8)
 145 #define OMAP1510_INT_FPGA9              (OMAP_FPGA_IRQ_BASE + 9)
 146 #define OMAP1510_INT_FPGA10             (OMAP_FPGA_IRQ_BASE + 10)
 147 #define OMAP1510_INT_FPGA11             (OMAP_FPGA_IRQ_BASE + 11)
 148 #define OMAP1510_INT_FPGA12             (OMAP_FPGA_IRQ_BASE + 12)
 149 #define OMAP1510_INT_ETHER              (OMAP_FPGA_IRQ_BASE + 13)
 150 #define OMAP1510_INT_FPGAUART1          (OMAP_FPGA_IRQ_BASE + 14)
 151 #define OMAP1510_INT_FPGAUART2          (OMAP_FPGA_IRQ_BASE + 15)
 152 #define OMAP1510_INT_FPGA_TS            (OMAP_FPGA_IRQ_BASE + 16)
 153 #define OMAP1510_INT_FPGA17             (OMAP_FPGA_IRQ_BASE + 17)
 154 #define OMAP1510_INT_FPGA_CAM           (OMAP_FPGA_IRQ_BASE + 18)
 155 #define OMAP1510_INT_FPGA_RTC_A         (OMAP_FPGA_IRQ_BASE + 19)
 156 #define OMAP1510_INT_FPGA_RTC_B         (OMAP_FPGA_IRQ_BASE + 20)
 157 #define OMAP1510_INT_FPGA_CD            (OMAP_FPGA_IRQ_BASE + 21)
 158 #define OMAP1510_INT_FPGA22             (OMAP_FPGA_IRQ_BASE + 22)
 159 #define OMAP1510_INT_FPGA23             (OMAP_FPGA_IRQ_BASE + 23)
 160 
 161 #endif /*  __ASM_ARCH_OMAP15XX_H */
 162