root/arch/arm/mach-omap1/include/mach/irqs.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  *  arch/arm/plat-omap/include/mach/irqs.h
   4  *
   5  *  Copyright (C) Greg Lonnon 2001
   6  *  Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
   7  *
   8  * Copyright (C) 2009 Texas Instruments
   9  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  10  *
  11  * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
  12  *       are different.
  13  */
  14 
  15 #ifndef __ASM_ARCH_OMAP15XX_IRQS_H
  16 #define __ASM_ARCH_OMAP15XX_IRQS_H
  17 
  18 /*
  19  * IRQ numbers for interrupt handler 1
  20  *
  21  * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
  22  *
  23  */
  24 #define INT_CAMERA              (NR_IRQS_LEGACY + 1)
  25 #define INT_FIQ                 (NR_IRQS_LEGACY + 3)
  26 #define INT_RTDX                (NR_IRQS_LEGACY + 6)
  27 #define INT_DSP_MMU_ABORT       (NR_IRQS_LEGACY + 7)
  28 #define INT_HOST                (NR_IRQS_LEGACY + 8)
  29 #define INT_ABORT               (NR_IRQS_LEGACY + 9)
  30 #define INT_BRIDGE_PRIV         (NR_IRQS_LEGACY + 13)
  31 #define INT_GPIO_BANK1          (NR_IRQS_LEGACY + 14)
  32 #define INT_UART3               (NR_IRQS_LEGACY + 15)
  33 #define INT_TIMER3              (NR_IRQS_LEGACY + 16)
  34 #define INT_DMA_CH0_6           (NR_IRQS_LEGACY + 19)
  35 #define INT_DMA_CH1_7           (NR_IRQS_LEGACY + 20)
  36 #define INT_DMA_CH2_8           (NR_IRQS_LEGACY + 21)
  37 #define INT_DMA_CH3             (NR_IRQS_LEGACY + 22)
  38 #define INT_DMA_CH4             (NR_IRQS_LEGACY + 23)
  39 #define INT_DMA_CH5             (NR_IRQS_LEGACY + 24)
  40 #define INT_TIMER1              (NR_IRQS_LEGACY + 26)
  41 #define INT_WD_TIMER            (NR_IRQS_LEGACY + 27)
  42 #define INT_BRIDGE_PUB          (NR_IRQS_LEGACY + 28)
  43 #define INT_TIMER2              (NR_IRQS_LEGACY + 30)
  44 #define INT_LCD_CTRL            (NR_IRQS_LEGACY + 31)
  45 
  46 /*
  47  * OMAP-1510 specific IRQ numbers for interrupt handler 1
  48  */
  49 #define INT_1510_IH2_IRQ        (NR_IRQS_LEGACY + 0)
  50 #define INT_1510_RES2           (NR_IRQS_LEGACY + 2)
  51 #define INT_1510_SPI_TX         (NR_IRQS_LEGACY + 4)
  52 #define INT_1510_SPI_RX         (NR_IRQS_LEGACY + 5)
  53 #define INT_1510_DSP_MAILBOX1   (NR_IRQS_LEGACY + 10)
  54 #define INT_1510_DSP_MAILBOX2   (NR_IRQS_LEGACY + 11)
  55 #define INT_1510_RES12          (NR_IRQS_LEGACY + 12)
  56 #define INT_1510_LB_MMU         (NR_IRQS_LEGACY + 17)
  57 #define INT_1510_RES18          (NR_IRQS_LEGACY + 18)
  58 #define INT_1510_LOCAL_BUS      (NR_IRQS_LEGACY + 29)
  59 
  60 /*
  61  * OMAP-1610 specific IRQ numbers for interrupt handler 1
  62  */
  63 #define INT_1610_IH2_IRQ        INT_1510_IH2_IRQ
  64 #define INT_1610_IH2_FIQ        (NR_IRQS_LEGACY + 2)
  65 #define INT_1610_McBSP2_TX      (NR_IRQS_LEGACY + 4)
  66 #define INT_1610_McBSP2_RX      (NR_IRQS_LEGACY + 5)
  67 #define INT_1610_DSP_MAILBOX1   (NR_IRQS_LEGACY + 10)
  68 #define INT_1610_DSP_MAILBOX2   (NR_IRQS_LEGACY + 11)
  69 #define INT_1610_LCD_LINE       (NR_IRQS_LEGACY + 12)
  70 #define INT_1610_GPTIMER1       (NR_IRQS_LEGACY + 17)
  71 #define INT_1610_GPTIMER2       (NR_IRQS_LEGACY + 18)
  72 #define INT_1610_SSR_FIFO_0     (NR_IRQS_LEGACY + 29)
  73 
  74 /*
  75  * OMAP-7xx specific IRQ numbers for interrupt handler 1
  76  */
  77 #define INT_7XX_IH2_FIQ         (NR_IRQS_LEGACY + 0)
  78 #define INT_7XX_IH2_IRQ         (NR_IRQS_LEGACY + 1)
  79 #define INT_7XX_USB_NON_ISO     (NR_IRQS_LEGACY + 2)
  80 #define INT_7XX_USB_ISO         (NR_IRQS_LEGACY + 3)
  81 #define INT_7XX_ICR             (NR_IRQS_LEGACY + 4)
  82 #define INT_7XX_EAC             (NR_IRQS_LEGACY + 5)
  83 #define INT_7XX_GPIO_BANK1      (NR_IRQS_LEGACY + 6)
  84 #define INT_7XX_GPIO_BANK2      (NR_IRQS_LEGACY + 7)
  85 #define INT_7XX_GPIO_BANK3      (NR_IRQS_LEGACY + 8)
  86 #define INT_7XX_McBSP2TX        (NR_IRQS_LEGACY + 10)
  87 #define INT_7XX_McBSP2RX        (NR_IRQS_LEGACY + 11)
  88 #define INT_7XX_McBSP2RX_OVF    (NR_IRQS_LEGACY + 12)
  89 #define INT_7XX_LCD_LINE        (NR_IRQS_LEGACY + 14)
  90 #define INT_7XX_GSM_PROTECT     (NR_IRQS_LEGACY + 15)
  91 #define INT_7XX_TIMER3          (NR_IRQS_LEGACY + 16)
  92 #define INT_7XX_GPIO_BANK5      (NR_IRQS_LEGACY + 17)
  93 #define INT_7XX_GPIO_BANK6      (NR_IRQS_LEGACY + 18)
  94 #define INT_7XX_SPGIO_WR        (NR_IRQS_LEGACY + 29)
  95 
  96 /*
  97  * IRQ numbers for interrupt handler 2
  98  *
  99  * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
 100  */
 101 #define IH2_BASE                (NR_IRQS_LEGACY + 32)
 102 
 103 #define INT_KEYBOARD            (1 + IH2_BASE)
 104 #define INT_uWireTX             (2 + IH2_BASE)
 105 #define INT_uWireRX             (3 + IH2_BASE)
 106 #define INT_I2C                 (4 + IH2_BASE)
 107 #define INT_MPUIO               (5 + IH2_BASE)
 108 #define INT_USB_HHC_1           (6 + IH2_BASE)
 109 #define INT_McBSP3TX            (10 + IH2_BASE)
 110 #define INT_McBSP3RX            (11 + IH2_BASE)
 111 #define INT_McBSP1TX            (12 + IH2_BASE)
 112 #define INT_McBSP1RX            (13 + IH2_BASE)
 113 #define INT_UART1               (14 + IH2_BASE)
 114 #define INT_UART2               (15 + IH2_BASE)
 115 #define INT_BT_MCSI1TX          (16 + IH2_BASE)
 116 #define INT_BT_MCSI1RX          (17 + IH2_BASE)
 117 #define INT_SOSSI_MATCH         (19 + IH2_BASE)
 118 #define INT_USB_W2FC            (20 + IH2_BASE)
 119 #define INT_1WIRE               (21 + IH2_BASE)
 120 #define INT_OS_TIMER            (22 + IH2_BASE)
 121 #define INT_MMC                 (23 + IH2_BASE)
 122 #define INT_GAUGE_32K           (24 + IH2_BASE)
 123 #define INT_RTC_TIMER           (25 + IH2_BASE)
 124 #define INT_RTC_ALARM           (26 + IH2_BASE)
 125 #define INT_MEM_STICK           (27 + IH2_BASE)
 126 
 127 /*
 128  * OMAP-1510 specific IRQ numbers for interrupt handler 2
 129  */
 130 #define INT_1510_DSP_MMU        (28 + IH2_BASE)
 131 #define INT_1510_COM_SPI_RO     (31 + IH2_BASE)
 132 
 133 /*
 134  * OMAP-1610 specific IRQ numbers for interrupt handler 2
 135  */
 136 #define INT_1610_FAC            (0 + IH2_BASE)
 137 #define INT_1610_USB_HHC_2      (7 + IH2_BASE)
 138 #define INT_1610_USB_OTG        (8 + IH2_BASE)
 139 #define INT_1610_SoSSI          (9 + IH2_BASE)
 140 #define INT_1610_SoSSI_MATCH    (19 + IH2_BASE)
 141 #define INT_1610_DSP_MMU        (28 + IH2_BASE)
 142 #define INT_1610_McBSP2RX_OF    (31 + IH2_BASE)
 143 #define INT_1610_STI            (32 + IH2_BASE)
 144 #define INT_1610_STI_WAKEUP     (33 + IH2_BASE)
 145 #define INT_1610_GPTIMER3       (34 + IH2_BASE)
 146 #define INT_1610_GPTIMER4       (35 + IH2_BASE)
 147 #define INT_1610_GPTIMER5       (36 + IH2_BASE)
 148 #define INT_1610_GPTIMER6       (37 + IH2_BASE)
 149 #define INT_1610_GPTIMER7       (38 + IH2_BASE)
 150 #define INT_1610_GPTIMER8       (39 + IH2_BASE)
 151 #define INT_1610_GPIO_BANK2     (40 + IH2_BASE)
 152 #define INT_1610_GPIO_BANK3     (41 + IH2_BASE)
 153 #define INT_1610_MMC2           (42 + IH2_BASE)
 154 #define INT_1610_CF             (43 + IH2_BASE)
 155 #define INT_1610_WAKE_UP_REQ    (46 + IH2_BASE)
 156 #define INT_1610_GPIO_BANK4     (48 + IH2_BASE)
 157 #define INT_1610_SPI            (49 + IH2_BASE)
 158 #define INT_1610_DMA_CH6        (53 + IH2_BASE)
 159 #define INT_1610_DMA_CH7        (54 + IH2_BASE)
 160 #define INT_1610_DMA_CH8        (55 + IH2_BASE)
 161 #define INT_1610_DMA_CH9        (56 + IH2_BASE)
 162 #define INT_1610_DMA_CH10       (57 + IH2_BASE)
 163 #define INT_1610_DMA_CH11       (58 + IH2_BASE)
 164 #define INT_1610_DMA_CH12       (59 + IH2_BASE)
 165 #define INT_1610_DMA_CH13       (60 + IH2_BASE)
 166 #define INT_1610_DMA_CH14       (61 + IH2_BASE)
 167 #define INT_1610_DMA_CH15       (62 + IH2_BASE)
 168 #define INT_1610_NAND           (63 + IH2_BASE)
 169 #define INT_1610_SHA1MD5        (91 + IH2_BASE)
 170 
 171 /*
 172  * OMAP-7xx specific IRQ numbers for interrupt handler 2
 173  */
 174 #define INT_7XX_HW_ERRORS       (0 + IH2_BASE)
 175 #define INT_7XX_NFIQ_PWR_FAIL   (1 + IH2_BASE)
 176 #define INT_7XX_CFCD            (2 + IH2_BASE)
 177 #define INT_7XX_CFIREQ          (3 + IH2_BASE)
 178 #define INT_7XX_I2C             (4 + IH2_BASE)
 179 #define INT_7XX_PCC             (5 + IH2_BASE)
 180 #define INT_7XX_MPU_EXT_NIRQ    (6 + IH2_BASE)
 181 #define INT_7XX_SPI_100K_1      (7 + IH2_BASE)
 182 #define INT_7XX_SYREN_SPI       (8 + IH2_BASE)
 183 #define INT_7XX_VLYNQ           (9 + IH2_BASE)
 184 #define INT_7XX_GPIO_BANK4      (10 + IH2_BASE)
 185 #define INT_7XX_McBSP1TX        (11 + IH2_BASE)
 186 #define INT_7XX_McBSP1RX        (12 + IH2_BASE)
 187 #define INT_7XX_McBSP1RX_OF     (13 + IH2_BASE)
 188 #define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
 189 #define INT_7XX_UART_MODEM_1    (15 + IH2_BASE)
 190 #define INT_7XX_MCSI            (16 + IH2_BASE)
 191 #define INT_7XX_uWireTX         (17 + IH2_BASE)
 192 #define INT_7XX_uWireRX         (18 + IH2_BASE)
 193 #define INT_7XX_SMC_CD          (19 + IH2_BASE)
 194 #define INT_7XX_SMC_IREQ        (20 + IH2_BASE)
 195 #define INT_7XX_HDQ_1WIRE       (21 + IH2_BASE)
 196 #define INT_7XX_TIMER32K        (22 + IH2_BASE)
 197 #define INT_7XX_MMC_SDIO        (23 + IH2_BASE)
 198 #define INT_7XX_UPLD            (24 + IH2_BASE)
 199 #define INT_7XX_USB_HHC_1       (27 + IH2_BASE)
 200 #define INT_7XX_USB_HHC_2       (28 + IH2_BASE)
 201 #define INT_7XX_USB_GENI        (29 + IH2_BASE)
 202 #define INT_7XX_USB_OTG         (30 + IH2_BASE)
 203 #define INT_7XX_CAMERA_IF       (31 + IH2_BASE)
 204 #define INT_7XX_RNG             (32 + IH2_BASE)
 205 #define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
 206 #define INT_7XX_DBB_RF_EN       (34 + IH2_BASE)
 207 #define INT_7XX_MPUIO_KEYPAD    (35 + IH2_BASE)
 208 #define INT_7XX_SHA1_MD5        (36 + IH2_BASE)
 209 #define INT_7XX_SPI_100K_2      (37 + IH2_BASE)
 210 #define INT_7XX_RNG_IDLE        (38 + IH2_BASE)
 211 #define INT_7XX_MPUIO           (39 + IH2_BASE)
 212 #define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF        (40 + IH2_BASE)
 213 #define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
 214 #define INT_7XX_LLPC_OE_RISING  (42 + IH2_BASE)
 215 #define INT_7XX_LLPC_VSYNC      (43 + IH2_BASE)
 216 #define INT_7XX_WAKE_UP_REQ     (46 + IH2_BASE)
 217 #define INT_7XX_DMA_CH6         (53 + IH2_BASE)
 218 #define INT_7XX_DMA_CH7         (54 + IH2_BASE)
 219 #define INT_7XX_DMA_CH8         (55 + IH2_BASE)
 220 #define INT_7XX_DMA_CH9         (56 + IH2_BASE)
 221 #define INT_7XX_DMA_CH10        (57 + IH2_BASE)
 222 #define INT_7XX_DMA_CH11        (58 + IH2_BASE)
 223 #define INT_7XX_DMA_CH12        (59 + IH2_BASE)
 224 #define INT_7XX_DMA_CH13        (60 + IH2_BASE)
 225 #define INT_7XX_DMA_CH14        (61 + IH2_BASE)
 226 #define INT_7XX_DMA_CH15        (62 + IH2_BASE)
 227 #define INT_7XX_NAND            (63 + IH2_BASE)
 228 
 229 /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
 230  * 16 MPUIO lines */
 231 #define OMAP_MAX_GPIO_LINES     192
 232 #define IH_GPIO_BASE            (128 + IH2_BASE)
 233 #define IH_MPUIO_BASE           (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
 234 #define OMAP_IRQ_END            (IH_MPUIO_BASE + 16)
 235 
 236 /* External FPGA handles interrupts on Innovator boards */
 237 #define OMAP_FPGA_IRQ_BASE      (OMAP_IRQ_END)
 238 #ifdef  CONFIG_MACH_OMAP_INNOVATOR
 239 #define OMAP_FPGA_NR_IRQS       24
 240 #else
 241 #define OMAP_FPGA_NR_IRQS       0
 242 #endif
 243 #define OMAP_FPGA_IRQ_END       (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
 244 
 245 #define OMAP_IRQ_BIT(irq)       (1 << ((irq - NR_IRQS_LEGACY) % 32))
 246 
 247 #ifdef CONFIG_FIQ
 248 #define FIQ_START               1024
 249 #endif
 250 
 251 #endif