This source file includes following definitions.
- GPIO_OUT
- GPIO_IO_CONF
- GPIO_BLINK_EN
- GPIO_IN_POL
- GPIO_DATA_IN
- GPIO_EDGE_CAUSE
- GPIO_EDGE_MASK
- GPIO_LEVEL_MASK
- __set_direction
- __set_level
- __set_blinking
- orion_gpio_is_valid
- orion_gpio_request
- orion_gpio_direction_input
- orion_gpio_get
- orion_gpio_direction_output
- orion_gpio_set
- orion_gpio_to_irq
- orion_gpio_chip_find
- orion_gpio_set_unused
- orion_gpio_set_valid
- orion_gpio_set_blink
- orion_gpio_led_blink_set
- gpio_irq_set_type
- gpio_irq_handler
- orion_gpio_dbg_show
- orion_gpio_unmask_irq
- orion_gpio_mask_irq
- orion_gpio_init
1
2
3
4
5
6
7
8
9
10
11 #define DEBUG
12
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/irq.h>
16 #include <linux/irqdomain.h>
17 #include <linux/module.h>
18 #include <linux/spinlock.h>
19 #include <linux/bitops.h>
20 #include <linux/io.h>
21 #include <linux/gpio.h>
22 #include <linux/leds.h>
23 #include <linux/of.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_address.h>
26 #include <plat/orion-gpio.h>
27
28
29
30
31 #define GPIO_OUT_OFF 0x0000
32 #define GPIO_IO_CONF_OFF 0x0004
33 #define GPIO_BLINK_EN_OFF 0x0008
34 #define GPIO_IN_POL_OFF 0x000c
35 #define GPIO_DATA_IN_OFF 0x0010
36 #define GPIO_EDGE_CAUSE_OFF 0x0014
37 #define GPIO_EDGE_MASK_OFF 0x0018
38 #define GPIO_LEVEL_MASK_OFF 0x001c
39
40 struct orion_gpio_chip {
41 struct gpio_chip chip;
42 spinlock_t lock;
43 void __iomem *base;
44 unsigned long valid_input;
45 unsigned long valid_output;
46 int mask_offset;
47 int secondary_irq_base;
48 struct irq_domain *domain;
49 };
50
51 static void __iomem *GPIO_OUT(struct orion_gpio_chip *ochip)
52 {
53 return ochip->base + GPIO_OUT_OFF;
54 }
55
56 static void __iomem *GPIO_IO_CONF(struct orion_gpio_chip *ochip)
57 {
58 return ochip->base + GPIO_IO_CONF_OFF;
59 }
60
61 static void __iomem *GPIO_BLINK_EN(struct orion_gpio_chip *ochip)
62 {
63 return ochip->base + GPIO_BLINK_EN_OFF;
64 }
65
66 static void __iomem *GPIO_IN_POL(struct orion_gpio_chip *ochip)
67 {
68 return ochip->base + GPIO_IN_POL_OFF;
69 }
70
71 static void __iomem *GPIO_DATA_IN(struct orion_gpio_chip *ochip)
72 {
73 return ochip->base + GPIO_DATA_IN_OFF;
74 }
75
76 static void __iomem *GPIO_EDGE_CAUSE(struct orion_gpio_chip *ochip)
77 {
78 return ochip->base + GPIO_EDGE_CAUSE_OFF;
79 }
80
81 static void __iomem *GPIO_EDGE_MASK(struct orion_gpio_chip *ochip)
82 {
83 return ochip->base + ochip->mask_offset + GPIO_EDGE_MASK_OFF;
84 }
85
86 static void __iomem *GPIO_LEVEL_MASK(struct orion_gpio_chip *ochip)
87 {
88 return ochip->base + ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
89 }
90
91
92 static struct orion_gpio_chip orion_gpio_chips[2];
93 static int orion_gpio_chip_count;
94
95 static inline void
96 __set_direction(struct orion_gpio_chip *ochip, unsigned pin, int input)
97 {
98 u32 u;
99
100 u = readl(GPIO_IO_CONF(ochip));
101 if (input)
102 u |= 1 << pin;
103 else
104 u &= ~(1 << pin);
105 writel(u, GPIO_IO_CONF(ochip));
106 }
107
108 static void __set_level(struct orion_gpio_chip *ochip, unsigned pin, int high)
109 {
110 u32 u;
111
112 u = readl(GPIO_OUT(ochip));
113 if (high)
114 u |= 1 << pin;
115 else
116 u &= ~(1 << pin);
117 writel(u, GPIO_OUT(ochip));
118 }
119
120 static inline void
121 __set_blinking(struct orion_gpio_chip *ochip, unsigned pin, int blink)
122 {
123 u32 u;
124
125 u = readl(GPIO_BLINK_EN(ochip));
126 if (blink)
127 u |= 1 << pin;
128 else
129 u &= ~(1 << pin);
130 writel(u, GPIO_BLINK_EN(ochip));
131 }
132
133 static inline int
134 orion_gpio_is_valid(struct orion_gpio_chip *ochip, unsigned pin, int mode)
135 {
136 if (pin >= ochip->chip.ngpio)
137 goto err_out;
138
139 if ((mode & GPIO_INPUT_OK) && !test_bit(pin, &ochip->valid_input))
140 goto err_out;
141
142 if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, &ochip->valid_output))
143 goto err_out;
144
145 return 1;
146
147 err_out:
148 pr_debug("%s: invalid GPIO %d\n", __func__, pin);
149 return false;
150 }
151
152
153
154
155 static int orion_gpio_request(struct gpio_chip *chip, unsigned pin)
156 {
157 struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
158
159 if (orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK) ||
160 orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
161 return 0;
162
163 return -EINVAL;
164 }
165
166 static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
167 {
168 struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
169 unsigned long flags;
170
171 if (!orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK))
172 return -EINVAL;
173
174 spin_lock_irqsave(&ochip->lock, flags);
175 __set_direction(ochip, pin, 1);
176 spin_unlock_irqrestore(&ochip->lock, flags);
177
178 return 0;
179 }
180
181 static int orion_gpio_get(struct gpio_chip *chip, unsigned pin)
182 {
183 struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
184 int val;
185
186 if (readl(GPIO_IO_CONF(ochip)) & (1 << pin)) {
187 val = readl(GPIO_DATA_IN(ochip)) ^ readl(GPIO_IN_POL(ochip));
188 } else {
189 val = readl(GPIO_OUT(ochip));
190 }
191
192 return (val >> pin) & 1;
193 }
194
195 static int
196 orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int value)
197 {
198 struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
199 unsigned long flags;
200
201 if (!orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
202 return -EINVAL;
203
204 spin_lock_irqsave(&ochip->lock, flags);
205 __set_blinking(ochip, pin, 0);
206 __set_level(ochip, pin, value);
207 __set_direction(ochip, pin, 0);
208 spin_unlock_irqrestore(&ochip->lock, flags);
209
210 return 0;
211 }
212
213 static void orion_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
214 {
215 struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
216 unsigned long flags;
217
218 spin_lock_irqsave(&ochip->lock, flags);
219 __set_level(ochip, pin, value);
220 spin_unlock_irqrestore(&ochip->lock, flags);
221 }
222
223 static int orion_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
224 {
225 struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
226
227 return irq_create_mapping(ochip->domain,
228 ochip->secondary_irq_base + pin);
229 }
230
231
232
233
234 static struct orion_gpio_chip *orion_gpio_chip_find(int pin)
235 {
236 int i;
237
238 for (i = 0; i < orion_gpio_chip_count; i++) {
239 struct orion_gpio_chip *ochip = orion_gpio_chips + i;
240 struct gpio_chip *chip = &ochip->chip;
241
242 if (pin >= chip->base && pin < chip->base + chip->ngpio)
243 return ochip;
244 }
245
246 return NULL;
247 }
248
249 void __init orion_gpio_set_unused(unsigned pin)
250 {
251 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
252
253 if (ochip == NULL)
254 return;
255
256 pin -= ochip->chip.base;
257
258
259 __set_level(ochip, pin, 0);
260 __set_direction(ochip, pin, 0);
261 }
262
263 void __init orion_gpio_set_valid(unsigned pin, int mode)
264 {
265 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
266
267 if (ochip == NULL)
268 return;
269
270 pin -= ochip->chip.base;
271
272 if (mode == 1)
273 mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
274
275 if (mode & GPIO_INPUT_OK)
276 __set_bit(pin, &ochip->valid_input);
277 else
278 __clear_bit(pin, &ochip->valid_input);
279
280 if (mode & GPIO_OUTPUT_OK)
281 __set_bit(pin, &ochip->valid_output);
282 else
283 __clear_bit(pin, &ochip->valid_output);
284 }
285
286 void orion_gpio_set_blink(unsigned pin, int blink)
287 {
288 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
289 unsigned long flags;
290
291 if (ochip == NULL)
292 return;
293
294 spin_lock_irqsave(&ochip->lock, flags);
295 __set_level(ochip, pin & 31, 0);
296 __set_blinking(ochip, pin & 31, blink);
297 spin_unlock_irqrestore(&ochip->lock, flags);
298 }
299 EXPORT_SYMBOL(orion_gpio_set_blink);
300
301 #define ORION_BLINK_HALF_PERIOD 100
302
303 int orion_gpio_led_blink_set(struct gpio_desc *desc, int state,
304 unsigned long *delay_on, unsigned long *delay_off)
305 {
306 unsigned gpio = desc_to_gpio(desc);
307
308 if (delay_on && delay_off && !*delay_on && !*delay_off)
309 *delay_on = *delay_off = ORION_BLINK_HALF_PERIOD;
310
311 switch (state) {
312 case GPIO_LED_NO_BLINK_LOW:
313 case GPIO_LED_NO_BLINK_HIGH:
314 orion_gpio_set_blink(gpio, 0);
315 gpio_set_value(gpio, state);
316 break;
317 case GPIO_LED_BLINK:
318 orion_gpio_set_blink(gpio, 1);
319 }
320 return 0;
321 }
322 EXPORT_SYMBOL_GPL(orion_gpio_led_blink_set);
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351 static int gpio_irq_set_type(struct irq_data *d, u32 type)
352 {
353 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
354 struct irq_chip_type *ct = irq_data_get_chip_type(d);
355 struct orion_gpio_chip *ochip = gc->private;
356 int pin;
357 u32 u;
358
359 pin = d->hwirq - ochip->secondary_irq_base;
360
361 u = readl(GPIO_IO_CONF(ochip)) & (1 << pin);
362 if (!u) {
363 return -EINVAL;
364 }
365
366 type &= IRQ_TYPE_SENSE_MASK;
367 if (type == IRQ_TYPE_NONE)
368 return -EINVAL;
369
370
371 if (!(ct->type & type))
372 if (irq_setup_alt_chip(d, type))
373 return -EINVAL;
374
375
376
377
378 if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) {
379 u = readl(GPIO_IN_POL(ochip));
380 u &= ~(1 << pin);
381 writel(u, GPIO_IN_POL(ochip));
382 } else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) {
383 u = readl(GPIO_IN_POL(ochip));
384 u |= 1 << pin;
385 writel(u, GPIO_IN_POL(ochip));
386 } else if (type == IRQ_TYPE_EDGE_BOTH) {
387 u32 v;
388
389 v = readl(GPIO_IN_POL(ochip)) ^ readl(GPIO_DATA_IN(ochip));
390
391
392
393
394 u = readl(GPIO_IN_POL(ochip));
395 if (v & (1 << pin))
396 u |= 1 << pin;
397 else
398 u &= ~(1 << pin);
399 writel(u, GPIO_IN_POL(ochip));
400 }
401 return 0;
402 }
403
404 static void gpio_irq_handler(struct irq_desc *desc)
405 {
406 struct orion_gpio_chip *ochip = irq_desc_get_handler_data(desc);
407 u32 cause, type;
408 int i;
409
410 if (ochip == NULL)
411 return;
412
413 cause = readl(GPIO_DATA_IN(ochip)) & readl(GPIO_LEVEL_MASK(ochip));
414 cause |= readl(GPIO_EDGE_CAUSE(ochip)) & readl(GPIO_EDGE_MASK(ochip));
415
416 for (i = 0; i < ochip->chip.ngpio; i++) {
417 int irq;
418
419 irq = ochip->secondary_irq_base + i;
420
421 if (!(cause & (1 << i)))
422 continue;
423
424 type = irq_get_trigger_type(irq);
425 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
426
427 u32 polarity;
428
429 polarity = readl(GPIO_IN_POL(ochip));
430 polarity ^= 1 << i;
431 writel(polarity, GPIO_IN_POL(ochip));
432 }
433 generic_handle_irq(irq);
434 }
435 }
436
437 #ifdef CONFIG_DEBUG_FS
438 #include <linux/seq_file.h>
439
440 static void orion_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
441 {
442
443 struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
444 u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
445 int i;
446
447 out = readl_relaxed(GPIO_OUT(ochip));
448 io_conf = readl_relaxed(GPIO_IO_CONF(ochip));
449 blink = readl_relaxed(GPIO_BLINK_EN(ochip));
450 in_pol = readl_relaxed(GPIO_IN_POL(ochip));
451 data_in = readl_relaxed(GPIO_DATA_IN(ochip));
452 cause = readl_relaxed(GPIO_EDGE_CAUSE(ochip));
453 edg_msk = readl_relaxed(GPIO_EDGE_MASK(ochip));
454 lvl_msk = readl_relaxed(GPIO_LEVEL_MASK(ochip));
455
456 for (i = 0; i < chip->ngpio; i++) {
457 const char *label;
458 u32 msk;
459 bool is_out;
460
461 label = gpiochip_is_requested(chip, i);
462 if (!label)
463 continue;
464
465 msk = 1 << i;
466 is_out = !(io_conf & msk);
467
468 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
469
470 if (is_out) {
471 seq_printf(s, " out %s %s\n",
472 out & msk ? "hi" : "lo",
473 blink & msk ? "(blink )" : "");
474 continue;
475 }
476
477 seq_printf(s, " in %s (act %s) - IRQ",
478 (data_in ^ in_pol) & msk ? "hi" : "lo",
479 in_pol & msk ? "lo" : "hi");
480 if (!((edg_msk | lvl_msk) & msk)) {
481 seq_puts(s, " disabled\n");
482 continue;
483 }
484 if (edg_msk & msk)
485 seq_puts(s, " edge ");
486 if (lvl_msk & msk)
487 seq_puts(s, " level");
488 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear ");
489 }
490 }
491 #else
492 #define orion_gpio_dbg_show NULL
493 #endif
494
495 static void orion_gpio_unmask_irq(struct irq_data *d)
496 {
497 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
498 struct irq_chip_type *ct = irq_data_get_chip_type(d);
499 u32 reg_val;
500 u32 mask = d->mask;
501
502 irq_gc_lock(gc);
503 reg_val = irq_reg_readl(gc, ct->regs.mask);
504 reg_val |= mask;
505 irq_reg_writel(gc, reg_val, ct->regs.mask);
506 irq_gc_unlock(gc);
507 }
508
509 static void orion_gpio_mask_irq(struct irq_data *d)
510 {
511 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
512 struct irq_chip_type *ct = irq_data_get_chip_type(d);
513 u32 mask = d->mask;
514 u32 reg_val;
515
516 irq_gc_lock(gc);
517 reg_val = irq_reg_readl(gc, ct->regs.mask);
518 reg_val &= ~mask;
519 irq_reg_writel(gc, reg_val, ct->regs.mask);
520 irq_gc_unlock(gc);
521 }
522
523 void __init orion_gpio_init(struct device_node *np,
524 int gpio_base, int ngpio,
525 void __iomem *base, int mask_offset,
526 int secondary_irq_base,
527 int irqs[4])
528 {
529 struct orion_gpio_chip *ochip;
530 struct irq_chip_generic *gc;
531 struct irq_chip_type *ct;
532 char gc_label[16];
533 int i;
534
535 if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips))
536 return;
537
538 snprintf(gc_label, sizeof(gc_label), "orion_gpio%d",
539 orion_gpio_chip_count);
540
541 ochip = orion_gpio_chips + orion_gpio_chip_count;
542 ochip->chip.label = kstrdup(gc_label, GFP_KERNEL);
543 ochip->chip.request = orion_gpio_request;
544 ochip->chip.direction_input = orion_gpio_direction_input;
545 ochip->chip.get = orion_gpio_get;
546 ochip->chip.direction_output = orion_gpio_direction_output;
547 ochip->chip.set = orion_gpio_set;
548 ochip->chip.to_irq = orion_gpio_to_irq;
549 ochip->chip.base = gpio_base;
550 ochip->chip.ngpio = ngpio;
551 ochip->chip.can_sleep = 0;
552 #ifdef CONFIG_OF
553 ochip->chip.of_node = np;
554 #endif
555 ochip->chip.dbg_show = orion_gpio_dbg_show;
556
557 spin_lock_init(&ochip->lock);
558 ochip->base = (void __iomem *)base;
559 ochip->valid_input = 0;
560 ochip->valid_output = 0;
561 ochip->mask_offset = mask_offset;
562 ochip->secondary_irq_base = secondary_irq_base;
563
564 gpiochip_add_data(&ochip->chip, ochip);
565
566
567
568
569 writel(0, GPIO_EDGE_CAUSE(ochip));
570 writel(0, GPIO_EDGE_MASK(ochip));
571 writel(0, GPIO_LEVEL_MASK(ochip));
572
573
574
575
576
577 for (i = 0; i < 4; i++) {
578 if (irqs[i]) {
579 irq_set_chained_handler_and_data(irqs[i],
580 gpio_irq_handler,
581 ochip);
582 }
583 }
584
585 gc = irq_alloc_generic_chip("orion_gpio_irq", 2,
586 secondary_irq_base,
587 ochip->base, handle_level_irq);
588 gc->private = ochip;
589 ct = gc->chip_types;
590 ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
591 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
592 ct->chip.irq_mask = orion_gpio_mask_irq;
593 ct->chip.irq_unmask = orion_gpio_unmask_irq;
594 ct->chip.irq_set_type = gpio_irq_set_type;
595 ct->chip.name = ochip->chip.label;
596
597 ct++;
598 ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF;
599 ct->regs.ack = GPIO_EDGE_CAUSE_OFF;
600 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
601 ct->chip.irq_ack = irq_gc_ack_clr_bit;
602 ct->chip.irq_mask = orion_gpio_mask_irq;
603 ct->chip.irq_unmask = orion_gpio_unmask_irq;
604 ct->chip.irq_set_type = gpio_irq_set_type;
605 ct->handler = handle_edge_irq;
606 ct->chip.name = ochip->chip.label;
607
608 irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
609 IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
610
611
612 ochip->domain = irq_domain_add_legacy(np,
613 ochip->chip.ngpio,
614 ochip->secondary_irq_base,
615 ochip->secondary_irq_base,
616 &irq_domain_simple_ops,
617 ochip);
618 if (!ochip->domain)
619 panic("%s: couldn't allocate irq domain (DT).\n",
620 ochip->chip.label);
621
622 orion_gpio_chip_count++;
623 }