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12 #include <linux/linkage.h>
13
14 #include <asm/assembler.h>
15 #include <asm/cache.h>
16 #include <asm/cp15.h>
17 #include <asm/hardware/cache-l2x0.h>
18
19 #include "iomap.h"
20 #include "sleep.h"
21
22 #define CLK_RESET_CCLK_BURST 0x20
23 #define CLK_RESET_CCLK_DIVIDER 0x24
24
25 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
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33 ENTRY(tegra_disable_clean_inv_dcache)
34 stmfd sp!, {r0, r4-r5, r7, r9-r11, lr}
35 dmb @ ensure ordering
36
37
38 mrc p15, 0, r2, c1, c0, 0
39 tst r2, #CR_C @ see tegra_sleep_cpu()
40 bic r2, r2, #CR_C
41 mcrne p15, 0, r2, c1, c0, 0
42 isb
43
44
45 cmp r0, #TEGRA_FLUSH_CACHE_ALL
46 blne v7_flush_dcache_louis
47 bleq v7_flush_dcache_all
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50 exit_smp r4, r5
51
52 ldmfd sp!, {r0, r4-r5, r7, r9-r11, pc}
53 ENDPROC(tegra_disable_clean_inv_dcache)
54 #endif
55
56 #ifdef CONFIG_PM_SLEEP
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61
62 ENTRY(tegra_init_l2_for_a15)
63 mrc p15, 0, r0, c0, c0, 5
64 ubfx r0, r0, #8, #4
65 tst r0, #1 @ only need for cluster 0
66 bne _exit_init_l2_a15
67
68 mrc p15, 0x1, r0, c9, c0, 2
69 and r0, r0, #7
70 cmp r0, #2
71 bicne r0, r0, #7
72 orrne r0, r0, #2
73 mcrne p15, 0x1, r0, c9, c0, 2
74 _exit_init_l2_a15:
75
76 ret lr
77 ENDPROC(tegra_init_l2_for_a15)
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85 ENTRY(tegra_sleep_cpu_finish)
86 mov r4, r0
87
88 mov r0, #TEGRA_FLUSH_CACHE_ALL
89 bl tegra_disable_clean_inv_dcache
90
91 mov r0, r4
92 mov32 r6, tegra_tear_down_cpu
93 ldr r1, [r6]
94 add r1, r1, r0
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96 mov32 r3, tegra_shut_off_mmu
97 add r3, r3, r0
98 mov r0, r1
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100 ret r3
101 ENDPROC(tegra_sleep_cpu_finish)
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111 .align L1_CACHE_SHIFT
112 .pushsection .idmap.text, "ax"
113 ENTRY(tegra_shut_off_mmu)
114 mrc p15, 0, r3, c1, c0, 0
115 movw r2, #CR_I | CR_Z | CR_C | CR_M
116 bic r3, r3, r2
117 dsb
118 mcr p15, 0, r3, c1, c0, 0
119 isb
120 #ifdef CONFIG_CACHE_L2X0
121
122 check_cpu_part_num 0xc09, r9, r10
123 retne r0
124
125 mov32 r2, TEGRA_ARM_PERIF_BASE + 0x3000
126 ldr r3, [r2, #L2X0_CTRL]
127 tst r3, #L2X0_CTRL_EN @ see tegra_sleep_cpu()
128 mov r3, #0
129 strne r3, [r2, #L2X0_CTRL]
130 #endif
131 ret r0
132 ENDPROC(tegra_shut_off_mmu)
133 .popsection
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139
140 ENTRY(tegra_switch_cpu_to_pllp)
141
142 mov32 r5, TEGRA_CLK_RESET_BASE
143 mov r0, #(2 << 28) @ burst policy = run mode
144 orr r0, r0, #(4 << 4) @ use PLLP in run mode burst
145 str r0, [r5, #CLK_RESET_CCLK_BURST]
146 mov r0, #0
147 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
148 ret lr
149 ENDPROC(tegra_switch_cpu_to_pllp)
150 #endif