arch/arm/mach-ux500/db8500-regs.h

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   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) ST-Ericsson SA 2010
   4  */
   5 
   6 #ifndef __MACH_DB8500_REGS_H
   7 #define __MACH_DB8500_REGS_H
   8 
   9 /* Base address and bank offsets for ESRAM */
  10 #define U8500_ESRAM_BASE        0x40000000
  11 #define U8500_ESRAM_BANK_SIZE   0x00020000
  12 #define U8500_ESRAM_BANK0       U8500_ESRAM_BASE
  13 #define U8500_ESRAM_BANK1       (U8500_ESRAM_BASE + U8500_ESRAM_BANK_SIZE)
  14 #define U8500_ESRAM_BANK2       (U8500_ESRAM_BANK1 + U8500_ESRAM_BANK_SIZE)
  15 #define U8500_ESRAM_BANK3       (U8500_ESRAM_BANK2 + U8500_ESRAM_BANK_SIZE)
  16 #define U8500_ESRAM_BANK4       (U8500_ESRAM_BANK3 + U8500_ESRAM_BANK_SIZE)
  17 /*
  18  * on V1 DMA uses 4KB for logical parameters position is right after the 64KB
  19  * reserved for security
  20  */
  21 #define U8500_ESRAM_DMA_LCPA_OFFSET     0x10000
  22 
  23 #define U8500_DMA_LCPA_BASE    (U8500_ESRAM_BANK0 + U8500_ESRAM_DMA_LCPA_OFFSET)
  24 
  25 /* This address fulfills the 256k alignment requirement of the lcla base */
  26 #define U8500_DMA_LCLA_BASE     U8500_ESRAM_BANK4
  27 
  28 #define U8500_PER3_BASE         0x80000000
  29 #define U8500_STM_BASE          0x80100000
  30 #define U8500_STM_REG_BASE      (U8500_STM_BASE + 0xF000)
  31 #define U8500_PER2_BASE         0x80110000
  32 #define U8500_PER1_BASE         0x80120000
  33 #define U8500_B2R2_BASE         0x80130000
  34 #define U8500_HSEM_BASE         0x80140000
  35 #define U8500_PER4_BASE         0x80150000
  36 #define U8500_TPIU_BASE         0x80190000
  37 #define U8500_ICN_BASE          0x81000000
  38 
  39 #define U8500_BOOT_ROM_BASE     0x90000000
  40 /* ASIC ID is at 0xbf4 offset within this region */
  41 #define U8500_ASIC_ID_BASE      0x9001D000
  42 
  43 #define U8500_PER6_BASE         0xa03c0000
  44 #define U8500_PER7_BASE         0xa03d0000
  45 #define U8500_PER5_BASE         0xa03e0000
  46 
  47 #define U8500_SVA_BASE          0xa0100000
  48 #define U8500_SIA_BASE          0xa0200000
  49 
  50 #define U8500_SGA_BASE          0xa0300000
  51 #define U8500_MCDE_BASE         0xa0350000
  52 #define U8500_DMA_BASE          0x801C0000      /* v1 */
  53 
  54 #define U8500_SBAG_BASE         0xa0390000
  55 
  56 #define U8500_SCU_BASE          0xa0410000
  57 #define U8500_GIC_CPU_BASE      0xa0410100
  58 #define U8500_TWD_BASE          0xa0410600
  59 #define U8500_GIC_DIST_BASE     0xa0411000
  60 #define U8500_L2CC_BASE         0xa0412000
  61 
  62 #define U8500_MODEM_I2C         0xb7e02000
  63 
  64 #define U8500_GPIO0_BASE        (U8500_PER1_BASE + 0xE000)
  65 #define U8500_GPIO1_BASE        (U8500_PER3_BASE + 0xE000)
  66 #define U8500_GPIO2_BASE        (U8500_PER2_BASE + 0xE000)
  67 #define U8500_GPIO3_BASE        (U8500_PER5_BASE + 0x1E000)
  68 
  69 #define U8500_UART0_BASE        (U8500_PER1_BASE + 0x0000)
  70 #define U8500_UART1_BASE        (U8500_PER1_BASE + 0x1000)
  71 
  72 /* per6 base addresses */
  73 #define U8500_RNG_BASE          (U8500_PER6_BASE + 0x0000)
  74 #define U8500_HASH0_BASE        (U8500_PER6_BASE + 0x1000)
  75 #define U8500_HASH1_BASE        (U8500_PER6_BASE + 0x2000)
  76 #define U8500_PKA_BASE          (U8500_PER6_BASE + 0x4000)
  77 #define U8500_PKAM_BASE         (U8500_PER6_BASE + 0x5100)
  78 #define U8500_MTU0_BASE         (U8500_PER6_BASE + 0x6000) /* v1 */
  79 #define U8500_MTU1_BASE         (U8500_PER6_BASE + 0x7000) /* v1 */
  80 #define U8500_CR_BASE           (U8500_PER6_BASE + 0x8000) /* v1 */
  81 #define U8500_CRYP0_BASE        (U8500_PER6_BASE + 0xa000)
  82 #define U8500_CRYP1_BASE        (U8500_PER6_BASE + 0xb000)
  83 #define U8500_CLKRST6_BASE      (U8500_PER6_BASE + 0xf000)
  84 
  85 /* per5 base addresses */
  86 #define U8500_USBOTG_BASE       (U8500_PER5_BASE + 0x00000)
  87 #define U8500_CLKRST5_BASE      (U8500_PER5_BASE + 0x1f000)
  88 
  89 /* per4 base addresses */
  90 #define U8500_BACKUPRAM0_BASE   (U8500_PER4_BASE + 0x00000)
  91 #define U8500_BACKUPRAM1_BASE   (U8500_PER4_BASE + 0x01000)
  92 #define U8500_RTT0_BASE         (U8500_PER4_BASE + 0x02000)
  93 #define U8500_RTT1_BASE         (U8500_PER4_BASE + 0x03000)
  94 #define U8500_RTC_BASE          (U8500_PER4_BASE + 0x04000)
  95 #define U8500_SCR_BASE          (U8500_PER4_BASE + 0x05000)
  96 #define U8500_DMC_BASE          (U8500_PER4_BASE + 0x06000)
  97 #define U8500_PRCMU_BASE        (U8500_PER4_BASE + 0x07000)
  98 #define U9540_DMC1_BASE         (U8500_PER4_BASE + 0x0A000)
  99 #define U8500_PRCMU_TCDM_BASE   (U8500_PER4_BASE + 0x68000)
 100 #define U8500_PRCMU_TCPM_BASE   (U8500_PER4_BASE + 0x60000)
 101 #define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338)
 102 #define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450)
 103 
 104 /* per3 base addresses */
 105 #define U8500_FSMC_BASE         (U8500_PER3_BASE + 0x0000)
 106 #define U8500_SSP0_BASE         (U8500_PER3_BASE + 0x2000)
 107 #define U8500_SSP1_BASE         (U8500_PER3_BASE + 0x3000)
 108 #define U8500_I2C0_BASE         (U8500_PER3_BASE + 0x4000)
 109 #define U8500_SDI2_BASE         (U8500_PER3_BASE + 0x5000)
 110 #define U8500_SKE_BASE          (U8500_PER3_BASE + 0x6000)
 111 #define U8500_UART2_BASE        (U8500_PER3_BASE + 0x7000)
 112 #define U8500_SDI5_BASE         (U8500_PER3_BASE + 0x8000)
 113 #define U8500_CLKRST3_BASE      (U8500_PER3_BASE + 0xf000)
 114 
 115 /* per2 base addresses */
 116 #define U8500_I2C3_BASE         (U8500_PER2_BASE + 0x0000)
 117 #define U8500_SPI2_BASE         (U8500_PER2_BASE + 0x1000)
 118 #define U8500_SPI1_BASE         (U8500_PER2_BASE + 0x2000)
 119 #define U8500_PWL_BASE          (U8500_PER2_BASE + 0x3000)
 120 #define U8500_SDI4_BASE         (U8500_PER2_BASE + 0x4000)
 121 #define U8500_MSP2_BASE         (U8500_PER2_BASE + 0x7000)
 122 #define U8500_SDI1_BASE         (U8500_PER2_BASE + 0x8000)
 123 #define U8500_SDI3_BASE         (U8500_PER2_BASE + 0x9000)
 124 #define U8500_SPI0_BASE         (U8500_PER2_BASE + 0xa000)
 125 #define U8500_HSIR_BASE         (U8500_PER2_BASE + 0xb000)
 126 #define U8500_HSIT_BASE         (U8500_PER2_BASE + 0xc000)
 127 #define U8500_CLKRST2_BASE      (U8500_PER2_BASE + 0xf000)
 128 
 129 /* per1 base addresses */
 130 #define U8500_I2C1_BASE         (U8500_PER1_BASE + 0x2000)
 131 #define U8500_MSP0_BASE         (U8500_PER1_BASE + 0x3000)
 132 #define U8500_MSP1_BASE         (U8500_PER1_BASE + 0x4000)
 133 #define U8500_MSP3_BASE         (U8500_PER1_BASE + 0x5000)
 134 #define U8500_SDI0_BASE         (U8500_PER1_BASE + 0x6000)
 135 #define U8500_I2C2_BASE         (U8500_PER1_BASE + 0x8000)
 136 #define U8500_SPI3_BASE         (U8500_PER1_BASE + 0x9000)
 137 #define U8500_I2C4_BASE         (U8500_PER1_BASE + 0xa000)
 138 #define U8500_SLIM0_BASE        (U8500_PER1_BASE + 0xb000)
 139 #define U8500_CLKRST1_BASE      (U8500_PER1_BASE + 0xf000)
 140 
 141 #define U8500_SHRM_GOP_INTERRUPT_BASE   0xB7C00040
 142 
 143 #define U8500_GPIOBANK0_BASE    U8500_GPIO0_BASE
 144 #define U8500_GPIOBANK1_BASE    (U8500_GPIO0_BASE + 0x80)
 145 #define U8500_GPIOBANK2_BASE    U8500_GPIO1_BASE
 146 #define U8500_GPIOBANK3_BASE    (U8500_GPIO1_BASE + 0x80)
 147 #define U8500_GPIOBANK4_BASE    (U8500_GPIO1_BASE + 0x100)
 148 #define U8500_GPIOBANK5_BASE    (U8500_GPIO1_BASE + 0x180)
 149 #define U8500_GPIOBANK6_BASE    U8500_GPIO2_BASE
 150 #define U8500_GPIOBANK7_BASE    (U8500_GPIO2_BASE + 0x80)
 151 #define U8500_GPIOBANK8_BASE    U8500_GPIO3_BASE
 152 
 153 #define U8500_MCDE_SIZE         0x1000
 154 #define U8500_DSI_LINK_SIZE     0x1000
 155 #define U8500_DSI_LINK1_BASE    (U8500_MCDE_BASE + U8500_MCDE_SIZE)
 156 #define U8500_DSI_LINK2_BASE    (U8500_DSI_LINK1_BASE + U8500_DSI_LINK_SIZE)
 157 #define U8500_DSI_LINK3_BASE    (U8500_DSI_LINK2_BASE + U8500_DSI_LINK_SIZE)
 158 #define U8500_DSI_LINK_COUNT    0x3
 159 
 160 /* Modem and APE physical addresses */
 161 #define U8500_MODEM_BASE        0xe000000
 162 #define U8500_APE_BASE          0x6000000
 163 
 164 /* SoC identification number information */
 165 #define U8500_BB_UID_BASE      (U8500_BACKUPRAM1_BASE + 0xFC0)
 166 
 167 /* Offsets to specific addresses in some IP blocks for DMA */
 168 #define MSP_TX_RX_REG_OFFSET    0
 169 #define CRYP1_RX_REG_OFFSET     0x10
 170 #define CRYP1_TX_REG_OFFSET     0x8
 171 #define HASH1_TX_REG_OFFSET     0x4
 172 
 173 /*
 174  * Macros to get at IO space when running virtually
 175  * We dont map all the peripherals, let ioremap do
 176  * this for us. We map only very basic peripherals here.
 177  */
 178 #define U8500_IO_VIRTUAL        0xf0000000
 179 #define U8500_IO_PHYSICAL       0xa0000000
 180 /* This is where we map in the ROM to check ASIC IDs */
 181 #define UX500_VIRT_ROM          IOMEM(0xf0000000)
 182 
 183 /* This macro is used in assembly, so no cast */
 184 #define IO_ADDRESS(x)           \
 185         (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL)
 186 
 187 /* typesafe io address */
 188 #define __io_address(n)         IOMEM(IO_ADDRESS(n))
 189 
 190 /* Used by some plat-nomadik code */
 191 #define io_p2v(n)               __io_address(n)
 192 
 193 #define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
 194 
 195 #endif
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root/arch/arm/mach-ux500/db8500-regs.h

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