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6 #ifndef __ASM_TLB_MMU_V1_H__
7 #define __ASM_TLB_MMU_V1_H__
8
9 #include <asm/mmu.h>
10
11 #if defined(__ASSEMBLY__) && (CONFIG_ARC_MMU_VER == 1)
12
13 .macro TLB_WRITE_HEURISTICS
14
15 #define JH_HACK1
16 #undef JH_HACK2
17 #undef JH_HACK3
18
19 #ifdef JH_HACK3
20 ; Calculate set index for 2-way MMU
21 ; -avoiding use of GetIndex from MMU
22 ; and its unpleasant LFSR pseudo-random sequence
23 ;
24 ; r1 = TLBPD0 from TLB_RELOAD above
25 ;
26 ; -- jh_ex_way_set not cleared on startup
27 ; didn't want to change setup.c
28 ; hence extra instruction to clean
29 ;
30 ; -- should be in cache since in same line
31 ; as r0/r1 saves above
32 ;
33 ld r0,[jh_ex_way_sel] ; victim pointer
34 and r0,r0,1 ; clean
35 xor.f r0,r0,1 ; flip
36 st r0,[jh_ex_way_sel] ; store back
37 asr r0,r1,12 ; get set # <<1, note bit 12=R=0
38 or.nz r0,r0,1 ; set way bit
39 and r0,r0,0xff ; clean
40 sr r0,[ARC_REG_TLBINDEX]
41 #endif
42
43 #ifdef JH_HACK2
44 ; JH hack #2
45 ; Faster than hack #1 in non-thrash case, but hard-coded for 2-way MMU
46 ; Slower in thrash case (where it matters) because more code is executed
47 ; Inefficient due to two-register paradigm of this miss handler
48 ;
49
50 lr r0,[eret]
51 xor r0,r0,r1
52 and.f r0,r0,0x000fe000
53 bne 88f
54
55 lr r0,[eret]
56 and r0,r0,PAGE_MASK
57 ; lr r1,[ARC_REG_TLBPD0]
58 and r1,r1,0xff
59 or r0,r0,r1
60
61 lr r1,[ARC_REG_TLBPD0]
62 sr r0,[ARC_REG_TLBPD0]
63 sr TLBProbe, [ARC_REG_TLBCOMMAND]
64 lr r0,[ARC_REG_TLBINDEX]
65 sr r1,[ARC_REG_TLBPD0]
66
67 xor r0,r0,1
68 b.d 89f
69 sr r0,[ARC_REG_TLBINDEX]
70 88:
71 sr TLBGetIndex, [ARC_REG_TLBCOMMAND]
72 89:
73 #endif
74
75 #ifdef JH_HACK1
76 ;
77 ; Always checks whether instruction will be kicked out by dtlb miss
78 ;
79 mov_s r3, r1 ; save PD0 prepared by TLB_RELOAD in r3
80 lr r0,[eret]
81 and r0,r0,PAGE_MASK
82 bmsk r1,r3,7
83 or_s r0,r0,r1
84
85 sr r0,[ARC_REG_TLBPD0]
86 sr TLBProbe, [ARC_REG_TLBCOMMAND]
87 lr r0,[ARC_REG_TLBINDEX]
88 sr r3,[ARC_REG_TLBPD0]
89
90 sr TLBGetIndex, [ARC_REG_TLBCOMMAND]
91 lr r1,[ARC_REG_TLBINDEX]
92 cmp r0,r1
93 xor.eq r1,r1,1
94 sr r1,[ARC_REG_TLBINDEX]
95 #endif
96
97 .endm
98
99 #endif
100
101 #endif