root/arch/arm/boot/dts/imx50-pinfunc.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
   4  */
   5 
   6 #ifndef __DTS_IMX50_PINFUNC_H
   7 #define __DTS_IMX50_PINFUNC_H
   8 
   9 /*
  10  * The pin function ID is a tuple of
  11  * <mux_reg conf_reg input_reg mux_mode input_val>
  12  */
  13 #define MX50_PAD_KEY_COL0__KPP_COL_0                            0x020 0x2cc 0x000 0x0 0x0
  14 #define MX50_PAD_KEY_COL0__GPIO4_0                              0x020 0x2cc 0x000 0x1 0x0
  15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE                        0x020 0x2cc 0x000 0x2 0x0
  16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7                          0x020 0x2cc 0x000 0x6 0x0
  17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY                      0x020 0x2cc 0x000 0x7 0x0
  18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0                            0x024 0x2d0 0x000 0x0 0x0
  19 #define MX50_PAD_KEY_ROW0__GPIO4_1                              0x024 0x2d0 0x000 0x1 0x0
  20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE                        0x024 0x2d0 0x000 0x2 0x0
  21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7                      0x024 0x2d0 0x000 0x6 0x0
  22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID                      0x024 0x2d0 0x000 0x7 0x0
  23 #define MX50_PAD_KEY_COL1__KPP_COL_1                            0x028 0x2d4 0x000 0x0 0x0
  24 #define MX50_PAD_KEY_COL1__GPIO4_2                              0x028 0x2d4 0x000 0x1 0x0
  25 #define MX50_PAD_KEY_COL1__EIM_NANDF_CEN_0                      0x028 0x2d4 0x000 0x2 0x0
  26 #define MX50_PAD_KEY_COL1__CTI_TRIGOUT_ACK6                     0x028 0x2d4 0x000 0x6 0x0
  27 #define MX50_PAD_KEY_COL1__USBPHY1_RXACTIVE                     0x028 0x2d4 0x000 0x7 0x0
  28 #define MX50_PAD_KEY_ROW1__KPP_ROW_1                            0x02c 0x2d8 0x000 0x0 0x0
  29 #define MX50_PAD_KEY_ROW1__GPIO4_3                              0x02c 0x2d8 0x000 0x1 0x0
  30 #define MX50_PAD_KEY_ROW1__EIM_NANDF_CEN_1                      0x02c 0x2d8 0x000 0x2 0x0
  31 #define MX50_PAD_KEY_ROW1__CTI_TRIGOUT_ACK7                     0x02c 0x2d8 0x000 0x6 0x0
  32 #define MX50_PAD_KEY_ROW1__USBPHY1_RXERROR                      0x02c 0x2d8 0x000 0x7 0x0
  33 #define MX50_PAD_KEY_COL2__KPP_COL_2                            0x030 0x2dc 0x000 0x0 0x0
  34 #define MX50_PAD_KEY_COL2__GPIO4_4                              0x030 0x2dc 0x000 0x1 0x0
  35 #define MX50_PAD_KEY_COL2__EIM_NANDF_CEN_2                      0x030 0x2dc 0x000 0x2 0x0
  36 #define MX50_PAD_KEY_COL2__CTI_TRIGOUT6                         0x030 0x2dc 0x000 0x6 0x0
  37 #define MX50_PAD_KEY_COL2__USBPHY1_SIECLOCK                     0x030 0x2dc 0x000 0x7 0x0
  38 #define MX50_PAD_KEY_ROW2__KPP_ROW_2                            0x034 0x2e0 0x000 0x0 0x0
  39 #define MX50_PAD_KEY_ROW2__GPIO4_5                              0x034 0x2e0 0x000 0x1 0x0
  40 #define MX50_PAD_KEY_ROW2__EIM_NANDF_CEN_3                      0x034 0x2e0 0x000 0x2 0x0
  41 #define MX50_PAD_KEY_ROW2__CTI_TRIGOUT7                         0x034 0x2e0 0x000 0x6 0x0
  42 #define MX50_PAD_KEY_ROW2__USBPHY1_LINESTATE_0                  0x034 0x2e0 0x000 0x7 0x0
  43 #define MX50_PAD_KEY_COL3__KPP_COL_3                            0x038 0x2e4 0x000 0x0 0x0
  44 #define MX50_PAD_KEY_COL3__GPIO4_6                              0x038 0x2e4 0x000 0x1 0x0
  45 #define MX50_PAD_KEY_COL3__EIM_NANDF_READY0                     0x038 0x2e4 0x7b4 0x2 0x0
  46 #define MX50_PAD_KEY_COL3__SDMA_EXT_EVENT_0                     0x038 0x2e4 0x7b8 0x6 0x0
  47 #define MX50_PAD_KEY_COL3__USBPHY1_LINESTATE_1                  0x038 0x2e4 0x000 0x7 0x0
  48 #define MX50_PAD_KEY_ROW3__KPP_ROW_3                            0x03c 0x2e8 0x000 0x0 0x0
  49 #define MX50_PAD_KEY_ROW3__GPIO4_7                              0x03c 0x2e8 0x000 0x1 0x0
  50 #define MX50_PAD_KEY_ROW3__EIM_NANDF_DQS                        0x03c 0x2e8 0x7b0 0x2 0x0
  51 #define MX50_PAD_KEY_ROW3__SDMA_EXT_EVENT_1                     0x03c 0x2e8 0x7bc 0x6 0x0
  52 #define MX50_PAD_KEY_ROW3__USBPHY1_VBUSVALID                    0x03c 0x2e8 0x000 0x7 0x0
  53 #define MX50_PAD_I2C1_SCL__I2C1_SCL                             0x040 0x2ec 0x000 0x0 0x0
  54 #define MX50_PAD_I2C1_SCL__GPIO6_18                             0x040 0x2ec 0x000 0x1 0x0
  55 #define MX50_PAD_I2C1_SCL__UART2_TXD_MUX                        0x040 0x2ec 0x7cc 0x2 0x0
  56 #define MX50_PAD_I2C1_SDA__I2C1_SDA                             0x044 0x2f0 0x000 0x0 0x0
  57 #define MX50_PAD_I2C1_SDA__GPIO6_19                             0x044 0x2f0 0x000 0x1 0x0
  58 #define MX50_PAD_I2C1_SDA__UART2_RXD_MUX                        0x044 0x2f0 0x7cc 0x2 0x1
  59 #define MX50_PAD_I2C2_SCL__I2C2_SCL                             0x048 0x2f4 0x000 0x0 0x0
  60 #define MX50_PAD_I2C2_SCL__GPIO6_20                             0x048 0x2f4 0x000 0x1 0x0
  61 #define MX50_PAD_I2C2_SCL__UART2_CTS                            0x048 0x2f4 0x000 0x2 0x0
  62 #define MX50_PAD_I2C2_SDA__I2C2_SDA                             0x04c 0x2f8 0x000 0x0 0x0
  63 #define MX50_PAD_I2C2_SDA__GPIO6_21                             0x04c 0x2f8 0x000 0x1 0x0
  64 #define MX50_PAD_I2C2_SDA__UART2_RTS                            0x04c 0x2f8 0x7c8 0x2 0x1
  65 #define MX50_PAD_I2C3_SCL__I2C3_SCL                             0x050 0x2fc 0x000 0x0 0x0
  66 #define MX50_PAD_I2C3_SCL__GPIO6_22                             0x050 0x2fc 0x000 0x1 0x0
  67 #define MX50_PAD_I2C3_SCL__FEC_MDC                              0x050 0x2fc 0x000 0x2 0x0
  68 #define MX50_PAD_I2C3_SCL__GPC_PMIC_RDY                         0x050 0x2fc 0x000 0x3 0x0
  69 #define MX50_PAD_I2C3_SCL__GPT_CAPIN1                           0x050 0x2fc 0x000 0x5 0x0
  70 #define MX50_PAD_I2C3_SCL__OBSERVE_MUX_OBSRV_INT_OUT0           0x050 0x2fc 0x000 0x6 0x0
  71 #define MX50_PAD_I2C3_SCL__USBOH1_USBOTG_OC                     0x050 0x2fc 0x7e8 0x7 0x0
  72 #define MX50_PAD_I2C3_SDA__I2C3_SDA                             0x054 0x300 0x000 0x0 0x0
  73 #define MX50_PAD_I2C3_SDA__GPIO6_23                             0x054 0x300 0x000 0x1 0x0
  74 #define MX50_PAD_I2C3_SDA__FEC_MDIO                             0x054 0x300 0x774 0x2 0x0
  75 #define MX50_PAD_I2C3_SDA__TZIC_PWRFAIL_INT                     0x054 0x300 0x000 0x3 0x0
  76 #define MX50_PAD_I2C3_SDA__SRTC_ALARM_DEB                       0x054 0x300 0x000 0x4 0x0
  77 #define MX50_PAD_I2C3_SDA__GPT_CAPIN2                           0x054 0x300 0x000 0x5 0x0
  78 #define MX50_PAD_I2C3_SDA__OBSERVE_MUX_OBSRV_INT_OUT1           0x054 0x300 0x000 0x6 0x0
  79 #define MX50_PAD_I2C3_SDA__USBOH1_USBOTG_PWR                    0x054 0x300 0x000 0x7 0x0
  80 #define MX50_PAD_PWM1__PWM1_PWMO                                0x058 0x304 0x000 0x0 0x0
  81 #define MX50_PAD_PWM1__GPIO6_24                                 0x058 0x304 0x000 0x1 0x0
  82 #define MX50_PAD_PWM1__USBOH1_USBOTG_OC                         0x058 0x304 0x7e8 0x2 0x1
  83 #define MX50_PAD_PWM1__GPT_CMPOUT1                              0x058 0x304 0x000 0x5 0x0
  84 #define MX50_PAD_PWM1__OBSERVE_MUX_OBSRV_INT_OUT2               0x058 0x304 0x000 0x6 0x0
  85 #define MX50_PAD_PWM1__SJC_FAIL                                 0x058 0x304 0x000 0x7 0x0
  86 #define MX50_PAD_PWM2__PWM2_PWMO                                0x05c 0x308 0x000 0x0 0x0
  87 #define MX50_PAD_PWM2__GPIO6_25                                 0x05c 0x308 0x000 0x1 0x0
  88 #define MX50_PAD_PWM2__USBOH1_USBOTG_PWR                        0x05c 0x308 0x000 0x2 0x0
  89 #define MX50_PAD_PWM2__GPT_CMPOUT2                              0x05c 0x308 0x000 0x5 0x0
  90 #define MX50_PAD_PWM2__OBSERVE_MUX_OBSRV_INT_OUT3               0x05c 0x308 0x000 0x6 0x0
  91 #define MX50_PAD_PWM2__SRC_ANY_PU_RST                           0x05c 0x308 0x000 0x7 0x0
  92 #define MX50_PAD_OWIRE__OWIRE_LINE                              0x060 0x30c 0x000 0x0 0x0
  93 #define MX50_PAD_OWIRE__GPIO6_26                                0x060 0x30c 0x000 0x1 0x0
  94 #define MX50_PAD_OWIRE__USBOH1_USBH1_OC                         0x060 0x30c 0x000 0x2 0x0
  95 #define MX50_PAD_OWIRE__CCM_SSI_EXT1_CLK                        0x060 0x30c 0x000 0x3 0x0
  96 #define MX50_PAD_OWIRE__EPDC_PWRIRQ                             0x060 0x30c 0x000 0x4 0x0
  97 #define MX50_PAD_OWIRE__GPT_CMPOUT3                             0x060 0x30c 0x000 0x5 0x0
  98 #define MX50_PAD_OWIRE__OBSERVE_MUX_OBSRV_INT_OUT4              0x060 0x30c 0x000 0x6 0x0
  99 #define MX50_PAD_OWIRE__SJC_JTAG_ACT                            0x060 0x30c 0x000 0x7 0x0
 100 #define MX50_PAD_EPITO__EPIT1_EPITO                             0x064 0x310 0x000 0x0 0x0
 101 #define MX50_PAD_EPITO__GPIO6_27                                0x064 0x310 0x000 0x1 0x0
 102 #define MX50_PAD_EPITO__USBOH1_USBH1_PWR                        0x064 0x310 0x000 0x2 0x0
 103 #define MX50_PAD_EPITO__CCM_SSI_EXT2_CLK                        0x064 0x310 0x000 0x3 0x0
 104 #define MX50_PAD_EPITO__DPLLIP1_TOG_EN                          0x064 0x310 0x000 0x4 0x0
 105 #define MX50_PAD_EPITO__GPT_CLK_IN                              0x064 0x310 0x000 0x5 0x0
 106 #define MX50_PAD_EPITO__PMU_IRQ_B                               0x064 0x310 0x000 0x6 0x0
 107 #define MX50_PAD_EPITO__SJC_DE_B                                0x064 0x310 0x000 0x7 0x0
 108 #define MX50_PAD_WDOG__WDOG1_WDOG_B                             0x068 0x314 0x000 0x0 0x0
 109 #define MX50_PAD_WDOG__GPIO6_28                                 0x068 0x314 0x000 0x1 0x0
 110 #define MX50_PAD_WDOG__WDOG1_WDOG_RST_B_DEB                     0x068 0x314 0x000 0x2 0x0
 111 #define MX50_PAD_WDOG__CCM_XTAL32K                              0x068 0x314 0x000 0x6 0x0
 112 #define MX50_PAD_WDOG__SJC_DONE                                 0x068 0x314 0x000 0x7 0x0
 113 #define MX50_PAD_SSI_TXFS__AUDMUX_AUD3_TXFS                     0x06c 0x318 0x000 0x0 0x0
 114 #define MX50_PAD_SSI_TXFS__GPIO6_0                              0x06c 0x318 0x000 0x1 0x0
 115 #define MX50_PAD_SSI_TXFS__SRC_BT_FUSE_RSV_1                    0x06c 0x318 0x000 0x6 0x0
 116 #define MX50_PAD_SSI_TXFS__USBPHY1_DATAOUT_8                    0x06c 0x318 0x000 0x7 0x0
 117 #define MX50_PAD_SSI_TXC__AUDMUX_AUD3_TXC                       0x070 0x31c 0x000 0x0 0x0
 118 #define MX50_PAD_SSI_TXC__GPIO6_1                               0x070 0x31c 0x000 0x1 0x0
 119 #define MX50_PAD_SSI_TXC__SRC_BT_FUSE_RSV_0                     0x070 0x31c 0x000 0x6 0x0
 120 #define MX50_PAD_SSI_TXC__USBPHY1_DATAOUT_9                     0x070 0x31c 0x000 0x7 0x0
 121 #define MX50_PAD_SSI_TXD__AUDMUX_AUD3_TXD                       0x074 0x320 0x000 0x0 0x0
 122 #define MX50_PAD_SSI_TXD__GPIO6_2                               0x074 0x320 0x000 0x1 0x0
 123 #define MX50_PAD_SSI_TXD__CSPI_RDY                              0x074 0x320 0x6e8 0x4 0x0
 124 #define MX50_PAD_SSI_TXD__USBPHY1_DATAOUT_10                    0x074 0x320 0x000 0x7 0x0
 125 #define MX50_PAD_SSI_RXD__AUDMUX_AUD3_RXD                       0x078 0x324 0x000 0x0 0x0
 126 #define MX50_PAD_SSI_RXD__GPIO6_3                               0x078 0x324 0x000 0x1 0x0
 127 #define MX50_PAD_SSI_RXD__CSPI_SS3                              0x078 0x324 0x6f4 0x4 0x0
 128 #define MX50_PAD_SSI_RXD__USBPHY1_DATAOUT_11                    0x078 0x324 0x000 0x7 0x0
 129 #define MX50_PAD_SSI_RXFS__AUDMUX_AUD3_RXFS                     0x07c 0x328 0x000 0x0 0x0
 130 #define MX50_PAD_SSI_RXFS__GPIO6_4                              0x07c 0x328 0x000 0x1 0x0
 131 #define MX50_PAD_SSI_RXFS__UART5_TXD_MUX                        0x07c 0x328 0x7e4 0x2 0x0
 132 #define MX50_PAD_SSI_RXFS__EIM_WEIM_D_6                         0x07c 0x328 0x804 0x3 0x0
 133 #define MX50_PAD_SSI_RXFS__CSPI_SS2                             0x07c 0x328 0x6f0 0x4 0x0
 134 #define MX50_PAD_SSI_RXFS__FEC_COL                              0x07c 0x328 0x770 0x5 0x0
 135 #define MX50_PAD_SSI_RXFS__FEC_MDC                              0x07c 0x328 0x000 0x6 0x0
 136 #define MX50_PAD_SSI_RXFS__USBPHY1_DATAOUT_12                   0x07c 0x328 0x000 0x7 0x0
 137 #define MX50_PAD_SSI_RXC__AUDMUX_AUD3_RXC                       0x080 0x32c 0x000 0x0 0x0
 138 #define MX50_PAD_SSI_RXC__GPIO6_5                               0x080 0x32c 0x000 0x1 0x0
 139 #define MX50_PAD_SSI_RXC__UART5_RXD_MUX                         0x080 0x32c 0x7e4 0x2 0x1
 140 #define MX50_PAD_SSI_RXC__EIM_WEIM_D_7                          0x080 0x32c 0x808 0x3 0x0
 141 #define MX50_PAD_SSI_RXC__CSPI_SS1                              0x080 0x32c 0x6ec 0x4 0x0
 142 #define MX50_PAD_SSI_RXC__FEC_RX_CLK                            0x080 0x32c 0x780 0x5 0x0
 143 #define MX50_PAD_SSI_RXC__FEC_MDIO                              0x080 0x32c 0x774 0x6 0x1
 144 #define MX50_PAD_SSI_RXC__USBPHY1_DATAOUT_13                    0x080 0x32c 0x000 0x7 0x0
 145 #define MX50_PAD_UART1_TXD__UART1_TXD_MUX                       0x084 0x330 0x7c4 0x0 0x0
 146 #define MX50_PAD_UART1_TXD__GPIO6_6                             0x084 0x330 0x000 0x1 0x0
 147 #define MX50_PAD_UART1_TXD__USBPHY1_DATAOUT_14                  0x084 0x330 0x000 0x7 0x0
 148 #define MX50_PAD_UART1_RXD__UART1_RXD_MUX                       0x088 0x334 0x7c4 0x0 0x1
 149 #define MX50_PAD_UART1_RXD__GPIO6_7                             0x088 0x334 0x000 0x1 0x0
 150 #define MX50_PAD_UART1_RXD__USBPHY1_DATAOUT_15                  0x088 0x334 0x000 0x7 0x0
 151 #define MX50_PAD_UART1_CTS__UART1_CTS                           0x08c 0x338 0x000 0x0 0x0
 152 #define MX50_PAD_UART1_CTS__GPIO6_8                             0x08c 0x338 0x000 0x1 0x0
 153 #define MX50_PAD_UART1_CTS__UART5_TXD_MUX                       0x08c 0x338 0x7e4 0x2 0x2
 154 #define MX50_PAD_UART1_CTS__ESDHC4_DAT4                         0x08c 0x338 0x760 0x4 0x0
 155 #define MX50_PAD_UART1_CTS__ESDHC4_CMD                          0x08c 0x338 0x74c 0x5 0x0
 156 #define MX50_PAD_UART1_CTS__USBPHY2_DATAOUT_8                   0x08c 0x338 0x000 0x7 0x0
 157 #define MX50_PAD_UART1_RTS__UART1_RTS                           0x090 0x33c 0x7c0 0x0 0x3
 158 #define MX50_PAD_UART1_RTS__GPIO6_9                             0x090 0x33c 0x000 0x1 0x0
 159 #define MX50_PAD_UART1_RTS__UART5_RXD_MUX                       0x090 0x33c 0x7e4 0x2 0x3
 160 #define MX50_PAD_UART1_RTS__ESDHC4_DAT5                         0x090 0x33c 0x764 0x4 0x0
 161 #define MX50_PAD_UART1_RTS__ESDHC4_CLK                          0x090 0x33c 0x748 0x5 0x0
 162 #define MX50_PAD_UART1_RTS__USBPHY2_DATAOUT_9                   0x090 0x33c 0x000 0x7 0x0
 163 #define MX50_PAD_UART2_TXD__UART2_TXD_MUX                       0x094 0x340 0x7cc 0x0 0x2
 164 #define MX50_PAD_UART2_TXD__GPIO6_10                            0x094 0x340 0x000 0x1 0x0
 165 #define MX50_PAD_UART2_TXD__ESDHC4_DAT6                         0x094 0x340 0x768 0x4 0x0
 166 #define MX50_PAD_UART2_TXD__ESDHC4_DAT4                         0x094 0x340 0x760 0x5 0x1
 167 #define MX50_PAD_UART2_TXD__USBPHY2_DATAOUT_10                  0x094 0x340 0x000 0x7 0x0
 168 #define MX50_PAD_UART2_RXD__UART2_RXD_MUX                       0x098 0x344 0x7cc 0x0 0x3
 169 #define MX50_PAD_UART2_RXD__GPIO6_11                            0x098 0x344 0x000 0x1 0x0
 170 #define MX50_PAD_UART2_RXD__ESDHC4_DAT7                         0x098 0x344 0x76c 0x4 0x0
 171 #define MX50_PAD_UART2_RXD__ESDHC4_DAT5                         0x098 0x344 0x764 0x5 0x1
 172 #define MX50_PAD_UART2_RXD__USBPHY2_DATAOUT_11                  0x098 0x344 0x000 0x7 0x0
 173 #define MX50_PAD_UART2_CTS__UART2_CTS                           0x09c 0x348 0x000 0x0 0x0
 174 #define MX50_PAD_UART2_CTS__GPIO6_12                            0x09c 0x348 0x000 0x1 0x0
 175 #define MX50_PAD_UART2_CTS__ESDHC4_CMD                          0x09c 0x348 0x74c 0x4 0x1
 176 #define MX50_PAD_UART2_CTS__ESDHC4_DAT6                         0x09c 0x348 0x768 0x5 0x1
 177 #define MX50_PAD_UART2_CTS__USBPHY2_DATAOUT_12                  0x09c 0x348 0x000 0x7 0x0
 178 #define MX50_PAD_UART2_RTS__UART2_RTS                           0x0a0 0x34c 0x7c8 0x0 0x2
 179 #define MX50_PAD_UART2_RTS__GPIO6_13                            0x0a0 0x34c 0x000 0x1 0x0
 180 #define MX50_PAD_UART2_RTS__ESDHC4_CLK                          0x0a0 0x34c 0x748 0x4 0x1
 181 #define MX50_PAD_UART2_RTS__ESDHC4_DAT7                         0x0a0 0x34c 0x76c 0x5 0x1
 182 #define MX50_PAD_UART2_RTS__USBPHY2_DATAOUT_13                  0x0a0 0x34c 0x000 0x7 0x0
 183 #define MX50_PAD_UART3_TXD__UART3_TXD_MUX                       0x0a4 0x350 0x7d4 0x0 0x0
 184 #define MX50_PAD_UART3_TXD__GPIO6_14                            0x0a4 0x350 0x000 0x1 0x0
 185 #define MX50_PAD_UART3_TXD__ESDHC1_DAT4                         0x0a4 0x350 0x000 0x3 0x0
 186 #define MX50_PAD_UART3_TXD__ESDHC4_DAT0                         0x0a4 0x350 0x000 0x4 0x0
 187 #define MX50_PAD_UART3_TXD__ESDHC2_WP                           0x0a4 0x350 0x744 0x5 0x0
 188 #define MX50_PAD_UART3_TXD__EIM_WEIM_D_12                       0x0a4 0x350 0x81c 0x6 0x0
 189 #define MX50_PAD_UART3_TXD__USBPHY2_DATAOUT_14                  0x0a4 0x350 0x000 0x7 0x0
 190 #define MX50_PAD_UART3_RXD__UART3_RXD_MUX                       0x0a8 0x354 0x7d4 0x0 0x1
 191 #define MX50_PAD_UART3_RXD__GPIO6_15                            0x0a8 0x354 0x000 0x1 0x0
 192 #define MX50_PAD_UART3_RXD__ESDHC1_DAT5                         0x0a8 0x354 0x000 0x3 0x0
 193 #define MX50_PAD_UART3_RXD__ESDHC4_DAT1                         0x0a8 0x354 0x754 0x4 0x0
 194 #define MX50_PAD_UART3_RXD__ESDHC2_CD                           0x0a8 0x354 0x740 0x5 0x0
 195 #define MX50_PAD_UART3_RXD__EIM_WEIM_D_13                       0x0a8 0x354 0x820 0x6 0x0
 196 #define MX50_PAD_UART3_RXD__USBPHY2_DATAOUT_15                  0x0a8 0x354 0x000 0x7 0x0
 197 #define MX50_PAD_UART4_TXD__UART4_TXD_MUX                       0x0ac 0x358 0x7dc 0x0 0x0
 198 #define MX50_PAD_UART4_TXD__GPIO6_16                            0x0ac 0x358 0x000 0x1 0x0
 199 #define MX50_PAD_UART4_TXD__UART3_CTS                           0x0ac 0x358 0x7d0 0x2 0x0
 200 #define MX50_PAD_UART4_TXD__ESDHC1_DAT6                         0x0ac 0x358 0x000 0x3 0x0
 201 #define MX50_PAD_UART4_TXD__ESDHC4_DAT2                         0x0ac 0x358 0x758 0x4 0x0
 202 #define MX50_PAD_UART4_TXD__ESDHC2_LCTL                         0x0ac 0x358 0x000 0x5 0x0
 203 #define MX50_PAD_UART4_TXD__EIM_WEIM_D_14                       0x0ac 0x358 0x824 0x6 0x0
 204 #define MX50_PAD_UART4_RXD__UART4_RXD_MUX                       0x0b0 0x35c 0x7dc 0x0 0x1
 205 #define MX50_PAD_UART4_RXD__GPIO6_17                            0x0b0 0x35c 0x000 0x1 0x0
 206 #define MX50_PAD_UART4_RXD__UART3_RTS                           0x0b0 0x35c 0x7d0 0x2 0x1
 207 #define MX50_PAD_UART4_RXD__ESDHC1_DAT7                         0x0b0 0x35c 0x000 0x3 0x0
 208 #define MX50_PAD_UART4_RXD__ESDHC4_DAT3                         0x0b0 0x35c 0x75c 0x4 0x0
 209 #define MX50_PAD_UART4_RXD__ESDHC1_LCTL                         0x0b0 0x35c 0x000 0x5 0x0
 210 #define MX50_PAD_UART4_RXD__EIM_WEIM_D_15                       0x0b0 0x35c 0x828 0x6 0x0
 211 #define MX50_PAD_CSPI_SCLK__CSPI_SCLK                           0x0b4 0x360 0x000 0x0 0x0
 212 #define MX50_PAD_CSPI_SCLK__GPIO4_8                             0x0b4 0x360 0x000 0x1 0x0
 213 #define MX50_PAD_CSPI_MOSI__CSPI_MOSI                           0x0b8 0x364 0x000 0x0 0x0
 214 #define MX50_PAD_CSPI_MOSI__GPIO4_9                             0x0b8 0x364 0x000 0x1 0x0
 215 #define MX50_PAD_CSPI_MISO__CSPI_MISO                           0x0bc 0x368 0x000 0x0 0x0
 216 #define MX50_PAD_CSPI_MISO__GPIO4_10                            0x0bc 0x368 0x000 0x1 0x0
 217 #define MX50_PAD_CSPI_SS0__CSPI_SS0                             0x0c0 0x36c 0x000 0x0 0x0
 218 #define MX50_PAD_CSPI_SS0__GPIO4_11                             0x0c0 0x36c 0x000 0x1 0x0
 219 #define MX50_PAD_ECSPI1_SCLK__ECSPI1_SCLK                       0x0c4 0x370 0x000 0x0 0x0
 220 #define MX50_PAD_ECSPI1_SCLK__GPIO4_12                          0x0c4 0x370 0x000 0x1 0x0
 221 #define MX50_PAD_ECSPI1_SCLK__CSPI_RDY                          0x0c4 0x370 0x6e8 0x2 0x1
 222 #define MX50_PAD_ECSPI1_SCLK__ECSPI2_RDY                        0x0c4 0x370 0x000 0x3 0x0
 223 #define MX50_PAD_ECSPI1_SCLK__UART3_RTS                         0x0c4 0x370 0x7d0 0x4 0x2
 224 #define MX50_PAD_ECSPI1_SCLK__EPDC_SDCE_6                       0x0c4 0x370 0x000 0x5 0x0
 225 #define MX50_PAD_ECSPI1_SCLK__EIM_WEIM_D_8                      0x0c4 0x370 0x80c 0x7 0x0
 226 #define MX50_PAD_ECSPI1_MOSI__ECSPI1_MOSI                       0x0c8 0x374 0x000 0x0 0x0
 227 #define MX50_PAD_ECSPI1_MOSI__GPIO4_13                          0x0c8 0x374 0x000 0x1 0x0
 228 #define MX50_PAD_ECSPI1_MOSI__CSPI_SS1                          0x0c8 0x374 0x6ec 0x2 0x1
 229 #define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1                        0x0c8 0x374 0x000 0x3 0x0
 230 #define MX50_PAD_ECSPI1_MOSI__UART3_CTS                         0x0c8 0x374 0x000 0x4 0x0
 231 #define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE_7                       0x0c8 0x374 0x000 0x5 0x0
 232 #define MX50_PAD_ECSPI1_MOSI__EIM_WEIM_D_9                      0x0c8 0x374 0x810 0x7 0x0
 233 #define MX50_PAD_ECSPI1_MISO__ECSPI1_MISO                       0x0cc 0x378 0x000 0x0 0x0
 234 #define MX50_PAD_ECSPI1_MISO__GPIO4_14                          0x0cc 0x378 0x000 0x1 0x0
 235 #define MX50_PAD_ECSPI1_MISO__CSPI_SS2                          0x0cc 0x378 0x6f0 0x2 0x1
 236 #define MX50_PAD_ECSPI1_MISO__ECSPI2_SS2                        0x0cc 0x378 0x000 0x3 0x0
 237 #define MX50_PAD_ECSPI1_MISO__UART4_RTS                         0x0cc 0x378 0x7d8 0x4 0x0
 238 #define MX50_PAD_ECSPI1_MISO__EPDC_SDCE_8                       0x0cc 0x378 0x000 0x5 0x0
 239 #define MX50_PAD_ECSPI1_MISO__EIM_WEIM_D_10                     0x0cc 0x378 0x814 0x7 0x0
 240 #define MX50_PAD_ECSPI1_SS0__ECSPI1_SS0                         0x0d0 0x37c 0x000 0x0 0x0
 241 #define MX50_PAD_ECSPI1_SS0__GPIO4_15                           0x0d0 0x37c 0x000 0x1 0x0
 242 #define MX50_PAD_ECSPI1_SS0__CSPI_SS3                           0x0d0 0x37c 0x6f4 0x2 0x1
 243 #define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3                         0x0d0 0x37c 0x000 0x3 0x0
 244 #define MX50_PAD_ECSPI1_SS0__UART4_CTS                          0x0d0 0x37c 0x000 0x4 0x0
 245 #define MX50_PAD_ECSPI1_SS0__EPDC_SDCE_9                        0x0d0 0x37c 0x000 0x5 0x0
 246 #define MX50_PAD_ECSPI1_SS0__EIM_WEIM_D_11                      0x0d0 0x37c 0x818 0x7 0x0
 247 #define MX50_PAD_ECSPI2_SCLK__ECSPI2_SCLK                       0x0d4 0x380 0x000 0x0 0x0
 248 #define MX50_PAD_ECSPI2_SCLK__GPIO4_16                          0x0d4 0x380 0x000 0x1 0x0
 249 #define MX50_PAD_ECSPI2_SCLK__ELCDIF_WR_RWN                     0x0d4 0x380 0x000 0x2 0x0
 250 #define MX50_PAD_ECSPI2_SCLK__ECSPI1_RDY                        0x0d4 0x380 0x000 0x3 0x0
 251 #define MX50_PAD_ECSPI2_SCLK__UART5_RTS                         0x0d4 0x380 0x7e0 0x4 0x0
 252 #define MX50_PAD_ECSPI2_SCLK__ELCDIF_DOTCLK                     0x0d4 0x380 0x000 0x5 0x0
 253 #define MX50_PAD_ECSPI2_SCLK__EIM_NANDF_CEN_4                   0x0d4 0x380 0x000 0x6 0x0
 254 #define MX50_PAD_ECSPI2_SCLK__EIM_WEIM_D_8                      0x0d4 0x380 0x80c 0x7 0x1
 255 #define MX50_PAD_ECSPI2_MOSI__ECSPI2_MOSI                       0x0d8 0x384 0x000 0x0 0x0
 256 #define MX50_PAD_ECSPI2_MOSI__GPIO4_17                          0x0d8 0x384 0x000 0x1 0x0
 257 #define MX50_PAD_ECSPI2_MOSI__ELCDIF_RE_E                       0x0d8 0x384 0x000 0x2 0x0
 258 #define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1                        0x0d8 0x384 0x000 0x3 0x0
 259 #define MX50_PAD_ECSPI2_MOSI__UART5_CTS                         0x0d8 0x384 0x7e0 0x4 0x1
 260 #define MX50_PAD_ECSPI2_MOSI__ELCDIF_ENABLE                     0x0d8 0x384 0x000 0x5 0x0
 261 #define MX50_PAD_ECSPI2_MOSI__EIM_NANDF_CEN_5                   0x0d8 0x384 0x000 0x6 0x0
 262 #define MX50_PAD_ECSPI2_MOSI__EIM_WEIM_D_9                      0x0d8 0x384 0x810 0x7 0x1
 263 #define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO                       0x0dc 0x388 0x000 0x0 0x0
 264 #define MX50_PAD_ECSPI2_MISO__GPIO4_18                          0x0dc 0x388 0x000 0x1 0x0
 265 #define MX50_PAD_ECSPI2_MISO__ELCDIF_RS                         0x0dc 0x388 0x000 0x2 0x0
 266 #define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2                        0x0dc 0x388 0x000 0x3 0x0
 267 #define MX50_PAD_ECSPI2_MISO__UART5_TXD_MUX                     0x0dc 0x388 0x7e4 0x4 0x4
 268 #define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC                      0x0dc 0x388 0x73c 0x5 0x0
 269 #define MX50_PAD_ECSPI2_MISO__EIM_NANDF_CEN_6                   0x0dc 0x388 0x000 0x6 0x0
 270 #define MX50_PAD_ECSPI2_MISO__EIM_WEIM_D_10                     0x0dc 0x388 0x814 0x7 0x1
 271 #define MX50_PAD_ECSPI2_SS0__ECSPI2_SS0                         0x0e0 0x38c 0x000 0x0 0x0
 272 #define MX50_PAD_ECSPI2_SS0__GPIO4_19                           0x0e0 0x38c 0x000 0x1 0x0
 273 #define MX50_PAD_ECSPI2_SS0__ELCDIF_CS                          0x0e0 0x38c 0x000 0x2 0x0
 274 #define MX50_PAD_ECSPI2_SS0__ECSPI2_SS3                         0x0e0 0x38c 0x000 0x3 0x0
 275 #define MX50_PAD_ECSPI2_SS0__UART5_RXD_MUX                      0x0e0 0x38c 0x7e4 0x4 0x5
 276 #define MX50_PAD_ECSPI2_SS0__ELCDIF_HSYNC                       0x0e0 0x38c 0x6f8 0x5 0x0
 277 #define MX50_PAD_ECSPI2_SS0__EIM_NANDF_CEN_7                    0x0e0 0x38c 0x000 0x6 0x0
 278 #define MX50_PAD_ECSPI2_SS0__EIM_WEIM_D_11                      0x0e0 0x38c 0x818 0x7 0x1
 279 #define MX50_PAD_SD1_CLK__ESDHC1_CLK                            0x0e4 0x390 0x000 0x0 0x0
 280 #define MX50_PAD_SD1_CLK__GPIO5_0                               0x0e4 0x390 0x000 0x1 0x0
 281 #define MX50_PAD_SD1_CLK__CCM_CLKO                              0x0e4 0x390 0x000 0x7 0x0
 282 #define MX50_PAD_SD1_CMD__ESDHC1_CMD                            0x0e8 0x394 0x000 0x0 0x0
 283 #define MX50_PAD_SD1_CMD__GPIO5_1                               0x0e8 0x394 0x000 0x1 0x0
 284 #define MX50_PAD_SD1_CMD__CCM_CLKO2                             0x0e8 0x394 0x000 0x7 0x0
 285 #define MX50_PAD_SD1_D0__ESDHC1_DAT0                            0x0ec 0x398 0x000 0x0 0x0
 286 #define MX50_PAD_SD1_D0__GPIO5_2                                0x0ec 0x398 0x000 0x1 0x0
 287 #define MX50_PAD_SD1_D0__CCM_PLL1_BYP                           0x0ec 0x398 0x6dc 0x7 0x0
 288 #define MX50_PAD_SD1_D1__ESDHC1_DAT1                            0x0f0 0x39c 0x000 0x0 0x0
 289 #define MX50_PAD_SD1_D1__GPIO5_3                                0x0f0 0x39c 0x000 0x1 0x0
 290 #define MX50_PAD_SD1_D1__CCM_PLL2_BYP                           0x0f0 0x39c 0x000 0x7 0x0
 291 #define MX50_PAD_SD1_D2__ESDHC1_DAT2                            0x0f4 0x3a0 0x000 0x0 0x0
 292 #define MX50_PAD_SD1_D2__GPIO5_4                                0x0f4 0x3a0 0x000 0x1 0x0
 293 #define MX50_PAD_SD1_D2__CCM_PLL3_BYP                           0x0f4 0x3a0 0x6e4 0x7 0x0
 294 #define MX50_PAD_SD1_D3__ESDHC1_DAT3                            0x0f8 0x3a4 0x000 0x0 0x0
 295 #define MX50_PAD_SD1_D3__GPIO5_5                                0x0f8 0x3a4 0x000 0x1 0x0
 296 #define MX50_PAD_SD2_CLK__ESDHC2_CLK                            0x0fc 0x3a8 0x000 0x0 0x0
 297 #define MX50_PAD_SD2_CLK__GPIO5_6                               0x0fc 0x3a8 0x000 0x1 0x0
 298 #define MX50_PAD_SD2_CLK__MSHC_SCLK                             0x0fc 0x3a8 0x000 0x2 0x0
 299 #define MX50_PAD_SD2_CMD__ESDHC2_CMD                            0x100 0x3ac 0x000 0x0 0x0
 300 #define MX50_PAD_SD2_CMD__GPIO5_7                               0x100 0x3ac 0x000 0x1 0x0
 301 #define MX50_PAD_SD2_CMD__MSHC_BS                               0x100 0x3ac 0x000 0x2 0x0
 302 #define MX50_PAD_SD2_D0__ESDHC2_DAT0                            0x104 0x3b0 0x000 0x0 0x0
 303 #define MX50_PAD_SD2_D0__GPIO5_8                                0x104 0x3b0 0x000 0x1 0x0
 304 #define MX50_PAD_SD2_D0__MSHC_DATA_0                            0x104 0x3b0 0x000 0x2 0x0
 305 #define MX50_PAD_SD2_D0__KPP_COL_4                              0x104 0x3b0 0x790 0x3 0x0
 306 #define MX50_PAD_SD2_D1__ESDHC2_DAT1                            0x108 0x3b4 0x000 0x0 0x0
 307 #define MX50_PAD_SD2_D1__GPIO5_9                                0x108 0x3b4 0x000 0x1 0x0
 308 #define MX50_PAD_SD2_D1__MSHC_DATA_1                            0x108 0x3b4 0x000 0x2 0x0
 309 #define MX50_PAD_SD2_D1__KPP_ROW_4                              0x108 0x3b4 0x7a0 0x3 0x0
 310 #define MX50_PAD_SD2_D2__ESDHC2_DAT2                            0x10c 0x3b8 0x000 0x0 0x0
 311 #define MX50_PAD_SD2_D2__GPIO5_10                               0x10c 0x3b8 0x000 0x1 0x0
 312 #define MX50_PAD_SD2_D2__MSHC_DATA_2                            0x10c 0x3b8 0x000 0x2 0x0
 313 #define MX50_PAD_SD2_D2__KPP_COL_5                              0x10c 0x3b8 0x794 0x3 0x0
 314 #define MX50_PAD_SD2_D3__ESDHC2_DAT3                            0x110 0x3bc 0x000 0x0 0x0
 315 #define MX50_PAD_SD2_D3__GPIO5_11                               0x110 0x3bc 0x000 0x1 0x0
 316 #define MX50_PAD_SD2_D3__MSHC_DATA_3                            0x110 0x3bc 0x000 0x2 0x0
 317 #define MX50_PAD_SD2_D3__KPP_ROW_5                              0x110 0x3bc 0x7a4 0x3 0x0
 318 #define MX50_PAD_SD2_D4__ESDHC2_DAT4                            0x114 0x3c0 0x000 0x0 0x0
 319 #define MX50_PAD_SD2_D4__GPIO5_12                               0x114 0x3c0 0x000 0x1 0x0
 320 #define MX50_PAD_SD2_D4__AUDMUX_AUD4_RXFS                       0x114 0x3c0 0x6d0 0x2 0x0
 321 #define MX50_PAD_SD2_D4__KPP_COL_6                              0x114 0x3c0 0x798 0x3 0x0
 322 #define MX50_PAD_SD2_D4__EIM_WEIM_D_0                           0x114 0x3c0 0x7ec 0x4 0x0
 323 #define MX50_PAD_SD2_D4__CCM_CCM_OUT_0                          0x114 0x3c0 0x000 0x7 0x0
 324 #define MX50_PAD_SD2_D5__ESDHC2_DAT5                            0x118 0x3c4 0x000 0x0 0x0
 325 #define MX50_PAD_SD2_D5__GPIO5_13                               0x118 0x3c4 0x000 0x1 0x0
 326 #define MX50_PAD_SD2_D5__AUDMUX_AUD4_RXC                        0x118 0x3c4 0x6cc 0x2 0x0
 327 #define MX50_PAD_SD2_D5__KPP_ROW_6                              0x118 0x3c4 0x7a8 0x3 0x0
 328 #define MX50_PAD_SD2_D5__EIM_WEIM_D_1                           0x118 0x3c4 0x7f0 0x4 0x0
 329 #define MX50_PAD_SD2_D5__CCM_CCM_OUT_1                          0x118 0x3c4 0x000 0x7 0x0
 330 #define MX50_PAD_SD2_D6__ESDHC2_DAT6                            0x11c 0x3c8 0x000 0x0 0x0
 331 #define MX50_PAD_SD2_D6__GPIO5_14                               0x11c 0x3c8 0x000 0x1 0x0
 332 #define MX50_PAD_SD2_D6__AUDMUX_AUD4_RXD                        0x11c 0x3c8 0x6c4 0x2 0x0
 333 #define MX50_PAD_SD2_D6__KPP_COL_7                              0x11c 0x3c8 0x79c 0x3 0x0
 334 #define MX50_PAD_SD2_D6__EIM_WEIM_D_2                           0x11c 0x3c8 0x7f4 0x4 0x0
 335 #define MX50_PAD_SD2_D6__CCM_CCM_OUT_2                          0x11c 0x3c8 0x000 0x7 0x0
 336 #define MX50_PAD_SD2_D7__ESDHC2_DAT7                            0x120 0x3cc 0x000 0x0 0x0
 337 #define MX50_PAD_SD2_D7__GPIO5_15                               0x120 0x3cc 0x000 0x1 0x0
 338 #define MX50_PAD_SD2_D7__AUDMUX_AUD4_TXFS                       0x120 0x3cc 0x6d8 0x2 0x0
 339 #define MX50_PAD_SD2_D7__KPP_ROW_7                              0x120 0x3cc 0x7ac 0x3 0x0
 340 #define MX50_PAD_SD2_D7__EIM_WEIM_D_3                           0x120 0x3cc 0x7f8 0x4 0x0
 341 #define MX50_PAD_SD2_D7__CCM_STOP                               0x120 0x3cc 0x000 0x7 0x0
 342 #define MX50_PAD_SD2_WP__ESDHC2_WP                              0x124 0x3d0 0x744 0x0 0x1
 343 #define MX50_PAD_SD2_WP__GPIO5_16                               0x124 0x3d0 0x000 0x1 0x0
 344 #define MX50_PAD_SD2_WP__AUDMUX_AUD4_TXD                        0x124 0x3d0 0x6c8 0x2 0x0
 345 #define MX50_PAD_SD2_WP__EIM_WEIM_D_4                           0x124 0x3d0 0x7fc 0x4 0x0
 346 #define MX50_PAD_SD2_WP__CCM_WAIT                               0x124 0x3d0 0x000 0x7 0x0
 347 #define MX50_PAD_SD2_CD__ESDHC2_CD                              0x128 0x3d4 0x740 0x0 0x1
 348 #define MX50_PAD_SD2_CD__GPIO5_17                               0x128 0x3d4 0x000 0x1 0x0
 349 #define MX50_PAD_SD2_CD__AUDMUX_AUD4_TXC                        0x128 0x3d4 0x6d4 0x2 0x0
 350 #define MX50_PAD_SD2_CD__EIM_WEIM_D_5                           0x128 0x3d4 0x800 0x4 0x0
 351 #define MX50_PAD_SD2_CD__CCM_REF_EN_B                           0x128 0x3d4 0x000 0x7 0x0
 352 #define MX50_PAD_DISP_D0__ELCDIF_DAT_0                          0x12c 0x40c 0x6fc 0x0 0x0
 353 #define MX50_PAD_DISP_D0__GPIO2_0                               0x12c 0x40c 0x000 0x1 0x0
 354 #define MX50_PAD_DISP_D0__FEC_TX_CLK                            0x12c 0x40c 0x78c 0x2 0x0
 355 #define MX50_PAD_DISP_D0__EIM_WEIM_A_16                         0x12c 0x40c 0x000 0x3 0x0
 356 #define MX50_PAD_DISP_D0__SDMA_DEBUG_PC_0                       0x12c 0x40c 0x000 0x6 0x0
 357 #define MX50_PAD_DISP_D0__USBPHY1_VSTATUS_0                     0x12c 0x40c 0x000 0x7 0x0
 358 #define MX50_PAD_DISP_D1__ELCDIF_DAT_1                          0x130 0x410 0x700 0x0 0x0
 359 #define MX50_PAD_DISP_D1__GPIO2_1                               0x130 0x410 0x000 0x1 0x0
 360 #define MX50_PAD_DISP_D1__FEC_RX_ERR                            0x130 0x410 0x788 0x2 0x0
 361 #define MX50_PAD_DISP_D1__EIM_WEIM_A_17                         0x130 0x410 0x000 0x3 0x0
 362 #define MX50_PAD_DISP_D1__SDMA_DEBUG_PC_1                       0x130 0x410 0x000 0x6 0x0
 363 #define MX50_PAD_DISP_D1__USBPHY1_VSTATUS_1                     0x130 0x410 0x000 0x7 0x0
 364 #define MX50_PAD_DISP_D2__ELCDIF_DAT_2                          0x134 0x414 0x704 0x0 0x0
 365 #define MX50_PAD_DISP_D2__GPIO2_2                               0x134 0x414 0x000 0x1 0x0
 366 #define MX50_PAD_DISP_D2__FEC_RX_DV                             0x134 0x414 0x784 0x2 0x0
 367 #define MX50_PAD_DISP_D2__EIM_WEIM_A_18                         0x134 0x414 0x000 0x3 0x0
 368 #define MX50_PAD_DISP_D2__SDMA_DEBUG_PC_2                       0x134 0x414 0x000 0x6 0x0
 369 #define MX50_PAD_DISP_D2__USBPHY1_VSTATUS_2                     0x134 0x414 0x000 0x7 0x0
 370 #define MX50_PAD_DISP_D3__ELCDIF_DAT_3                          0x138 0x418 0x708 0x0 0x0
 371 #define MX50_PAD_DISP_D3__GPIO2_3                               0x138 0x418 0x000 0x1 0x0
 372 #define MX50_PAD_DISP_D3__FEC_RDATA_1                           0x138 0x418 0x77c 0x2 0x0
 373 #define MX50_PAD_DISP_D3__EIM_WEIM_A_19                         0x138 0x418 0x000 0x3 0x0
 374 #define MX50_PAD_DISP_D3__FEC_COL                               0x138 0x418 0x770 0x4 0x1
 375 #define MX50_PAD_DISP_D3__SDMA_DEBUG_PC_3                       0x138 0x418 0x000 0x6 0x0
 376 #define MX50_PAD_DISP_D3__USBPHY1_VSTATUS_3                     0x138 0x418 0x000 0x7 0x0
 377 #define MX50_PAD_DISP_D4__ELCDIF_DAT_4                          0x13c 0x41c 0x70c 0x0 0x0
 378 #define MX50_PAD_DISP_D4__GPIO2_4                               0x13c 0x41c 0x000 0x1 0x0
 379 #define MX50_PAD_DISP_D4__FEC_RDATA_0                           0x13c 0x41c 0x778 0x2 0x0
 380 #define MX50_PAD_DISP_D4__EIM_WEIM_A_20                         0x13c 0x41c 0x000 0x3 0x0
 381 #define MX50_PAD_DISP_D4__SDMA_DEBUG_PC_4                       0x13c 0x41c 0x000 0x6 0x0
 382 #define MX50_PAD_DISP_D4__USBPHY1_VSTATUS_4                     0x13c 0x41c 0x000 0x7 0x0
 383 #define MX50_PAD_DISP_D5__ELCDIF_DAT_5                          0x140 0x420 0x710 0x0 0x0
 384 #define MX50_PAD_DISP_D5__GPIO2_5                               0x140 0x420 0x000 0x1 0x0
 385 #define MX50_PAD_DISP_D5__FEC_TX_EN                             0x140 0x420 0x000 0x2 0x0
 386 #define MX50_PAD_DISP_D5__EIM_WEIM_A_21                         0x140 0x420 0x000 0x3 0x0
 387 #define MX50_PAD_DISP_D5__SDMA_DEBUG_PC_5                       0x140 0x420 0x000 0x6 0x0
 388 #define MX50_PAD_DISP_D5__USBPHY1_VSTATUS_5                     0x140 0x420 0x000 0x7 0x0
 389 #define MX50_PAD_DISP_D6__ELCDIF_DAT_6                          0x144 0x424 0x714 0x0 0x0
 390 #define MX50_PAD_DISP_D6__GPIO2_6                               0x144 0x424 0x000 0x1 0x0
 391 #define MX50_PAD_DISP_D6__FEC_TDATA_1                           0x144 0x424 0x000 0x2 0x0
 392 #define MX50_PAD_DISP_D6__EIM_WEIM_A_22                         0x144 0x424 0x000 0x3 0x0
 393 #define MX50_PAD_DISP_D6__FEC_RX_CLK                            0x144 0x424 0x780 0x4 0x1
 394 #define MX50_PAD_DISP_D6__SDMA_DEBUG_PC_6                       0x144 0x424 0x000 0x6 0x0
 395 #define MX50_PAD_DISP_D6__USBPHY1_VSTATUS_6                     0x144 0x424 0x000 0x7 0x0
 396 #define MX50_PAD_DISP_D7__ELCDIF_DAT_7                          0x148 0x428 0x718 0x0 0x0
 397 #define MX50_PAD_DISP_D7__GPIO2_7                               0x148 0x428 0x000 0x1 0x0
 398 #define MX50_PAD_DISP_D7__FEC_TDATA_0                           0x148 0x428 0x000 0x2 0x0
 399 #define MX50_PAD_DISP_D7__EIM_WEIM_A_23                         0x148 0x428 0x000 0x3 0x0
 400 #define MX50_PAD_DISP_D7__SDMA_DEBUG_PC_7                       0x148 0x428 0x000 0x6 0x0
 401 #define MX50_PAD_DISP_D7__USBPHY1_VSTATUS_7                     0x148 0x428 0x000 0x7 0x0
 402 #define MX50_PAD_DISP_WR__ELCDIF_WR_RWN                         0x14c 0x42c 0x000 0x0 0x0
 403 #define MX50_PAD_DISP_WR__GPIO2_16                              0x14c 0x42c 0x000 0x1 0x0
 404 #define MX50_PAD_DISP_WR__ELCDIF_DOTCLK                         0x14c 0x42c 0x000 0x2 0x0
 405 #define MX50_PAD_DISP_WR__EIM_WEIM_A_24                         0x14c 0x42c 0x000 0x3 0x0
 406 #define MX50_PAD_DISP_WR__SDMA_DEBUG_PC_8                       0x14c 0x42c 0x000 0x6 0x0
 407 #define MX50_PAD_DISP_WR__USBPHY1_AVALID                        0x14c 0x42c 0x000 0x7 0x0
 408 #define MX50_PAD_DISP_RD__ELCDIF_RD_E                           0x150 0x430 0x000 0x0 0x0
 409 #define MX50_PAD_DISP_RD__GPIO2_19                              0x150 0x430 0x000 0x1 0x0
 410 #define MX50_PAD_DISP_RD__ELCDIF_ENABLE                         0x150 0x430 0x000 0x2 0x0
 411 #define MX50_PAD_DISP_RD__EIM_WEIM_A_25                         0x150 0x430 0x000 0x3 0x0
 412 #define MX50_PAD_DISP_RD__SDMA_DEBUG_PC_9                       0x150 0x430 0x000 0x6 0x0
 413 #define MX50_PAD_DISP_RD__USBPHY1_BVALID                        0x150 0x430 0x000 0x7 0x0
 414 #define MX50_PAD_DISP_RS__ELCDIF_RS                             0x154 0x434 0x000 0x0 0x0
 415 #define MX50_PAD_DISP_RS__GPIO2_17                              0x154 0x434 0x000 0x1 0x0
 416 #define MX50_PAD_DISP_RS__ELCDIF_VSYNC                          0x154 0x434 0x73c 0x2 0x1
 417 #define MX50_PAD_DISP_RS__EIM_WEIM_A_26                         0x154 0x434 0x000 0x3 0x0
 418 #define MX50_PAD_DISP_RS__SDMA_DEBUG_PC_10                      0x154 0x434 0x000 0x6 0x0
 419 #define MX50_PAD_DISP_RS__USBPHY1_ENDSESSION                    0x154 0x434 0x000 0x7 0x0
 420 #define MX50_PAD_DISP_CS__ELCDIF_CS                             0x158 0x438 0x000 0x0 0x0
 421 #define MX50_PAD_DISP_CS__GPIO2_21                              0x158 0x438 0x000 0x1 0x0
 422 #define MX50_PAD_DISP_CS__ELCDIF_HSYNC                          0x158 0x438 0x6f8 0x2 0x1
 423 #define MX50_PAD_DISP_CS__EIM_WEIM_A_27                         0x158 0x438 0x000 0x3 0x0
 424 #define MX50_PAD_DISP_CS__EIM_WEIM_CS_3                         0x158 0x438 0x000 0x4 0x0
 425 #define MX50_PAD_DISP_CS__SDMA_DEBUG_PC_11                      0x158 0x438 0x000 0x6 0x0
 426 #define MX50_PAD_DISP_CS__USBPHY1_IDDIG                         0x158 0x438 0x000 0x7 0x0
 427 #define MX50_PAD_DISP_BUSY__ELCDIF_BUSY                         0x15c 0x43c 0x6f8 0x0 0x2
 428 #define MX50_PAD_DISP_BUSY__GPIO2_18                            0x15c 0x43c 0x000 0x1 0x0
 429 #define MX50_PAD_DISP_BUSY__EIM_WEIM_CS_3                       0x15c 0x43c 0x000 0x4 0x0
 430 #define MX50_PAD_DISP_BUSY__SDMA_DEBUG_PC_12                    0x15c 0x43c 0x000 0x6 0x0
 431 #define MX50_PAD_DISP_BUSY__USBPHY2_HOSTDISCONNECT              0x15c 0x43c 0x000 0x7 0x0
 432 #define MX50_PAD_DISP_RESET__ELCDIF_RESET                       0x160 0x440 0x000 0x0 0x0
 433 #define MX50_PAD_DISP_RESET__GPIO2_20                           0x160 0x440 0x000 0x1 0x0
 434 #define MX50_PAD_DISP_RESET__EIM_WEIM_CS_3                      0x160 0x440 0x000 0x4 0x0
 435 #define MX50_PAD_DISP_RESET__SDMA_DEBUG_PC_13                   0x160 0x440 0x000 0x6 0x0
 436 #define MX50_PAD_DISP_RESET__USBPHY2_BISTOK                     0x160 0x440 0x000 0x7 0x0
 437 #define MX50_PAD_SD3_CMD__ESDHC3_CMD                            0x164 0x444 0x000 0x0 0x0
 438 #define MX50_PAD_SD3_CMD__GPIO5_18                              0x164 0x444 0x000 0x1 0x0
 439 #define MX50_PAD_SD3_CMD__EIM_NANDF_WRN                         0x164 0x444 0x000 0x2 0x0
 440 #define MX50_PAD_SD3_CMD__SSP_CMD                               0x164 0x444 0x000 0x3 0x0
 441 #define MX50_PAD_SD3_CLK__ESDHC3_CLK                            0x168 0x448 0x000 0x0 0x0
 442 #define MX50_PAD_SD3_CLK__GPIO5_19                              0x168 0x448 0x000 0x1 0x0
 443 #define MX50_PAD_SD3_CLK__EIM_NANDF_RDN                         0x168 0x448 0x000 0x2 0x0
 444 #define MX50_PAD_SD3_CLK__SSP_CLK                               0x168 0x448 0x000 0x3 0x0
 445 #define MX50_PAD_SD3_D0__ESDHC3_DAT0                            0x16c 0x44c 0x000 0x0 0x0
 446 #define MX50_PAD_SD3_D0__GPIO5_20                               0x16c 0x44c 0x000 0x1 0x0
 447 #define MX50_PAD_SD3_D0__EIM_NANDF_D_4                          0x16c 0x44c 0x000 0x2 0x0
 448 #define MX50_PAD_SD3_D0__SSP_D0                                 0x16c 0x44c 0x000 0x3 0x0
 449 #define MX50_PAD_SD3_D0__CCM_PLL1_BYP                           0x16c 0x44c 0x6dc 0x7 0x1
 450 #define MX50_PAD_SD3_D1__ESDHC3_DAT1                            0x170 0x450 0x000 0x0 0x0
 451 #define MX50_PAD_SD3_D1__GPIO5_21                               0x170 0x450 0x000 0x1 0x0
 452 #define MX50_PAD_SD3_D1__EIM_NANDF_D_5                          0x170 0x450 0x000 0x2 0x0
 453 #define MX50_PAD_SD3_D1__SSP_D1                                 0x170 0x450 0x000 0x3 0x0
 454 #define MX50_PAD_SD3_D1__CCM_PLL2_BYP                           0x170 0x450 0x000 0x7 0x0
 455 #define MX50_PAD_SD3_D2__ESDHC3_DAT2                            0x174 0x454 0x000 0x0 0x0
 456 #define MX50_PAD_SD3_D2__GPIO5_22                               0x174 0x454 0x000 0x1 0x0
 457 #define MX50_PAD_SD3_D2__EIM_NANDF_D_6                          0x174 0x454 0x000 0x2 0x0
 458 #define MX50_PAD_SD3_D2__SSP_D2                                 0x174 0x454 0x000 0x3 0x0
 459 #define MX50_PAD_SD3_D2__CCM_PLL3_BYP                           0x174 0x454 0x6e4 0x7 0x1
 460 #define MX50_PAD_SD3_D3__ESDHC3_DAT3                            0x178 0x458 0x000 0x0 0x0
 461 #define MX50_PAD_SD3_D3__GPIO5_23                               0x178 0x458 0x000 0x1 0x0
 462 #define MX50_PAD_SD3_D3__EIM_NANDF_D_7                          0x178 0x458 0x000 0x2 0x0
 463 #define MX50_PAD_SD3_D3__SSP_D3                                 0x178 0x458 0x000 0x3 0x0
 464 #define MX50_PAD_SD3_D4__ESDHC3_DAT4                            0x17c 0x45c 0x000 0x0 0x0
 465 #define MX50_PAD_SD3_D4__GPIO5_24                               0x17c 0x45c 0x000 0x1 0x0
 466 #define MX50_PAD_SD3_D4__EIM_NANDF_D_0                          0x17c 0x45c 0x000 0x2 0x0
 467 #define MX50_PAD_SD3_D4__SSP_D4                                 0x17c 0x45c 0x000 0x3 0x0
 468 #define MX50_PAD_SD3_D5__ESDHC3_DAT5                            0x180 0x460 0x000 0x0 0x0
 469 #define MX50_PAD_SD3_D5__GPIO5_25                               0x180 0x460 0x000 0x1 0x0
 470 #define MX50_PAD_SD3_D5__EIM_NANDF_D_1                          0x180 0x460 0x000 0x2 0x0
 471 #define MX50_PAD_SD3_D5__SSP_D5                                 0x180 0x460 0x000 0x3 0x0
 472 #define MX50_PAD_SD3_D6__ESDHC3_DAT6                            0x184 0x464 0x000 0x0 0x0
 473 #define MX50_PAD_SD3_D6__GPIO5_26                               0x184 0x464 0x000 0x1 0x0
 474 #define MX50_PAD_SD3_D6__EIM_NANDF_D_2                          0x184 0x464 0x000 0x2 0x0
 475 #define MX50_PAD_SD3_D6__SSP_D6                                 0x184 0x464 0x000 0x3 0x0
 476 #define MX50_PAD_SD3_D7__ESDHC3_DAT7                            0x188 0x468 0x000 0x0 0x0
 477 #define MX50_PAD_SD3_D7__GPIO5_27                               0x188 0x468 0x000 0x1 0x0
 478 #define MX50_PAD_SD3_D7__EIM_NANDF_D_3                          0x188 0x468 0x000 0x2 0x0
 479 #define MX50_PAD_SD3_D7__SSP_D7                                 0x188 0x468 0x000 0x3 0x0
 480 #define MX50_PAD_SD3_WP__ESDHC3_WP                              0x18c 0x46C 0x000 0x0 0x0
 481 #define MX50_PAD_SD3_WP__GPIO5_28                               0x18c 0x46C 0x000 0x1 0x0
 482 #define MX50_PAD_SD3_WP__EIM_NANDF_RESETN                       0x18c 0x46C 0x000 0x2 0x0
 483 #define MX50_PAD_SD3_WP__SSP_CD                                 0x18c 0x46C 0x000 0x3 0x0
 484 #define MX50_PAD_SD3_WP__ESDHC4_LCTL                            0x18c 0x46C 0x000 0x4 0x0
 485 #define MX50_PAD_SD3_WP__EIM_WEIM_CS_3                          0x18c 0x46C 0x000 0x5 0x0
 486 #define MX50_PAD_DISP_D8__ELCDIF_DAT_8                          0x190 0x470 0x71c 0x0 0x0
 487 #define MX50_PAD_DISP_D8__GPIO2_8                               0x190 0x470 0x000 0x1 0x0
 488 #define MX50_PAD_DISP_D8__EIM_NANDF_CLE                         0x190 0x470 0x000 0x2 0x0
 489 #define MX50_PAD_DISP_D8__ESDHC1_LCTL                           0x190 0x470 0x000 0x3 0x0
 490 #define MX50_PAD_DISP_D8__ESDHC4_CMD                            0x190 0x470 0x74c 0x4 0x2
 491 #define MX50_PAD_DISP_D8__KPP_COL_4                             0x190 0x470 0x790 0x5 0x1
 492 #define MX50_PAD_DISP_D8__FEC_TX_CLK                            0x190 0x470 0x78c 0x6 0x1
 493 #define MX50_PAD_DISP_D8__USBPHY1_DATAOUT_0                     0x190 0x470 0x000 0x7 0x0
 494 #define MX50_PAD_DISP_D9__ELCDIF_DAT_9                          0x194 0x474 0x720 0x0 0x0
 495 #define MX50_PAD_DISP_D9__GPIO2_9                               0x194 0x474 0x000 0x1 0x0
 496 #define MX50_PAD_DISP_D9__EIM_NANDF_ALE                         0x194 0x474 0x000 0x2 0x0
 497 #define MX50_PAD_DISP_D9__ESDHC2_LCTL                           0x194 0x474 0x000 0x3 0x0
 498 #define MX50_PAD_DISP_D9__ESDHC4_CLK                            0x194 0x474 0x748 0x4 0x2
 499 #define MX50_PAD_DISP_D9__KPP_ROW_4                             0x194 0x474 0x7a0 0x5 0x1
 500 #define MX50_PAD_DISP_D9__FEC_RX_ER                             0x194 0x474 0x788 0x6 0x1
 501 #define MX50_PAD_DISP_D9__USBPHY1_DATAOUT_1                     0x194 0x474 0x000 0x7 0x0
 502 #define MX50_PAD_DISP_D10__ELCDIF_DAT_10                        0x198 0x478 0x724 0x0 0x0
 503 #define MX50_PAD_DISP_D10__GPIO2_10                             0x198 0x478 0x000 0x1 0x0
 504 #define MX50_PAD_DISP_D10__EIM_NANDF_CEN_0                      0x198 0x478 0x000 0x2 0x0
 505 #define MX50_PAD_DISP_D10__ESDHC3_LCTL                          0x198 0x478 0x000 0x3 0x0
 506 #define MX50_PAD_DISP_D10__ESDHC4_DAT0                          0x198 0x478 0x000 0x4 0x0
 507 #define MX50_PAD_DISP_D10__KPP_COL_5                            0x198 0x478 0x794 0x5 0x1
 508 #define MX50_PAD_DISP_D10__FEC_RX_DV                            0x198 0x478 0x784 0x6 0x1
 509 #define MX50_PAD_DISP_D10__USBPHY1_DATAOUT_2                    0x198 0x478 0x000 0x7 0x0
 510 #define MX50_PAD_DISP_D11__ELCDIF_DAT_11                        0x19c 0x47c 0x728 0x0 0x0
 511 #define MX50_PAD_DISP_D11__GPIO2_11                             0x19c 0x47c 0x000 0x1 0x0
 512 #define MX50_PAD_DISP_D11__EIM_NANDF_CEN_1                      0x19c 0x47c 0x000 0x2 0x0
 513 #define MX50_PAD_DISP_D11__ESDHC4_DAT1                          0x19c 0x47c 0x754 0x4 0x1
 514 #define MX50_PAD_DISP_D11__KPP_ROW_5                            0x19c 0x47c 0x7a4 0x5 0x1
 515 #define MX50_PAD_DISP_D11__FEC_RDATA_1                          0x19c 0x47c 0x77c 0x6 0x1
 516 #define MX50_PAD_DISP_D11__USBPHY1_DATAOUT_3                    0x19c 0x47c 0x000 0x7 0x0
 517 #define MX50_PAD_DISP_D12__ELCDIF_DAT_12                        0x1a0 0x480 0x72c 0x0 0x0
 518 #define MX50_PAD_DISP_D12__GPIO2_12                             0x1a0 0x480 0x000 0x1 0x0
 519 #define MX50_PAD_DISP_D12__EIM_NANDF_CEN_2                      0x1a0 0x480 0x000 0x2 0x0
 520 #define MX50_PAD_DISP_D12__ESDHC1_CD                            0x1a0 0x480 0x000 0x3 0x0
 521 #define MX50_PAD_DISP_D12__ESDHC4_DAT2                          0x1a0 0x480 0x758 0x4 0x1
 522 #define MX50_PAD_DISP_D12__KPP_COL_6                            0x1a0 0x480 0x798 0x5 0x1
 523 #define MX50_PAD_DISP_D12__FEC_RDATA_0                          0x1a0 0x480 0x778 0x6 0x1
 524 #define MX50_PAD_DISP_D12__USBPHY1_DATAOUT_4                    0x1a0 0x480 0x000 0x7 0x0
 525 #define MX50_PAD_DISP_D13__ELCDIF_DAT_13                        0x1a4 0x484 0x730 0x0 0x0
 526 #define MX50_PAD_DISP_D13__GPIO2_13                             0x1a4 0x484 0x000 0x1 0x0
 527 #define MX50_PAD_DISP_D13__EIM_NANDF_CEN_3                      0x1a4 0x484 0x000 0x2 0x0
 528 #define MX50_PAD_DISP_D13__ESDHC3_CD                            0x1a4 0x484 0x000 0x3 0x0
 529 #define MX50_PAD_DISP_D13__ESDHC4_DAT3                          0x1a4 0x484 0x75c 0x4 0x1
 530 #define MX50_PAD_DISP_D13__KPP_ROW_6                            0x1a4 0x484 0x7a8 0x5 0x1
 531 #define MX50_PAD_DISP_D13__FEC_TX_EN                            0x1a4 0x484 0x000 0x6 0x0
 532 #define MX50_PAD_DISP_D13__USBPHY1_DATAOUT_5                    0x1a4 0x484 0x000 0x7 0x0
 533 #define MX50_PAD_DISP_D14__ELCDIF_DAT_14                        0x1a8 0x488 0x734 0x0 0x0
 534 #define MX50_PAD_DISP_D14__GPIO2_14                             0x1a8 0x488 0x000 0x1 0x0
 535 #define MX50_PAD_DISP_D14__EIM_NANDF_READY0                     0x1a8 0x488 0x7b4 0x2 0x1
 536 #define MX50_PAD_DISP_D14__ESDHC1_WP                            0x1a8 0x488 0x000 0x3 0x0
 537 #define MX50_PAD_DISP_D14__ESDHC4_WP                            0x1a8 0x488 0x000 0x4 0x0
 538 #define MX50_PAD_DISP_D14__KPP_COL_7                            0x1a8 0x488 0x79c 0x5 0x1
 539 #define MX50_PAD_DISP_D14__FEC_TDATA_1                          0x1a8 0x488 0x000 0x6 0x0
 540 #define MX50_PAD_DISP_D14__USBPHY1_DATAOUT_6                    0x1a8 0x488 0x000 0x7 0x0
 541 #define MX50_PAD_DISP_D15__ELCDIF_DAT_15                        0x1ac 0x48c 0x738 0x0 0x0
 542 #define MX50_PAD_DISP_D15__GPIO2_15                             0x1ac 0x48c 0x000 0x1 0x0
 543 #define MX50_PAD_DISP_D15__EIM_NANDF_DQS                        0x1ac 0x48c 0x7b0 0x2 0x1
 544 #define MX50_PAD_DISP_D15__ESDHC3_RST                           0x1ac 0x48c 0x000 0x3 0x0
 545 #define MX50_PAD_DISP_D15__ESDHC4_CD                            0x1ac 0x48c 0x000 0x4 0x0
 546 #define MX50_PAD_DISP_D15__KPP_ROW_7                            0x1ac 0x48c 0x7ac 0x5 0x1
 547 #define MX50_PAD_DISP_D15__FEC_TDATA_0                          0x1ac 0x48c 0x000 0x6 0x0
 548 #define MX50_PAD_DISP_D15__USBPHY1_DATAOUT_7                    0x1ac 0x48c 0x000 0x7 0x0
 549 #define MX50_PAD_EPDC_D0__EPDC_SDDO_0                           0x1b0 0x54c 0x000 0x0 0x0
 550 #define MX50_PAD_EPDC_D0__GPIO3_0                               0x1b0 0x54c 0x000 0x1 0x0
 551 #define MX50_PAD_EPDC_D0__EIM_WEIM_D_0                          0x1b0 0x54c 0x7ec 0x2 0x1
 552 #define MX50_PAD_EPDC_D0__ELCDIF_RS                             0x1b0 0x54c 0x000 0x3 0x0
 553 #define MX50_PAD_EPDC_D0__ELCDIF_DOTCLK                         0x1b0 0x54c 0x000 0x4 0x0
 554 #define MX50_PAD_EPDC_D0__SDMA_DEBUG_EVT_CHN_LINES_0            0x1b0 0x54c 0x000 0x6 0x0
 555 #define MX50_PAD_EPDC_D0__USBPHY2_DATAOUT_0                     0x1b0 0x54c 0x000 0x7 0x0
 556 #define MX50_PAD_EPDC_D1__EPDC_SDDO_1                           0x1b4 0x550 0x000 0x0 0x0
 557 #define MX50_PAD_EPDC_D1__GPIO3_1                               0x1b4 0x550 0x000 0x1 0x0
 558 #define MX50_PAD_EPDC_D1__EIM_WEIM_D_1                          0x1b4 0x550 0x7f0 0x2 0x1
 559 #define MX50_PAD_EPDC_D1__ELCDIF_CS                             0x1b4 0x550 0x000 0x3 0x0
 560 #define MX50_PAD_EPDC_D1__ELCDIF_ENABLE                         0x1b4 0x550 0x000 0x4 0x0
 561 #define MX50_PAD_EPDC_D1__SDMA_DEBUG_EVT_CHN_LINES_1            0x1b4 0x550 0x000 0x6 0x0
 562 #define MX50_PAD_EPDC_D1__USBPHY2_DATAOUT_1                     0x1b4 0x550 0x000 0x7 0x0
 563 #define MX50_PAD_EPDC_D2__EPDC_SDDO_2                           0x1b8 0x554 0x000 0x0 0x0
 564 #define MX50_PAD_EPDC_D2__GPIO3_2                               0x1b8 0x554 0x000 0x1 0x0
 565 #define MX50_PAD_EPDC_D2__EIM_WEIM_D_2                          0x1b8 0x554 0x7f4 0x2 0x1
 566 #define MX50_PAD_EPDC_D2__ELCDIF_WR_RWN                         0x1b8 0x554 0x000 0x3 0x0
 567 #define MX50_PAD_EPDC_D2__ELCDIF_VSYNC                          0x1b8 0x554 0x73c 0x4 0x2
 568 #define MX50_PAD_EPDC_D2__SDMA_DEBUG_EVT_CHN_LINES_2            0x1b8 0x554 0x000 0x6 0x0
 569 #define MX50_PAD_EPDC_D2__USBPHY2_DATAOUT_2                     0x1b8 0x554 0x000 0x7 0x0
 570 #define MX50_PAD_EPDC_D3__EPDC_SDDO_3                           0x1bc 0x558 0x000 0x0 0x0
 571 #define MX50_PAD_EPDC_D3__GPIO3_3                               0x1bc 0x558 0x000 0x1 0x0
 572 #define MX50_PAD_EPDC_D3__EIM_WEIM_D_3                          0x1bc 0x558 0x7f8 0x2 0x1
 573 #define MX50_PAD_EPDC_D3__ELCDIF_RD_E                           0x1bc 0x558 0x000 0x3 0x0
 574 #define MX50_PAD_EPDC_D3__ELCDIF_HSYNC                          0x1bc 0x558 0x6f8 0x4 0x3
 575 #define MX50_PAD_EPDC_D3__SDMA_DEBUG_EVT_CHN_LINES_3            0x1bc 0x558 0x000 0x6 0x0
 576 #define MX50_PAD_EPDC_D3__USBPHY2_DATAOUT_3                     0x1bc 0x558 0x000 0x7 0x0
 577 #define MX50_PAD_EPDC_D4__EPDC_SDDO_4                           0x1c0 0x55c 0x000 0x0 0x0
 578 #define MX50_PAD_EPDC_D4__GPIO3_4                               0x1c0 0x55c 0x000 0x1 0x0
 579 #define MX50_PAD_EPDC_D4__EIM_WEIM_D_4                          0x1c0 0x55c 0x7fc 0x2 0x1
 580 #define MX50_PAD_EPDC_D4__SDMA_DEBUG_EVT_CHN_LINES_4            0x1c0 0x55c 0x000 0x6 0x0
 581 #define MX50_PAD_EPDC_D4__USBPHY2_DATAOUT_4                     0x1c0 0x55c 0x000 0x7 0x0
 582 #define MX50_PAD_EPDC_D5__EPDC_SDDO_5                           0x1c4 0x560 0x000 0x0 0x0
 583 #define MX50_PAD_EPDC_D5__GPIO3_5                               0x1c4 0x560 0x000 0x1 0x0
 584 #define MX50_PAD_EPDC_D5__EIM_WEIM_D_5                          0x1c4 0x560 0x800 0x2 0x1
 585 #define MX50_PAD_EPDC_D5__SDMA_DEBUG_EVT_CHN_LINES_5            0x1c4 0x560 0x000 0x6 0x0
 586 #define MX50_PAD_EPDC_D5__USBPHY2_DATAOUT_5                     0x1c4 0x560 0x000 0x7 0x0
 587 #define MX50_PAD_EPDC_D6__EPDC_SDDO_6                           0x1c8 0x564 0x000 0x0 0x0
 588 #define MX50_PAD_EPDC_D6__GPIO3_6                               0x1c8 0x564 0x000 0x1 0x0
 589 #define MX50_PAD_EPDC_D6__EIM_WEIM_D_6                          0x1c8 0x564 0x804 0x2 0x1
 590 #define MX50_PAD_EPDC_D6__SDMA_DEBUG_EVT_CHN_LINES_6            0x1c8 0x564 0x000 0x6 0x0
 591 #define MX50_PAD_EPDC_D6__USBPHY2_DATAOUT_6                     0x1c8 0x564 0x000 0x7 0x0
 592 #define MX50_PAD_EPDC_D7__EPDC_SDDO_7                           0x1cc 0x568 0x000 0x0 0x0
 593 #define MX50_PAD_EPDC_D7__GPIO3_7                               0x1cc 0x568 0x000 0x1 0x0
 594 #define MX50_PAD_EPDC_D7__EIM_WEIM_D_7                          0x1cc 0x568 0x808 0x2 0x1
 595 #define MX50_PAD_EPDC_D7__SDMA_DEBUG_EVT_CHN_LINES_7            0x1cc 0x568 0x000 0x6 0x0
 596 #define MX50_PAD_EPDC_D7__USBPHY2_DATAOUT_7                     0x1cc 0x568 0x000 0x7 0x0
 597 #define MX50_PAD_EPDC_D8__EPDC_SDDO_8                           0x1d0 0x56c 0x000 0x0 0x0
 598 #define MX50_PAD_EPDC_D8__GPIO3_8                               0x1d0 0x56c 0x000 0x1 0x0
 599 #define MX50_PAD_EPDC_D8__EIM_WEIM_D_8                          0x1d0 0x56c 0x80c 0x2 0x2
 600 #define MX50_PAD_EPDC_D8__ELCDIF_DAT_24                         0x1d0 0x56c 0x000 0x3 0x0
 601 #define MX50_PAD_EPDC_D8__SDMA_DEBUG_MATCHED_DMBUS              0x1d0 0x56c 0x000 0x6 0x0
 602 #define MX50_PAD_EPDC_D8__USBPHY2_VSTATUS_0                     0x1d0 0x56c 0x000 0x7 0x0
 603 #define MX50_PAD_EPDC_D9__EPDC_SDDO_9                           0x1d4 0x570 0x000 0x0 0x0
 604 #define MX50_PAD_EPDC_D9__GPIO3_9                               0x1d4 0x570 0x000 0x1 0x0
 605 #define MX50_PAD_EPDC_D9__EIM_WEIM_D_9                          0x1d4 0x570 0x810 0x2 0x2
 606 #define MX50_PAD_EPDC_D9__ELCDIF_DAT_25                         0x1d4 0x570 0x000 0x3 0x0
 607 #define MX50_PAD_EPDC_D9__SDMA_DEBUG_EVENT_CHANNEL_SEL          0x1d4 0x570 0x000 0x6 0x0
 608 #define MX50_PAD_EPDC_D9__USBPHY2_VSTATUS_1                     0x1d4 0x570 0x000 0x7 0x0
 609 #define MX50_PAD_EPDC_D10__EPDC_SDDO_10                         0x1d8 0x574 0x000 0x0 0x0
 610 #define MX50_PAD_EPDC_D10__GPIO3_10                             0x1d8 0x574 0x000 0x1 0x0
 611 #define MX50_PAD_EPDC_D10__EIM_WEIM_D_10                        0x1d8 0x574 0x814 0x2 0x2
 612 #define MX50_PAD_EPDC_D10__ELCDIF_DAT_26                        0x1d8 0x574 0x000 0x3 0x0
 613 #define MX50_PAD_EPDC_D10__SDMA_DEBUG_EVENT_CHANNEL_0           0x1d8 0x574 0x000 0x6 0x0
 614 #define MX50_PAD_EPDC_D10__USBPHY2_VSTATUS_2                    0x1d8 0x574 0x000 0x7 0x0
 615 #define MX50_PAD_EPDC_D11__EPDC_SDDO_11                         0x1dc 0x578 0x000 0x0 0x0
 616 #define MX50_PAD_EPDC_D11__GPIO3_11                             0x1dc 0x578 0x000 0x1 0x0
 617 #define MX50_PAD_EPDC_D11__EIM_WEIM_D_11                        0x1dc 0x578 0x818 0x2 0x2
 618 #define MX50_PAD_EPDC_D11__ELCDIF_DAT_27                        0x1dc 0x578 0x000 0x3 0x0
 619 #define MX50_PAD_EPDC_D11__SDMA_DEBUG_EVENT_CHANNEL_1           0x1dc 0x578 0x000 0x6 0x0
 620 #define MX50_PAD_EPDC_D11__USBPHY2_VSTATUS_3                    0x1dc 0x578 0x000 0x7 0x0
 621 #define MX50_PAD_EPDC_D12__EPDC_SDDO_12                         0x1e0 0x57c 0x000 0x0 0x0
 622 #define MX50_PAD_EPDC_D12__GPIO3_12                             0x1e0 0x57c 0x000 0x1 0x0
 623 #define MX50_PAD_EPDC_D12__EIM_WEIM_D_12                        0x1e0 0x57c 0x81c 0x2 0x1
 624 #define MX50_PAD_EPDC_D12__ELCDIF_DAT_28                        0x1e0 0x57c 0x000 0x3 0x0
 625 #define MX50_PAD_EPDC_D12__SDMA_DEBUG_EVENT_CHANNEL_2           0x1e0 0x57c 0x000 0x6 0x0
 626 #define MX50_PAD_EPDC_D12__USBPHY2_VSTATUS_4                    0x1e0 0x57c 0x000 0x7 0x0
 627 #define MX50_PAD_EPDC_D13__EPDC_SDDO_13                         0x1e4 0x580 0x000 0x0 0x0
 628 #define MX50_PAD_EPDC_D13__GPIO3_13                             0x1e4 0x580 0x000 0x1 0x0
 629 #define MX50_PAD_EPDC_D13__EIM_WEIM_D_13                        0x1e4 0x580 0x820 0x2 0x1
 630 #define MX50_PAD_EPDC_D13__ELCDIF_DAT_29                        0x1e4 0x580 0x000 0x3 0x0
 631 #define MX50_PAD_EPDC_D13__SDMA_DEBUG_EVENT_CHANNEL_3           0x1e4 0x580 0x000 0x6 0x0
 632 #define MX50_PAD_EPDC_D13__USBPHY2_VSTATUS_5                    0x1e4 0x580 0x000 0x7 0x0
 633 #define MX50_PAD_EPDC_D14__EPDC_SDDO_14                         0x1e8 0x584 0x000 0x0 0x0
 634 #define MX50_PAD_EPDC_D14__GPIO3_14                             0x1e8 0x584 0x000 0x1 0x0
 635 #define MX50_PAD_EPDC_D14__EIM_WEIM_D_14                        0x1e8 0x584 0x824 0x2 0x1
 636 #define MX50_PAD_EPDC_D14__ELCDIF_DAT_30                        0x1e8 0x584 0x000 0x3 0x0
 637 #define MX50_PAD_EPDC_D14__AUDMUX_AUD6_TXD                      0x1e8 0x584 0x000 0x4 0x0
 638 #define MX50_PAD_EPDC_D14__SDMA_DEBUG_EVENT_CHANNEL_4           0x1e8 0x584 0x000 0x6 0x0
 639 #define MX50_PAD_EPDC_D14__USBPHY2_VSTATUS_6                    0x1e8 0x584 0x000 0x7 0x0
 640 #define MX50_PAD_EPDC_D15__EPDC_SDDO_15                         0x1ec 0x588 0x000 0x0 0x0
 641 #define MX50_PAD_EPDC_D15__GPIO3_15                             0x1ec 0x588 0x000 0x1 0x0
 642 #define MX50_PAD_EPDC_D15__EIM_WEIM_D_15                        0x1ec 0x588 0x828 0x2 0x1
 643 #define MX50_PAD_EPDC_D15__ELCDIF_DAT_31                        0x1ec 0x588 0x000 0x3 0x0
 644 #define MX50_PAD_EPDC_D15__AUDMUX_AUD6_TXC                      0x1ec 0x588 0x000 0x4 0x0
 645 #define MX50_PAD_EPDC_D15__SDMA_DEBUG_EVENT_CHANNEL_5           0x1ec 0x588 0x000 0x6 0x0
 646 #define MX50_PAD_EPDC_D15__USBPHY2_VSTATUS_7                    0x1ec 0x588 0x000 0x7 0x0
 647 #define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK                         0x1f0 0x58c 0x000 0x0 0x0
 648 #define MX50_PAD_EPDC_GDCLK__GPIO3_16                           0x1f0 0x58c 0x000 0x1 0x0
 649 #define MX50_PAD_EPDC_GDCLK__EIM_WEIM_D_16                      0x1f0 0x58c 0x000 0x2 0x0
 650 #define MX50_PAD_EPDC_GDCLK__ELCDIF_DAT_16                      0x1f0 0x58c 0x000 0x3 0x0
 651 #define MX50_PAD_EPDC_GDCLK__AUDMUX_AUD6_TXFS                   0x1f0 0x58c 0x000 0x4 0x0
 652 #define MX50_PAD_EPDC_GDCLK__SDMA_DEBUG_CORE_STATE_0            0x1f0 0x58c 0x000 0x6 0x0
 653 #define MX50_PAD_EPDC_GDCLK__USBPHY2_BISTOK                     0x1f0 0x58c 0x000 0x7 0x0
 654 #define MX50_PAD_EPDC_GDSP__EPCD_GDSP                           0x1f4 0x590 0x000 0x0 0x0
 655 #define MX50_PAD_EPDC_GDSP__GPIO3_17                            0x1f4 0x590 0x000 0x1 0x0
 656 #define MX50_PAD_EPDC_GDSP__EIM_WEIM_D_17                       0x1f4 0x590 0x000 0x2 0x0
 657 #define MX50_PAD_EPDC_GDSP__ELCDIF_DAT_17                       0x1f4 0x590 0x000 0x3 0x0
 658 #define MX50_PAD_EPDC_GDSP__AUDMUX_AUD6_RXD                     0x1f4 0x590 0x000 0x4 0x0
 659 #define MX50_PAD_EPDC_GDSP__SDMA_DEBUG_CORE_STATE_1             0x1f4 0x590 0x000 0x6 0x0
 660 #define MX50_PAD_EPDC_GDSP__USBPHY2_BVALID                      0x1f4 0x590 0x000 0x7 0x0
 661 #define MX50_PAD_EPDC_GDOE__EPCD_GDOE                           0x1f8 0x594 0x000 0x0 0x0
 662 #define MX50_PAD_EPDC_GDOE__GPIO3_18                            0x1f8 0x594 0x000 0x1 0x0
 663 #define MX50_PAD_EPDC_GDOE__EIM_WEIM_D_18                       0x1f8 0x594 0x000 0x2 0x0
 664 #define MX50_PAD_EPDC_GDOE__ELCDIF_DAT_18                       0x1f8 0x594 0x000 0x3 0x0
 665 #define MX50_PAD_EPDC_GDOE__AUDMUX_AUD6_RXC                     0x1f8 0x594 0x000 0x4 0x0
 666 #define MX50_PAD_EPDC_GDOE__SDMA_DEBUG_CORE_STATE_2             0x1f8 0x594 0x000 0x6 0x0
 667 #define MX50_PAD_EPDC_GDOE__USBPHY2_ENDSESSION                  0x1f8 0x594 0x000 0x7 0x0
 668 #define MX50_PAD_EPDC_GDRL__EPCD_GDRL                           0x1fc 0x598 0x000 0x0 0x0
 669 #define MX50_PAD_EPDC_GDRL__GPIO3_19                            0x1fc 0x598 0x000 0x1 0x0
 670 #define MX50_PAD_EPDC_GDRL__EIM_WEIM_D_19                       0x1f8 0x598 0x000 0x2 0x0
 671 #define MX50_PAD_EPDC_GDRL__ELCDIF_DAT_19                       0x1fc 0x598 0x000 0x3 0x0
 672 #define MX50_PAD_EPDC_GDRL__AUDMUX_AUD6_RXFS                    0x1fc 0x598 0x000 0x4 0x0
 673 #define MX50_PAD_EPDC_GDRL__SDMA_DEBUG_CORE_STATE_3             0x1fc 0x598 0x000 0x6 0x0
 674 #define MX50_PAD_EPDC_GDRL__USBPHY2_IDDIG                       0x1fc 0x598 0x000 0x7 0x0
 675 #define MX50_PAD_EPDC_SDCLK__EPCD_SDCLK                         0x200 0x59c 0x000 0x0 0x0
 676 #define MX50_PAD_EPDC_SDCLK__GPIO3_20                           0x200 0x59c 0x000 0x1 0x0
 677 #define MX50_PAD_EPDC_SDCLK__EIM_WEIM_D_20                      0x200 0x59c 0x000 0x2 0x0
 678 #define MX50_PAD_EPDC_SDCLK__ELCDIF_DAT_20                      0x200 0x59c 0x000 0x3 0x0
 679 #define MX50_PAD_EPDC_SDCLK__AUDMUX_AUD5_TXD                    0x200 0x59c 0x000 0x4 0x0
 680 #define MX50_PAD_EPDC_SDCLK__SDMA_DEBUG_BUS_DEVICE_0            0x200 0x59c 0x000 0x6 0x0
 681 #define MX50_PAD_EPDC_SDCLK__USBPHY2_HOSTDISCONNECT             0x200 0x59c 0x000 0x7 0x0
 682 #define MX50_PAD_EPDC_SDOEZ__EPCD_SDOEZ                         0x204 0x5a0 0x000 0x0 0x0
 683 #define MX50_PAD_EPDC_SDOEZ__GPIO3_21                           0x204 0x5a0 0x000 0x1 0x0
 684 #define MX50_PAD_EPDC_SDOEZ__EIM_WEIM_D_21                      0x204 0x5a0 0x000 0x2 0x0
 685 #define MX50_PAD_EPDC_SDOEZ__ELCDIF_DAT_21                      0x204 0x5a0 0x000 0x3 0x0
 686 #define MX50_PAD_EPDC_SDOEZ__AUDMUX_AUD5_TXC                    0x204 0x5a0 0x000 0x4 0x0
 687 #define MX50_PAD_EPDC_SDOEZ__SDMA_DEBUG_BUS_DEVICE_1            0x204 0x5a0 0x000 0x6 0x0
 688 #define MX50_PAD_EPDC_SDOEZ__USBPHY2_TXREADY                    0x204 0x5a0 0x000 0x7 0x0
 689 #define MX50_PAD_EPDC_SDOED__EPCD_SDOED                         0x208 0x5a4 0x000 0x0 0x0
 690 #define MX50_PAD_EPDC_SDOED__GPIO3_22                           0x208 0x5a4 0x000 0x1 0x0
 691 #define MX50_PAD_EPDC_SDOED__EIM_WEIM_D_22                      0x208 0x5a4 0x000 0x2 0x0
 692 #define MX50_PAD_EPDC_SDOED__ELCDIF_DAT_22                      0x208 0x5a4 0x000 0x3 0x0
 693 #define MX50_PAD_EPDC_SDOED__AUDMUX_AUD5_TXFS                   0x208 0x5a4 0x000 0x4 0x0
 694 #define MX50_PAD_EPDC_SDOED__SDMA_DEBUG_BUS_DEVICE_2            0x208 0x5a4 0x000 0x6 0x0
 695 #define MX50_PAD_EPDC_SDOED__USBPHY2_RXVALID                    0x208 0x5a4 0x000 0x7 0x0
 696 #define MX50_PAD_EPDC_SDOE__EPCD_SDOE                           0x20c 0x5a8 0x000 0x0 0x0
 697 #define MX50_PAD_EPDC_SDOE__GPIO3_23                            0x20c 0x5a8 0x000 0x1 0x0
 698 #define MX50_PAD_EPDC_SDOE__EIM_WEIM_D_23                       0x20c 0x5a8 0x000 0x2 0x0
 699 #define MX50_PAD_EPDC_SDOE__ELCDIF_DAT_23                       0x20c 0x5a8 0x000 0x3 0x0
 700 #define MX50_PAD_EPDC_SDOE__AUDMUX_AUD5_RXD                     0x20c 0x5a8 0x000 0x4 0x0
 701 #define MX50_PAD_EPDC_SDOE__SDMA_DEBUG_BUS_DEVICE_3             0x20c 0x5a8 0x000 0x6 0x0
 702 #define MX50_PAD_EPDC_SDOE__USBPHY2_RXACTIVE                    0x20c 0x5a8 0x000 0x7 0x0
 703 #define MX50_PAD_EPDC_SDLE__EPCD_SDLE                           0x210 0x5ac 0x000 0x0 0x0
 704 #define MX50_PAD_EPDC_SDLE__GPIO3_24                            0x210 0x5ac 0x000 0x1 0x0
 705 #define MX50_PAD_EPDC_SDLE__EIM_WEIM_D_24                       0x210 0x5ac 0x000 0x2 0x0
 706 #define MX50_PAD_EPDC_SDLE__ELCDIF_DAT_8                        0x210 0x5ac 0x71c 0x3 0x1
 707 #define MX50_PAD_EPDC_SDLE__AUDMUX_AUD5_RXC                     0x210 0x5ac 0x000 0x4 0x0
 708 #define MX50_PAD_EPDC_SDLE__SDMA_DEBUG_BUS_DEVICE_4             0x210 0x5ac 0x000 0x6 0x0
 709 #define MX50_PAD_EPDC_SDLE__USBPHY2_RXERROR                     0x210 0x5ac 0x000 0x7 0x0
 710 #define MX50_PAD_EPDC_SDCLKN__EPCD_SDCLKN                       0x214 0x5b0 0x000 0x0 0x0
 711 #define MX50_PAD_EPDC_SDCLKN__GPIO3_25                          0x214 0x5b0 0x000 0x1 0x0
 712 #define MX50_PAD_EPDC_SDCLKN__EIM_WEIM_D_25                     0x214 0x5b0 0x000 0x2 0x0
 713 #define MX50_PAD_EPDC_SDCLKN__ELCDIF_DAT_9                      0x214 0x5b0 0x720 0x3 0x1
 714 #define MX50_PAD_EPDC_SDCLKN__AUDMUX_AUD5_RXFS                  0x214 0x5b0 0x000 0x4 0x0
 715 #define MX50_PAD_EPDC_SDCLKN__SDMA_DEBUG_BUS_ERROR              0x214 0x5b0 0x000 0x6 0x0
 716 #define MX50_PAD_EPDC_SDCLKN__USBPHY2_SIECLOCK                  0x214 0x5b0 0x000 0x7 0x0
 717 #define MX50_PAD_EPDC_SDSHR__EPCD_SDSHR                         0x218 0x5b4 0x000 0x0 0x0
 718 #define MX50_PAD_EPDC_SDSHR__GPIO3_26                           0x218 0x5b4 0x000 0x1 0x0
 719 #define MX50_PAD_EPDC_SDSHR__EIM_WEIM_D_26                      0x218 0x5b4 0x000 0x2 0x0
 720 #define MX50_PAD_EPDC_SDSHR__ELCDIF_DAT_10                      0x218 0x5b4 0x724 0x3 0x1
 721 #define MX50_PAD_EPDC_SDSHR__AUDMUX_AUD4_TXD                    0x218 0x5b4 0x6c8 0x4 0x1
 722 #define MX50_PAD_EPDC_SDSHR__SDMA_DEBUG_BUS_RWB                 0x218 0x5b4 0x000 0x6 0x0
 723 #define MX50_PAD_EPDC_SDSHR__USBPHY2_LINESTATE_0                0x218 0x5b4 0x000 0x7 0x0
 724 #define MX50_PAD_EPDC_PWRCOM__EPCD_PWRCOM                       0x21c 0x5b8 0x000 0x0 0x0
 725 #define MX50_PAD_EPDC_PWRCOM__GPIO3_27                          0x21c 0x5b8 0x000 0x1 0x0
 726 #define MX50_PAD_EPDC_PWRCOM__EIM_WEIM_D_27                     0x21c 0x5b8 0x000 0x2 0x0
 727 #define MX50_PAD_EPDC_PWRCOM__ELCDIF_DAT_11                     0x21c 0x5b8 0x728 0x3 0x1
 728 #define MX50_PAD_EPDC_PWRCOM__AUDMUX_AUD4_TXC                   0x21c 0x5b8 0x6d4 0x4 0x1
 729 #define MX50_PAD_EPDC_PWRCOM__SDMA_DEBUG_CORE_RUN               0x21c 0x5b8 0x000 0x6 0x0
 730 #define MX50_PAD_EPDC_PWRCOM__USBPHY2_LINESTATE_1               0x21c 0x5b8 0x000 0x7 0x0
 731 #define MX50_PAD_EPDC_PWRSTAT__EPCD_PWRSTAT                     0x220 0x5bc 0x000 0x0 0x0
 732 #define MX50_PAD_EPDC_PWRSTAT__GPIO3_28                         0x220 0x5bc 0x000 0x1 0x0
 733 #define MX50_PAD_EPDC_PWRSTAT__EIM_WEIM_D_28                    0x220 0x5bc 0x000 0x2 0x0
 734 #define MX50_PAD_EPDC_PWRSTAT__ELCDIF_DAT_12                    0x220 0x5bc 0x72c 0x3 0x1
 735 #define MX50_PAD_EPDC_PWRSTAT__AUDMUX_AUD4_TXFS                 0x220 0x5bc 0x6d8 0x4 0x1
 736 #define MX50_PAD_EPDC_PWRSTAT__SDMA_DEBUG_MODE                  0x220 0x5bc 0x000 0x6 0x0
 737 #define MX50_PAD_EPDC_PWRSTAT__USBPHY2_VBUSVALID                0x220 0x5bc 0x000 0x7 0x0
 738 #define MX50_PAD_EPDC_PWRCTRL0__EPCD_PWRCTRL0                   0x224 0x5c0 0x000 0x0 0x0
 739 #define MX50_PAD_EPDC_PWRCTRL0__GPIO3_29                        0x224 0x5c0 0x000 0x1 0x0
 740 #define MX50_PAD_EPDC_PWRCTRL0__EIM_WEIM_D_29                   0x224 0x5c0 0x000 0x2 0x0
 741 #define MX50_PAD_EPDC_PWRCTRL0__ELCDIF_DAT_13                   0x224 0x5c0 0x730 0x3 0x1
 742 #define MX50_PAD_EPDC_PWRCTRL0__AUDMUX_AUD4_RXD                 0x224 0x5c0 0x6c4 0x4 0x1
 743 #define MX50_PAD_EPDC_PWRCTRL0__SDMA_DEBUG_RTBUFFER_WRITE       0x224 0x5c0 0x000 0x6 0x0
 744 #define MX50_PAD_EPDC_PWRCTRL0__USBPHY2_AVALID                  0x224 0x5c0 0x000 0x7 0x0
 745 #define MX50_PAD_EPDC_PWRCTRL1__EPCD_PWRCTRL1                   0x228 0x5c4 0x000 0x0 0x0
 746 #define MX50_PAD_EPDC_PWRCTRL1__GPIO3_30                        0x228 0x5c4 0x000 0x1 0x0
 747 #define MX50_PAD_EPDC_PWRCTRL1__EIM_WEIM_D_30                   0x228 0x5c4 0x000 0x2 0x0
 748 #define MX50_PAD_EPDC_PWRCTRL1__ELCDIF_DAT_14                   0x228 0x5c4 0x734 0x3 0x1
 749 #define MX50_PAD_EPDC_PWRCTRL1__AUDMUX_AUD4_RXC                 0x228 0x5c4 0x6cc 0x4 0x1
 750 #define MX50_PAD_EPDC_PWRCTRL1__SDMA_DEBUG_YIELD                0x228 0x5c4 0x000 0x6 0x0
 751 #define MX50_PAD_EPDC_PWRCTRL1__USBPHY1_ONBIST                  0x228 0x5c4 0x000 0x7 0x0
 752 #define MX50_PAD_EPDC_PWRCTRL2__EPCD_PWRCTRL2                   0x22c 0x5c8 0x000 0x0 0x0
 753 #define MX50_PAD_EPDC_PWRCTRL2__GPIO3_31                        0x22c 0x5c8 0x000 0x1 0x0
 754 #define MX50_PAD_EPDC_PWRCTRL2__EIM_WEIM_D_31                   0x22c 0x5c8 0x000 0x2 0x0
 755 #define MX50_PAD_EPDC_PWRCTRL2__ELCDIF_DAT_15                   0x22c 0x5c8 0x738 0x3 0x1
 756 #define MX50_PAD_EPDC_PWRCTRL2__AUDMUX_AUD4_RXFS                0x22c 0x5c8 0x6d0 0x4 0x1
 757 #define MX50_PAD_EPDC_PWRCTRL2__SDMA_EXT_EVENT_0                0x22c 0x5c8 0x7b8 0x6 0x1
 758 #define MX50_PAD_EPDC_PWRCTRL2__USBPHY2_ONBIST                  0x22c 0x5c8 0x000 0x7 0x0
 759 #define MX50_PAD_EPDC_PWRCTRL3__EPCD_PWRCTRL3                   0x230 0x5cc 0x000 0x0 0x0
 760 #define MX50_PAD_EPDC_PWRCTRL3__GPIO4_20                        0x230 0x5cc 0x000 0x1 0x0
 761 #define MX50_PAD_EPDC_PWRCTRL3__EIM_WEIM_EB_2                   0x230 0x5cc 0x000 0x2 0x0
 762 #define MX50_PAD_EPDC_PWRCTRL3__SDMA_EXT_EVENT_1                0x230 0x5cc 0x7bc 0x6 0x1
 763 #define MX50_PAD_EPDC_PWRCTRL3__USBPHY1_BISTOK                  0x230 0x5cc 0x000 0x7 0x0
 764 #define MX50_PAD_EPDC_VCOM0__EPCD_VCOM_0                        0x234 0x5d0 0x000 0x0 0x0
 765 #define MX50_PAD_EPDC_VCOM0__GPIO4_21                           0x234 0x5d0 0x000 0x1 0x0
 766 #define MX50_PAD_EPDC_VCOM0__EIM_WEIM_EB_3                      0x234 0x5d0 0x000 0x2 0x0
 767 #define MX50_PAD_EPDC_VCOM0__USBPHY2_BISTOK                     0x234 0x5d0 0x000 0x7 0x0
 768 #define MX50_PAD_EPDC_VCOM1__EPCD_VCOM_1                        0x238 0x5d4 0x000 0x0 0x0
 769 #define MX50_PAD_EPDC_VCOM1__GPIO4_22                           0x238 0x5d4 0x000 0x1 0x0
 770 #define MX50_PAD_EPDC_VCOM1__EIM_WEIM_CS_3                      0x238 0x5d4 0x000 0x2 0x0
 771 #define MX50_PAD_EPDC_BDR0__EPCD_BDR_0                          0x23c 0x5d8 0x000 0x0 0x0
 772 #define MX50_PAD_EPDC_BDR0__GPIO4_23                            0x23c 0x5d8 0x000 0x1 0x0
 773 #define MX50_PAD_EPDC_BDR0__ELCDIF_DAT_7                        0x23c 0x5d8 0x718 0x3 0x1
 774 #define MX50_PAD_EPDC_BDR1__EPCD_BDR_1                          0x240 0x5dc 0x000 0x0 0x0
 775 #define MX50_PAD_EPDC_BDR1__GPIO4_24                            0x240 0x5dc 0x000 0x1 0x0
 776 #define MX50_PAD_EPDC_BDR1__ELCDIF_DAT_6                        0x240 0x5dc 0x714 0x3 0x1
 777 #define MX50_PAD_EPDC_SDCE0__EPCD_SDCE_0                        0x244 0x5e0 0x000 0x0 0x0
 778 #define MX50_PAD_EPDC_SDCE0__GPIO4_25                           0x244 0x5e0 0x000 0x1 0x0
 779 #define MX50_PAD_EPDC_SDCE0__ELCDIF_DAT_5                       0x244 0x5e0 0x710 0x3 0x1
 780 #define MX50_PAD_EPDC_SDCE1__EPCD_SDCE_1                        0x248 0x5e4 0x000 0x0 0x0
 781 #define MX50_PAD_EPDC_SDCE1__GPIO4_26                           0x248 0x5e4 0x000 0x1 0x0
 782 #define MX50_PAD_EPDC_SDCE1__ELCDIF_DAT_4                       0x248 0x5e4 0x70c 0x3 0x0
 783 #define MX50_PAD_EPDC_SDCE2__EPCD_SDCE_2                        0x24c 0x5e8 0x000 0x0 0x0
 784 #define MX50_PAD_EPDC_SDCE2__GPIO4_27                           0x24c 0x5e8 0x000 0x1 0x0
 785 #define MX50_PAD_EPDC_SDCE2__ELCDIF_DAT_3                       0x24c 0x5e8 0x708 0x3 0x1
 786 #define MX50_PAD_EPDC_SDCE3__EPCD_SDCE_3                        0x250 0x5ec 0x000 0x0 0x0
 787 #define MX50_PAD_EPDC_SDCE3__GPIO4_28                           0x250 0x5ec 0x000 0x1 0x0
 788 #define MX50_PAD_EPDC_SDCE3__ELCDIF_DAT_2                       0x250 0x5ec 0x704 0x3 0x1
 789 #define MX50_PAD_EPDC_SDCE4__EPCD_SDCE_4                        0x254 0x5f0 0x000 0x0 0x0
 790 #define MX50_PAD_EPDC_SDCE4__GPIO4_29                           0x254 0x5f0 0x000 0x1 0x0
 791 #define MX50_PAD_EPDC_SDCE4__ELCDIF_DAT_1                       0x254 0x5f0 0x700 0x3 0x1
 792 #define MX50_PAD_EPDC_SDCE5__EPCD_SDCE_5                        0x258 0x5f4 0x000 0x0 0x0
 793 #define MX50_PAD_EPDC_SDCE5__GPIO4_30                           0x258 0x5f4 0x000 0x1 0x0
 794 #define MX50_PAD_EPDC_SDCE5__ELCDIF_DAT_0                       0x258 0x5f4 0x6fc 0x3 0x1
 795 #define MX50_PAD_EIM_DA0__EIM_WEIM_A_0                          0x25c 0x5f8 0x000 0x0 0x0
 796 #define MX50_PAD_EIM_DA0__GPIO1_0                               0x25c 0x5f8 0x000 0x1 0x0
 797 #define MX50_PAD_EIM_DA0__KPP_COL_4                             0x25c 0x5f8 0x790 0x3 0x2
 798 #define MX50_PAD_EIM_DA0__TPIU_TRACE_0                          0x25c 0x5f8 0x000 0x6 0x0
 799 #define MX50_PAD_EIM_DA0__SRC_BT_CFG1_0                         0x25c 0x5f8 0x000 0x7 0x0
 800 #define MX50_PAD_EIM_DA1__EIM_WEIM_A_1                          0x260 0x5fc 0x000 0x0 0x0
 801 #define MX50_PAD_EIM_DA1__GPIO1_1                               0x260 0x5fc 0x000 0x1 0x0
 802 #define MX50_PAD_EIM_DA1__KPP_ROW_4                             0x260 0x5fc 0x7a0 0x3 0x2
 803 #define MX50_PAD_EIM_DA1__TPIU_TRACE_1                          0x260 0x5fc 0x000 0x6 0x0
 804 #define MX50_PAD_EIM_DA1__SRC_BT_CFG1_1                         0x260 0x5fc 0x000 0x7 0x0
 805 #define MX50_PAD_EIM_DA2__EIM_WEIM_A_2                          0x264 0x600 0x000 0x0 0x0
 806 #define MX50_PAD_EIM_DA2__GPIO1_2                               0x264 0x600 0x000 0x1 0x0
 807 #define MX50_PAD_EIM_DA2__KPP_COL_5                             0x264 0x600 0x794 0x3 0x2
 808 #define MX50_PAD_EIM_DA2__TPIU_TRACE_2                          0x264 0x600 0x000 0x6 0x0
 809 #define MX50_PAD_EIM_DA2__SRC_BT_CFG1_2                         0x264 0x600 0x000 0x7 0x0
 810 #define MX50_PAD_EIM_DA3__EIM_WEIM_A_3                          0x268 0x604 0x000 0x0 0x0
 811 #define MX50_PAD_EIM_DA3__GPIO1_3                               0x268 0x604 0x000 0x1 0x0
 812 #define MX50_PAD_EIM_DA3__KPP_ROW_5                             0x268 0x604 0x7a4 0x3 0x2
 813 #define MX50_PAD_EIM_DA3__TPIU_TRACE_3                          0x268 0x604 0x000 0x6 0x0
 814 #define MX50_PAD_EIM_DA3__SRC_BT_CFG1_3                         0x268 0x604 0x000 0x7 0x0
 815 #define MX50_PAD_EIM_DA4__EIM_WEIM_A_4                          0x26c 0x608 0x000 0x0 0x0
 816 #define MX50_PAD_EIM_DA4__GPIO1_4                               0x26c 0x608 0x000 0x1 0x0
 817 #define MX50_PAD_EIM_DA4__KPP_COL_6                             0x26c 0x608 0x798 0x3 0x2
 818 #define MX50_PAD_EIM_DA4__TPIU_TRACE_4                          0x26c 0x608 0x000 0x6 0x0
 819 #define MX50_PAD_EIM_DA4__SRC_BT_CFG1_4                         0x26c 0x608 0x000 0x7 0x0
 820 #define MX50_PAD_EIM_DA5__EIM_WEIM_A_5                          0x270 0x60c 0x000 0x0 0x0
 821 #define MX50_PAD_EIM_DA5__GPIO1_5                               0x270 0x60c 0x000 0x1 0x0
 822 #define MX50_PAD_EIM_DA5__KPP_ROW_6                             0x270 0x60c 0x7a8 0x3 0x2
 823 #define MX50_PAD_EIM_DA5__TPIU_TRACE_5                          0x270 0x60c 0x000 0x6 0x0
 824 #define MX50_PAD_EIM_DA5__SRC_BT_CFG1_5                         0x270 0x60c 0x000 0x7 0x0
 825 #define MX50_PAD_EIM_DA6__EIM_WEIM_A_6                          0x274 0x610 0x000 0x0 0x0
 826 #define MX50_PAD_EIM_DA6__GPIO1_6                               0x274 0x610 0x000 0x1 0x0
 827 #define MX50_PAD_EIM_DA6__KPP_COL_7                             0x274 0x610 0x79c 0x3 0x2
 828 #define MX50_PAD_EIM_DA6__TPIU_TRACE_6                          0x274 0x610 0x000 0x6 0x0
 829 #define MX50_PAD_EIM_DA6__SRC_BT_CFG1_6                         0x274 0x610 0x000 0x7 0x0
 830 #define MX50_PAD_EIM_DA7__EIM_WEIM_A_7                          0x278 0x614 0x000 0x0 0x0
 831 #define MX50_PAD_EIM_DA7__GPIO1_7                               0x278 0x614 0x000 0x1 0x0
 832 #define MX50_PAD_EIM_DA7__KPP_ROW_7                             0x278 0x614 0x7ac 0x3 0x2
 833 #define MX50_PAD_EIM_DA7__TPIU_TRACE_7                          0x278 0x614 0x000 0x6 0x0
 834 #define MX50_PAD_EIM_DA7__SRC_BT_CFG1_7                         0x278 0x614 0x000 0x7 0x0
 835 #define MX50_PAD_EIM_DA8__EIM_WEIM_A_8                          0x27c 0x618 0x000 0x0 0x0
 836 #define MX50_PAD_EIM_DA8__GPIO1_8                               0x27c 0x618 0x000 0x1 0x0
 837 #define MX50_PAD_EIM_DA8__EIM_NANDF_CLE                         0x27c 0x618 0x000 0x2 0x0
 838 #define MX50_PAD_EIM_DA8__TPIU_TRACE_8                          0x27c 0x618 0x000 0x6 0x0
 839 #define MX50_PAD_EIM_DA8__SRC_BT_CFG2_0                         0x27c 0x618 0x000 0x7 0x0
 840 #define MX50_PAD_EIM_DA9__EIM_WEIM_A_9                          0x280 0x61c 0x000 0x0 0x0
 841 #define MX50_PAD_EIM_DA9__GPIO1_9                               0x280 0x61c 0x000 0x1 0x0
 842 #define MX50_PAD_EIM_DA9__EIM_NANDF_ALE                         0x280 0x61c 0x000 0x2 0x0
 843 #define MX50_PAD_EIM_DA9__TPIU_TRACE_9                          0x280 0x61c 0x000 0x6 0x0
 844 #define MX50_PAD_EIM_DA9__SRC_BT_CFG2_1                         0x280 0x61c 0x000 0x7 0x0
 845 #define MX50_PAD_EIM_DA10__EIM_WEIM_A_10                        0x284 0x620 0x000 0x0 0x0
 846 #define MX50_PAD_EIM_DA10__GPIO1_10                             0x284 0x620 0x000 0x1 0x0
 847 #define MX50_PAD_EIM_DA10__EIM_NANDF_CEN_0                      0x284 0x620 0x000 0x2 0x0
 848 #define MX50_PAD_EIM_DA10__TPIU_TRACE_10                        0x284 0x620 0x000 0x6 0x0
 849 #define MX50_PAD_EIM_DA10__SRC_BT_CFG2_2                        0x284 0x620 0x000 0x7 0x0
 850 #define MX50_PAD_EIM_DA11__EIM_WEIM_A_11                        0x288 0x624 0x000 0x0 0x0
 851 #define MX50_PAD_EIM_DA11__GPIO1_11                             0x288 0x624 0x000 0x1 0x0
 852 #define MX50_PAD_EIM_DA11__EIM_NANDF_CEN_1                      0x288 0x624 0x000 0x2 0x0
 853 #define MX50_PAD_EIM_DA11__TPIU_TRACE_11                        0x288 0x624 0x000 0x6 0x0
 854 #define MX50_PAD_EIM_DA11__SRC_BT_CFG2_3                        0x288 0x624 0x000 0x7 0x0
 855 #define MX50_PAD_EIM_DA12__EIM_WEIM_A_12                        0x28c 0x628 0x000 0x0 0x0
 856 #define MX50_PAD_EIM_DA12__GPIO1_12                             0x28c 0x628 0x000 0x1 0x0
 857 #define MX50_PAD_EIM_DA12__EIM_NANDF_CEN_2                      0x28c 0x628 0x000 0x2 0x0
 858 #define MX50_PAD_EIM_DA12__EPDC_SDCE_6                          0x28c 0x628 0x000 0x3 0x0
 859 #define MX50_PAD_EIM_DA12__TPIU_TRACE_12                        0x28c 0x628 0x000 0x6 0x0
 860 #define MX50_PAD_EIM_DA12__SRC_BT_CFG2_4                        0x28c 0x628 0x000 0x7 0x0
 861 #define MX50_PAD_EIM_DA13__EIM_WEIM_A_13                        0x290 0x62c 0x000 0x0 0x0
 862 #define MX50_PAD_EIM_DA13__GPIO1_13                             0x290 0x62c 0x000 0x1 0x0
 863 #define MX50_PAD_EIM_DA13__EIM_NANDF_CEN_3                      0x290 0x62c 0x000 0x2 0x0
 864 #define MX50_PAD_EIM_DA13__EPDC_SDCE_7                          0x290 0x62c 0x000 0x3 0x0
 865 #define MX50_PAD_EIM_DA13__TPIU_TRACE_13                        0x290 0x62c 0x000 0x6 0x0
 866 #define MX50_PAD_EIM_DA13__SRC_BT_CFG2_5                        0x290 0x62c 0x000 0x7 0x0
 867 #define MX50_PAD_EIM_DA14__EIM_WEIM_A_14                        0x294 0x630 0x000 0x0 0x0
 868 #define MX50_PAD_EIM_DA14__GPIO1_14                             0x294 0x630 0x000 0x1 0x0
 869 #define MX50_PAD_EIM_DA14__EIM_NANDF_READY0                     0x294 0x630 0x7b4 0x2 0x2
 870 #define MX50_PAD_EIM_DA14__EPDC_SDCE_8                          0x294 0x630 0x000 0x3 0x0
 871 #define MX50_PAD_EIM_DA14__TPIU_TRACE_14                        0x294 0x630 0x000 0x6 0x0
 872 #define MX50_PAD_EIM_DA14__SRC_BT_CFG2_6                        0x294 0x630 0x000 0x7 0x0
 873 #define MX50_PAD_EIM_DA15__EIM_WEIM_A_15                        0x298 0x634 0x000 0x0 0x0
 874 #define MX50_PAD_EIM_DA15__GPIO1_15                             0x298 0x634 0x000 0x1 0x0
 875 #define MX50_PAD_EIM_DA15__EIM_NANDF_DQS                        0x298 0x634 0x7b0 0x2 0x2
 876 #define MX50_PAD_EIM_DA15__EPDC_SDCE_9                          0x298 0x634 0x000 0x3 0x0
 877 #define MX50_PAD_EIM_DA15__TPIU_TRACE_15                        0x298 0x634 0x000 0x6 0x0
 878 #define MX50_PAD_EIM_DA15__SRC_BT_CFG2_7                        0x298 0x634 0x000 0x7 0x0
 879 #define MX50_PAD_EIM_CS2__EIM_WEIM_CS_2                         0x29c 0x638 0x000 0x0 0x0
 880 #define MX50_PAD_EIM_CS2__GPIO1_16                              0x29c 0x638 0x000 0x1 0x0
 881 #define MX50_PAD_EIM_CS2__EIM_WEIM_A_27                         0x29c 0x638 0x000 0x2 0x0
 882 #define MX50_PAD_EIM_CS2__TPIU_TRCLK                            0x29c 0x638 0x000 0x6 0x0
 883 #define MX50_PAD_EIM_CS2__SRC_BT_CFG3_0                         0x29c 0x638 0x000 0x7 0x0
 884 #define MX50_PAD_EIM_CS1__EIM_WEIM_CS_1                         0x2a0 0x63c 0x000 0x0 0x0
 885 #define MX50_PAD_EIM_CS1__GPIO1_17                              0x2a0 0x63c 0x000 0x1 0x0
 886 #define MX50_PAD_EIM_CS1__TPIU_TRCTL                            0x2a0 0x63c 0x000 0x6 0x0
 887 #define MX50_PAD_EIM_CS1__SRC_BT_CFG3_1                         0x2a0 0x63c 0x000 0x7 0x0
 888 #define MX50_PAD_EIM_CS0__EIM_WEIM_CS_0                         0x2a4 0x640 0x000 0x0 0x0
 889 #define MX50_PAD_EIM_CS0__GPIO1_18                              0x2a4 0x640 0x000 0x1 0x0
 890 #define MX50_PAD_EIM_CS0__SRC_BT_CFG3_2                         0x2a4 0x640 0x000 0x7 0x0
 891 #define MX50_PAD_EIM_EB0__EIM_WEIM_EB_0                         0x2a8 0x644 0x000 0x0 0x0
 892 #define MX50_PAD_EIM_EB0__GPIO1_19                              0x2a8 0x644 0x000 0x1 0x0
 893 #define MX50_PAD_EIM_EB0__SRC_BT_CFG3_3                         0x2a8 0x644 0x000 0x7 0x0
 894 #define MX50_PAD_EIM_EB1__EIM_WEIM_EB_1                         0x2ac 0x648 0x000 0x0 0x0
 895 #define MX50_PAD_EIM_EB1__GPIO1_20                              0x2ac 0x648 0x000 0x1 0x0
 896 #define MX50_PAD_EIM_EB1__SRC_BT_CFG3_4                         0x2ac 0x648 0x000 0x7 0x0
 897 #define MX50_PAD_EIM_WAIT__EIM_WEIM_WAIT                        0x2b0 0x64c 0x000 0x0 0x0
 898 #define MX50_PAD_EIM_WAIT__GPIO1_21                             0x2b0 0x64c 0x000 0x1 0x0
 899 #define MX50_PAD_EIM_WAIT__EIM_WEIM_DTACK_B                     0x2b0 0x64c 0x000 0x2 0x0
 900 #define MX50_PAD_EIM_WAIT__SRC_BT_CFG3_5                        0x2b0 0x64c 0x000 0x7 0x0
 901 #define MX50_PAD_EIM_BCLK__EIM_WEIM_BCLK                        0x2b4 0x650 0x000 0x0 0x0
 902 #define MX50_PAD_EIM_BCLK__GPIO1_22                             0x2b4 0x650 0x000 0x1 0x0
 903 #define MX50_PAD_EIM_BCLK__SRC_BT_CFG3_6                        0x2b4 0x650 0x000 0x7 0x0
 904 #define MX50_PAD_EIM_RDY__EIM_WEIM_RDY                          0x2b8 0x654 0x000 0x0 0x0
 905 #define MX50_PAD_EIM_RDY__GPIO1_23                              0x2b8 0x654 0x000 0x1 0x0
 906 #define MX50_PAD_EIM_RDY__SRC_BT_CFG3_7                         0x2b8 0x654 0x000 0x7 0x0
 907 #define MX50_PAD_EIM_OE__EIM_WEIM_OE                            0x2bc 0x658 0x000 0x0 0x0
 908 #define MX50_PAD_EIM_OE__GPIO1_24                               0x2bc 0x658 0x000 0x1 0x0
 909 #define MX50_PAD_EIM_OE__INT_BOOT                               0x2bc 0x658 0x000 0x7 0x0
 910 #define MX50_PAD_EIM_RW__EIM_WEIM_RW                            0x2c0 0x65c 0x000 0x0 0x0
 911 #define MX50_PAD_EIM_RW__GPIO1_25                               0x2c0 0x65c 0x000 0x1 0x0
 912 #define MX50_PAD_EIM_RW__SYSTEM_RST                             0x2c0 0x65c 0x000 0x7 0x0
 913 #define MX50_PAD_EIM_LBA__EIM_WEIM_LBA                          0x2c4 0x660 0x000 0x0 0x0
 914 #define MX50_PAD_EIM_LBA__GPIO1_26                              0x2c4 0x660 0x000 0x1 0x0
 915 #define MX50_PAD_EIM_LBA__TESTER_ACK                            0x2c4 0x660 0x000 0x7 0x0
 916 #define MX50_PAD_EIM_CRE__EIM_WEIM_CRE                          0x2c8 0x664 0x000 0x0 0x0
 917 #define MX50_PAD_EIM_CRE__GPIO1_27                              0x2c8 0x664 0x000 0x1 0x0
 918 
 919 #endif /* __DTS_IMX50_PINFUNC_H */