root/arch/arc/include/asm/cache.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   4  */
   5 
   6 #ifndef __ARC_ASM_CACHE_H
   7 #define __ARC_ASM_CACHE_H
   8 
   9 /* In case $$ not config, setup a dummy number for rest of kernel */
  10 #ifndef CONFIG_ARC_CACHE_LINE_SHIFT
  11 #define L1_CACHE_SHIFT          6
  12 #else
  13 #define L1_CACHE_SHIFT          CONFIG_ARC_CACHE_LINE_SHIFT
  14 #endif
  15 
  16 #define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
  17 #define CACHE_LINE_MASK         (~(L1_CACHE_BYTES - 1))
  18 
  19 /*
  20  * ARC700 doesn't cache any access in top 1G (0xc000_0000 to 0xFFFF_FFFF)
  21  * Ideal for wiring memory mapped peripherals as we don't need to do
  22  * explicit uncached accesses (LD.di/ST.di) hence more portable drivers
  23  */
  24 #define ARC_UNCACHED_ADDR_SPACE 0xc0000000
  25 
  26 #ifndef __ASSEMBLY__
  27 
  28 /* Uncached access macros */
  29 #define arc_read_uncached_32(ptr)       \
  30 ({                                      \
  31         unsigned int __ret;             \
  32         __asm__ __volatile__(           \
  33         "       ld.di %0, [%1]  \n"     \
  34         : "=r"(__ret)                   \
  35         : "r"(ptr));                    \
  36         __ret;                          \
  37 })
  38 
  39 #define arc_write_uncached_32(ptr, data)\
  40 ({                                      \
  41         __asm__ __volatile__(           \
  42         "       st.di %0, [%1]  \n"     \
  43         :                               \
  44         : "r"(data), "r"(ptr));         \
  45 })
  46 
  47 /* Largest line length for either L1 or L2 is 128 bytes */
  48 #define SMP_CACHE_BYTES         128
  49 #define cache_line_size()       SMP_CACHE_BYTES
  50 #define ARCH_DMA_MINALIGN       SMP_CACHE_BYTES
  51 
  52 /*
  53  * Make sure slab-allocated buffers are 64-bit aligned when atomic64_t uses
  54  * ARCv2 64-bit atomics (LLOCKD/SCONDD). This guarantess runtime 64-bit
  55  * alignment for any atomic64_t embedded in buffer.
  56  * Default ARCH_SLAB_MINALIGN is __alignof__(long long) which has a relaxed
  57  * value of 4 (and not 8) in ARC ABI.
  58  */
  59 #if defined(CONFIG_ARC_HAS_LL64) && defined(CONFIG_ARC_HAS_LLSC)
  60 #define ARCH_SLAB_MINALIGN      8
  61 #endif
  62 
  63 extern void arc_cache_init(void);
  64 extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
  65 extern void read_decode_cache_bcr(void);
  66 
  67 extern int ioc_enable;
  68 extern unsigned long perip_base, perip_end;
  69 
  70 #endif  /* !__ASSEMBLY__ */
  71 
  72 /* Instruction cache related Auxiliary registers */
  73 #define ARC_REG_IC_BCR          0x77    /* Build Config reg */
  74 #define ARC_REG_IC_IVIC         0x10
  75 #define ARC_REG_IC_CTRL         0x11
  76 #define ARC_REG_IC_IVIR         0x16
  77 #define ARC_REG_IC_ENDR         0x17
  78 #define ARC_REG_IC_IVIL         0x19
  79 #define ARC_REG_IC_PTAG         0x1E
  80 #define ARC_REG_IC_PTAG_HI      0x1F
  81 
  82 /* Bit val in IC_CTRL */
  83 #define IC_CTRL_DIS             0x1
  84 
  85 /* Data cache related Auxiliary registers */
  86 #define ARC_REG_DC_BCR          0x72    /* Build Config reg */
  87 #define ARC_REG_DC_IVDC         0x47
  88 #define ARC_REG_DC_CTRL         0x48
  89 #define ARC_REG_DC_IVDL         0x4A
  90 #define ARC_REG_DC_FLSH         0x4B
  91 #define ARC_REG_DC_FLDL         0x4C
  92 #define ARC_REG_DC_STARTR       0x4D
  93 #define ARC_REG_DC_ENDR         0x4E
  94 #define ARC_REG_DC_PTAG         0x5C
  95 #define ARC_REG_DC_PTAG_HI      0x5F
  96 
  97 /* Bit val in DC_CTRL */
  98 #define DC_CTRL_DIS             0x001
  99 #define DC_CTRL_INV_MODE_FLUSH  0x040
 100 #define DC_CTRL_FLUSH_STATUS    0x100
 101 #define DC_CTRL_RGN_OP_INV      0x200
 102 #define DC_CTRL_RGN_OP_MSK      0x200
 103 
 104 /*System-level cache (L2 cache) related Auxiliary registers */
 105 #define ARC_REG_SLC_CFG         0x901
 106 #define ARC_REG_SLC_CTRL        0x903
 107 #define ARC_REG_SLC_FLUSH       0x904
 108 #define ARC_REG_SLC_INVALIDATE  0x905
 109 #define ARC_AUX_SLC_IVDL        0x910
 110 #define ARC_AUX_SLC_FLDL        0x912
 111 #define ARC_REG_SLC_RGN_START   0x914
 112 #define ARC_REG_SLC_RGN_START1  0x915
 113 #define ARC_REG_SLC_RGN_END     0x916
 114 #define ARC_REG_SLC_RGN_END1    0x917
 115 
 116 /* Bit val in SLC_CONTROL */
 117 #define SLC_CTRL_DIS            0x001
 118 #define SLC_CTRL_IM             0x040
 119 #define SLC_CTRL_BUSY           0x100
 120 #define SLC_CTRL_RGN_OP_INV     0x200
 121 
 122 /* IO coherency related Auxiliary registers */
 123 #define ARC_REG_IO_COH_ENABLE   0x500
 124 #define ARC_IO_COH_ENABLE_BIT   BIT(0)
 125 #define ARC_REG_IO_COH_PARTIAL  0x501
 126 #define ARC_IO_COH_PARTIAL_BIT  BIT(0)
 127 #define ARC_REG_IO_COH_AP0_BASE 0x508
 128 #define ARC_REG_IO_COH_AP0_SIZE 0x509
 129 
 130 #endif /* _ASM_CACHE_H */