root/arch/arm/mach-rpc/irq.c

DEFINITIONS

1. iomd_get_base
2. iomd_set_base_mask
3. iomd_irq_mask_ack
4. iomd_irq_mask
5. iomd_irq_unmask
6. rpc_init_irq

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <linux/init.h>
   3 #include <linux/list.h>
   4 #include <linux/io.h>
   5 
   6 #include <asm/mach/irq.h>
   7 #include <asm/hardware/iomd.h>
   8 #include <asm/irq.h>
   9 #include <asm/fiq.h>
  10 
  11 // These are offsets from the stat register for each IRQ bank
  12 #define STAT    0x00
  13 #define REQ     0x04
  14 #define CLR     0x04
  15 #define MASK    0x08
  16 
  17 static void __iomem *iomd_get_base(struct irq_data *d)
  18 {
  19         void *cd = irq_data_get_irq_chip_data(d);
  20 
  21         return (void __iomem *)(unsigned long)cd;
  22 }
  23 
  24 static void iomd_set_base_mask(unsigned int irq, void __iomem *base, u32 mask)
  25 {
  26         struct irq_data *d = irq_get_irq_data(irq);
  27 
  28         d->mask = mask;
  29         irq_set_chip_data(irq, (void *)(unsigned long)base);
  30 }
  31 
  32 static void iomd_irq_mask_ack(struct irq_data *d)
  33 {
  34         void __iomem *base = iomd_get_base(d);
  35         unsigned int val, mask = d->mask;
  36 
  37         val = readb(base + MASK);
  38         writeb(val & ~mask, base + MASK);
  39         writeb(mask, base + CLR);
  40 }
  41 
  42 static void iomd_irq_mask(struct irq_data *d)
  43 {
  44         void __iomem *base = iomd_get_base(d);
  45         unsigned int val, mask = d->mask;
  46 
  47         val = readb(base + MASK);
  48         writeb(val & ~mask, base + MASK);
  49 }
  50 
  51 static void iomd_irq_unmask(struct irq_data *d)
  52 {
  53         void __iomem *base = iomd_get_base(d);
  54         unsigned int val, mask = d->mask;
  55 
  56         val = readb(base + MASK);
  57         writeb(val | mask, base + MASK);
  58 }
  59 
  60 static struct irq_chip iomd_chip_clr = {
  61         .irq_mask_ack   = iomd_irq_mask_ack,
  62         .irq_mask       = iomd_irq_mask,
  63         .irq_unmask     = iomd_irq_unmask,
  64 };
  65 
  66 static struct irq_chip iomd_chip_noclr = {
  67         .irq_mask       = iomd_irq_mask,
  68         .irq_unmask     = iomd_irq_unmask,
  69 };
  70 
  71 extern unsigned char rpc_default_fiq_start, rpc_default_fiq_end;
  72 
  73 void __init rpc_init_irq(void)
  74 {
  75         unsigned int irq, clr, set;
  76 
  77         iomd_writeb(0, IOMD_IRQMASKA);
  78         iomd_writeb(0, IOMD_IRQMASKB);
  79         iomd_writeb(0, IOMD_FIQMASK);
  80         iomd_writeb(0, IOMD_DMAMASK);
  81 
  82         set_fiq_handler(&rpc_default_fiq_start,
  83                 &rpc_default_fiq_end - &rpc_default_fiq_start);
  84 
  85         for (irq = 0; irq < NR_IRQS; irq++) {
  86                 clr = IRQ_NOREQUEST;
  87                 set = 0;
  88 
  89                 if (irq <= 6 || (irq >= 9 && irq <= 15))
  90                         clr |= IRQ_NOPROBE;
  91 
  92                 if (irq == 21 || (irq >= 16 && irq <= 19) ||
  93                     irq == IRQ_KEYBOARDTX)
  94                         set |= IRQ_NOAUTOEN;
  95 
  96                 switch (irq) {
  97                 case 0 ... 7:
  98                         irq_set_chip_and_handler(irq, &iomd_chip_clr,
  99                                                  handle_level_irq);
 100                         irq_modify_status(irq, clr, set);
 101                         iomd_set_base_mask(irq, IOMD_BASE + IOMD_IRQSTATA,
 102                                            BIT(irq));
 103                         break;
 104 
 105                 case 8 ... 15:
 106                         irq_set_chip_and_handler(irq, &iomd_chip_noclr,
 107                                                  handle_level_irq);
 108                         irq_modify_status(irq, clr, set);
 109                         iomd_set_base_mask(irq, IOMD_BASE + IOMD_IRQSTATB,
 110                                            BIT(irq - 8));
 111                         break;
 112 
 113                 case 16 ... 21:
 114                         irq_set_chip_and_handler(irq, &iomd_chip_noclr,
 115                                                  handle_level_irq);
 116                         irq_modify_status(irq, clr, set);
 117                         iomd_set_base_mask(irq, IOMD_BASE + IOMD_DMASTAT,
 118                                            BIT(irq - 16));
 119                         break;
 120 
 121                 case 64 ... 71:
 122                         irq_set_chip(irq, &iomd_chip_noclr);
 123                         irq_modify_status(irq, clr, set);
 124                         iomd_set_base_mask(irq, IOMD_BASE + IOMD_FIQSTAT,
 125                                            BIT(irq - 64));
 126                         break;
 127                 }
 128         }
 129 
 130         init_FIQ(FIQ_START);
 131 }