arch/arm/kvm/emulate.c

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This source file includes following definitions.
vcpu_reg
__vcpu_spsr
kvm_inject_vabt
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
   4  * Author: Christoffer Dall <c.dall@virtualopensystems.com>
   5  */
   6 
   7 #include <linux/mm.h>
   8 #include <linux/kvm_host.h>
   9 #include <asm/kvm_arm.h>
  10 #include <asm/kvm_emulate.h>
  11 #include <asm/opcodes.h>
  12 #include <trace/events/kvm.h>
  13 
  14 #include "trace.h"
  15 
  16 #define VCPU_NR_MODES           6
  17 #define VCPU_REG_OFFSET_USR     0
  18 #define VCPU_REG_OFFSET_FIQ     1
  19 #define VCPU_REG_OFFSET_IRQ     2
  20 #define VCPU_REG_OFFSET_SVC     3
  21 #define VCPU_REG_OFFSET_ABT     4
  22 #define VCPU_REG_OFFSET_UND     5
  23 #define REG_OFFSET(_reg) \
  24         (offsetof(struct kvm_regs, _reg) / sizeof(u32))
  25 
  26 #define USR_REG_OFFSET(_num) REG_OFFSET(usr_regs.uregs[_num])
  27 
  28 static const unsigned long vcpu_reg_offsets[VCPU_NR_MODES][15] = {
  29         /* USR/SYS Registers */
  30         [VCPU_REG_OFFSET_USR] = {
  31                 USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
  32                 USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
  33                 USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
  34                 USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
  35                 USR_REG_OFFSET(12), USR_REG_OFFSET(13), USR_REG_OFFSET(14),
  36         },
  37 
  38         /* FIQ Registers */
  39         [VCPU_REG_OFFSET_FIQ] = {
  40                 USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
  41                 USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
  42                 USR_REG_OFFSET(6), USR_REG_OFFSET(7),
  43                 REG_OFFSET(fiq_regs[0]), /* r8 */
  44                 REG_OFFSET(fiq_regs[1]), /* r9 */
  45                 REG_OFFSET(fiq_regs[2]), /* r10 */
  46                 REG_OFFSET(fiq_regs[3]), /* r11 */
  47                 REG_OFFSET(fiq_regs[4]), /* r12 */
  48                 REG_OFFSET(fiq_regs[5]), /* r13 */
  49                 REG_OFFSET(fiq_regs[6]), /* r14 */
  50         },
  51 
  52         /* IRQ Registers */
  53         [VCPU_REG_OFFSET_IRQ] = {
  54                 USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
  55                 USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
  56                 USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
  57                 USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
  58                 USR_REG_OFFSET(12),
  59                 REG_OFFSET(irq_regs[0]), /* r13 */
  60                 REG_OFFSET(irq_regs[1]), /* r14 */
  61         },
  62 
  63         /* SVC Registers */
  64         [VCPU_REG_OFFSET_SVC] = {
  65                 USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
  66                 USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
  67                 USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
  68                 USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
  69                 USR_REG_OFFSET(12),
  70                 REG_OFFSET(svc_regs[0]), /* r13 */
  71                 REG_OFFSET(svc_regs[1]), /* r14 */
  72         },
  73 
  74         /* ABT Registers */
  75         [VCPU_REG_OFFSET_ABT] = {
  76                 USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
  77                 USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
  78                 USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
  79                 USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
  80                 USR_REG_OFFSET(12),
  81                 REG_OFFSET(abt_regs[0]), /* r13 */
  82                 REG_OFFSET(abt_regs[1]), /* r14 */
  83         },
  84 
  85         /* UND Registers */
  86         [VCPU_REG_OFFSET_UND] = {
  87                 USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
  88                 USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
  89                 USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
  90                 USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
  91                 USR_REG_OFFSET(12),
  92                 REG_OFFSET(und_regs[0]), /* r13 */
  93                 REG_OFFSET(und_regs[1]), /* r14 */
  94         },
  95 };
  96 
  97 /*
  98  * Return a pointer to the register number valid in the current mode of
  99  * the virtual CPU.
 100  */
 101 unsigned long *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num)
 102 {
 103         unsigned long *reg_array = (unsigned long *)&vcpu->arch.ctxt.gp_regs;
 104         unsigned long mode = *vcpu_cpsr(vcpu) & MODE_MASK;
 105 
 106         switch (mode) {
 107         case USR_MODE...SVC_MODE:
 108                 mode &= ~MODE32_BIT; /* 0 ... 3 */
 109                 break;
 110 
 111         case ABT_MODE:
 112                 mode = VCPU_REG_OFFSET_ABT;
 113                 break;
 114 
 115         case UND_MODE:
 116                 mode = VCPU_REG_OFFSET_UND;
 117                 break;
 118 
 119         case SYSTEM_MODE:
 120                 mode = VCPU_REG_OFFSET_USR;
 121                 break;
 122 
 123         default:
 124                 BUG();
 125         }
 126 
 127         return reg_array + vcpu_reg_offsets[mode][reg_num];
 128 }
 129 
 130 /*
 131  * Return the SPSR for the current mode of the virtual CPU.
 132  */
 133 unsigned long *__vcpu_spsr(struct kvm_vcpu *vcpu)
 134 {
 135         unsigned long mode = *vcpu_cpsr(vcpu) & MODE_MASK;
 136         switch (mode) {
 137         case SVC_MODE:
 138                 return &vcpu->arch.ctxt.gp_regs.KVM_ARM_SVC_spsr;
 139         case ABT_MODE:
 140                 return &vcpu->arch.ctxt.gp_regs.KVM_ARM_ABT_spsr;
 141         case UND_MODE:
 142                 return &vcpu->arch.ctxt.gp_regs.KVM_ARM_UND_spsr;
 143         case IRQ_MODE:
 144                 return &vcpu->arch.ctxt.gp_regs.KVM_ARM_IRQ_spsr;
 145         case FIQ_MODE:
 146                 return &vcpu->arch.ctxt.gp_regs.KVM_ARM_FIQ_spsr;
 147         default:
 148                 BUG();
 149         }
 150 }
 151 
 152 /******************************************************************************
 153  * Inject exceptions into the guest
 154  */
 155 
 156 /**
 157  * kvm_inject_vabt - inject an async abort / SError into the guest
 158  * @vcpu: The VCPU to receive the exception
 159  *
 160  * It is assumed that this code is called from the VCPU thread and that the
 161  * VCPU therefore is not currently executing guest code.
 162  */
 163 void kvm_inject_vabt(struct kvm_vcpu *vcpu)
 164 {
 165         *vcpu_hcr(vcpu) |= HCR_VA;
 166 }
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root/arch/arm/kvm/emulate.c

DEFINITIONS
